TW544574B - Memory control method - Google Patents

Memory control method Download PDF

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Publication number
TW544574B
TW544574B TW091101193A TW91101193A TW544574B TW 544574 B TW544574 B TW 544574B TW 091101193 A TW091101193 A TW 091101193A TW 91101193 A TW91101193 A TW 91101193A TW 544574 B TW544574 B TW 544574B
Authority
TW
Taiwan
Prior art keywords
memory
page
access
mode
address
Prior art date
Application number
TW091101193A
Other languages
English (en)
Chinese (zh)
Inventor
Seiji Miura
Kazushige Ayukawa
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW544574B publication Critical patent/TW544574B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
TW091101193A 2000-08-21 2001-06-26 Memory control method TW544574B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000254245A JP2002063069A (ja) 2000-08-21 2000-08-21 メモリ制御装置、データ処理システム及び半導体装置

Publications (1)

Publication Number Publication Date
TW544574B true TW544574B (en) 2003-08-01

Family

ID=18743225

Family Applications (3)

Application Number Title Priority Date Filing Date
TW091101193A TW544574B (en) 2000-08-21 2001-06-26 Memory control method
TW090115419A TWI284801B (en) 2000-08-21 2001-06-26 Memory controller, data processing system, and semiconductor device
TW093100573A TWI251739B (en) 2000-08-21 2001-06-26 Semiconductor device

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW090115419A TWI284801B (en) 2000-08-21 2001-06-26 Memory controller, data processing system, and semiconductor device
TW093100573A TWI251739B (en) 2000-08-21 2001-06-26 Semiconductor device

Country Status (4)

Country Link
US (8) US6587934B2 (https=)
JP (1) JP2002063069A (https=)
KR (1) KR100764633B1 (https=)
TW (3) TW544574B (https=)

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Also Published As

Publication number Publication date
TWI251739B (en) 2006-03-21
JP2002063069A (ja) 2002-02-28
US6542957B2 (en) 2003-04-01
US20030126392A1 (en) 2003-07-03
KR20020015266A (ko) 2002-02-27
KR100764633B1 (ko) 2007-10-08
US20020023197A1 (en) 2002-02-21
US20020053001A1 (en) 2002-05-02
US6587934B2 (en) 2003-07-01
US8024512B2 (en) 2011-09-20
US7624238B2 (en) 2009-11-24
US20060245281A1 (en) 2006-11-02
US20020035662A1 (en) 2002-03-21
US6675269B2 (en) 2004-01-06
US7076601B2 (en) 2006-07-11
US20120005421A1 (en) 2012-01-05
US20100064101A1 (en) 2010-03-11
TW200408945A (en) 2004-06-01
TWI284801B (en) 2007-08-01
US20040095818A1 (en) 2004-05-20
US6574700B2 (en) 2003-06-03
US8255622B2 (en) 2012-08-28

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