TW530455B - Switch circuit device of compound semiconductor - Google Patents

Switch circuit device of compound semiconductor Download PDF

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Publication number
TW530455B
TW530455B TW90129037A TW90129037A TW530455B TW 530455 B TW530455 B TW 530455B TW 90129037 A TW90129037 A TW 90129037A TW 90129037 A TW90129037 A TW 90129037A TW 530455 B TW530455 B TW 530455B
Authority
TW
Taiwan
Prior art keywords
compound semiconductor
electrode
fets
circuit device
electrodes
Prior art date
Application number
TW90129037A
Other languages
English (en)
Inventor
Tetsuro Asano
Hitoshi Tsuchiya
Toshikazu Hirai
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001121292A external-priority patent/JP2002314042A/ja
Priority claimed from JP2001121293A external-priority patent/JP2002314043A/ja
Priority claimed from JP2001141894A external-priority patent/JP2002343869A/ja
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Application granted granted Critical
Publication of TW530455B publication Critical patent/TW530455B/zh

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
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    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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Description

530455 A7
經濟部智慧財產局員工消費合作社印製 [發明之詳細說明] [發明所屬技術範圍] 本發明,係關於使用於高 _日 回頻開關用途的化合物半導f 開關電路裝置,特別是關於内穿 門裒有雙連開關電路的化合 半導體開關電路裝置。 [先前技術] 在行動電話等移動體用通訊撼哭 遇Λ機态中,多使用GHZ頻荀 的微波’在天線的切換電路或收送訊的切換電路等方面, 則多使用可切換此等高頻訊號的開關元件(例如,特開平 9福642號)。該元件,由於係用以處理高㈣因此㈣ 使用應用砷化鎵(GaAs)的場效電晶體(以下稱fet),因此 也促進了將前述開關電路本身積體化的單石微波積體電鲜 (MMIC)的開發。 第18圖(A)為砷化鎵金屬半導體場效電晶體 MESFET的剖面圖。在未摻雜的GaAs基板!的表面部分, 摻雜N型雜質以形成N型的通道領域2,並在通道領域: 的表面配置進行蕭特基接觸的閘極電極3,而閘極電極3 的兩侧則分別配置於GaAs表面進行歐姆接觸的源極•汲 極%極4’ 5。該電晶體’藉由閘極電極3的電位於正下^ 的通道領域2中形成空乏層,並以此控制源極電極4與这 極電極5之間的通道電流。 第18圖(B)為使用GaAs FET的被稱做為單極雙投 SPDT (Single Pole Double Throw)的化合物半導體開關電 路裝置的原理電路圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 1 313199 (請先閱讀背面之注咅?事項再填寫本頁) jI I I =0 線丨费丨 530455 A7 五、發明說明(2 ) 第1與第2FET1,FET2的源極(或汲極)分別與輸入端 子INI,IN2相連接,FET1,FET2的閘極則分別隔介電随 R1’R2與第1,第2控制端子Ctl小Ctl_2連接,而FEti, FET2的/及極(或源極)則是與共通的輸出端子out連接。 施加於第1,第2控制端子cu-i,ctl_2的訊號為互補訊 號,將施加Η位準訊號的FET予以導通,而將施加於輪入 端子IN1或IN2的任一方的輸入端子的訊號傳達至輸出端 子。配置電阻Rl,R2的目的,係在防止藉由閘極電極而 對作為交流接地的控制端子CtM,Ctl-2的直流電位漏出 南頻訊號。 第19圖係將第18圖(B)所示之化合物半導體開關電路 裝置及積體化的化合物半導體晶片的一例。 在GaA s基板上,將執行開關的FET1及FET2配置在 中央部’並在各FET的閘極電極上連接電阻ri,R2。此 外’在基板的周邊設置與輸入端子INhIN2,共通輸出端 子OUT,控制端子cn,ctl-2對應的銲墊。另外,以虛 線表示的第2層的配線,係各FET的閘極電極形成時同時 形成的閘極金屬層(鈦/鉑/金Ti/Pt/Au) 20,實線所表示的 第3層的配線係用以連接各元件及形成銲墊的銲墊金屬層 (鈦/翻/金Ti/Pt/Au) 30。在第1層的基板上,與電阻接觸 的電阻金屬層(鍺化金/鎳/金AuGe/Ni/Au)形成各FET的源、 極電極,汲極電極及各電阻兩側的取出電極,在第19圖 中,因與銲墊層重疊而未圖示出來。 第20圖(A)係第19圖所示之FET1的部分放大平面 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 313199 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -n I n I I I I 心°J· I n II ϋ I n I I ϋ ϋ- I ϋ n ϋ ϋ ϋ n n ϋ n -i«i in n n ϋ ϋ - 2 530455 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(3 ) 圖。圖巾,以點鍊線圍纟的長方形狀區域係形成於基板ι ι 的通道領域12。由左側延伸的梳齒狀的第3層銲墊金屬 層30 ’係連接輸入端子IN1的源極電極(或汲極電極), 其下方為形成於第i層電阻金屬層1〇的源極電極14(或汲 極電極)。而由右側延伸的梳齒狀的第3層的銲墊金屬層 3〇係連接共通輸出端子〇υτ的沒極電極(或源極電 極)’其下方為形成於第1層電阻金屬層10的汲極電極 16(或源極電極)。該兩電極以咬合梳齒的形狀配置,兩者 之間,形成於第2層的閘極金屬層2〇上的閘極電極”在 通道領域12上呈梳齒狀配置。 第20圖(Β)為該FET的部分剖面圖。基板u上,設 置有η型通道領域12及兩侧形成有源極領域“與汲極領 域19的η+型尚濃度領域,通道領域12中設置有閘極電極 17,而高濃度領域中則設置有形成於第U的電阻金屬層 ίο上的汲極電極14與源極電極16。此外,如前述一般y 另又設置形成於第3層的銲墊金屬層3G上的汲極電極^ 與源極電極15,以進行各元件的配線等。 此外,在組合步驟中,係將由晶圓切割分離的化合物 半導體晶片固定在引線架,並藉由運用模具與樹脂注入的 移轉模塑法,將固定在引線架上的化合物半導體晶片予以 密封,而進行依照各個化合物半導體開關裝置分離密封的 化合物半導體晶片的步驟。該引線架,多使用窄長形或環 狀的引線架,不論使用哪一種,均以一次的密封程序同 將多數個化合物體開關裝置予以密封。 ' 表紙張尺度適財關家標準(CNS)A4H (21G X 297公髮 3 313199 (請先閱讀背面之注音?事項再填寫本頁} > - -ϋ n *1 ϋ i_l ϋ'-口、I mt »ϋ n n ·ϋ 線丨· 530455 A7 B7 五、發明說明(4 ) 第21圖係藉由移轉模塑法製造上述化合物半導體曰曰 片的化合物半導體開關裝置圖,(A)為平面圖,(b)為刊面 圖。 形成開關元件的化合物半導體晶片53,係藉由銀糊等 導電性黏合劑55而固定封裝於引線架的島部54上,化人 物半導體晶片53的電極銲墊與引線端子56係藉由線 連接,而化合物半導體晶片53的周邊部分係以與模塑模具 呈一致形狀的樹脂58被覆,而引線端子56的前端部分則 導出於樹脂58的外部。 、 [本發明所欲解決的課題] 在行動電話等移動體用通訊機器中,欲利用一台的機 盗對應兩種不同的通訊方式,例如分碼多重擷取(c〇de D1Visi〇n Multiple Access) CDMA方式與全球定位衛星 (Global Positioning Satellite Gps)方式時,在用以切換高 頻訊號的開關元件方面,以使用雙電路雙連開關最具效^ 果,該效果的發揮也最受期待。 上述之化合物半導體開關電路裝置,係單電路單連開 關,單純將2組該種開關設置於同一基板上並收藏於一個 封裝體内,也會因為銷的數量、尺寸大小而無法發揮任何 優點。 料’欲將可實現電路構成共通化的各個控制端子匯 二二個時’將產生配線交叉的問題,而為了避免配線產 又叉則會發生擴增不必要的晶片面積的問題。 [解決課題的手段] t氏張尺度適用 313199 f請先閱讀背面之注意事項再填寫本頁) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 > ^ -• — 1— ϋ n ϋ ·ϋ »^^-0 V a a-^i n n I n MMm§ I I I fti_i n I I ϋ n I ϋ I n n n ϋ I ϋ ϋ «1 ϋ ϋ ϋ ϋ H _ 4 530455 A7 B7 五、發明說明(5 本發明係有鑑於上述各種問題而創作,係利用8個最 低需要量的銷來實現可利用為一組互補訊號之控制訊號進 行動作的雙電路雙連的開關元件,並藉由將晶片尺寸控制 到最小程度,以裝設於外形縮小之8個銷的封裝體中來實 現本發明。 亦即,第1,本發明係具備有:用以將在通道層表面 上裝设源極電極,閘極電極及汲極電極的第i,第2及第3, 第4FET,·與第i,第2FET的各源極電極或沒極電極相 連接的第1,第2輸入端子;與第3,第4而的各源極 電極或汲極電極相連接的第3,第4輸入端子;與第丨,第 2 FET的各汲極電極或源極電極相連接的第i共通輸出端 子,與弟3,第4 FET的汲極電極或源極電極相連接的第2 共通輸出端子,第1,第3 FET的各閘極電極及第j控制 端子予以連接的連接機構;以及用以連接第2,第4fet 的各閘極電極及第2控制端子的連接機構,並藉由對第j, 第2控制端子施加控制訊號以解決課題。 此外,其特徵為:第1,第2及第3,第4 Fet係由 與通道層進行蕭特基接觸的閘極電極;及與通道層進行歐 姆接觸的源極與汲極電極所形成。 其另一特徵為:係以MESFET形成第卜第2及第3, 第 4 FET 〇 第2 ’本發明係具備有:用以將通道層表面上裝設有 源極電極’閘極電極及汲極電極的第1,第2及第3,第4 FET ;與第1,第2 FET的各源極電極或汲極電極相連接的 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐)---- 313199 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I I I I I I I I 一^— — — — — — — — — — — — — — — — — — — — — — 一 5 530455
經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明( 第1,第2輸入端子;與第3,第4FET的各源極電極或 沒極電極相連接的第3,第4輸入端子;與第1,第2fet 的及極電極或源極電極相連接的第丨共通輸出端子;與第 3,第4 FET的汲極電極或源極電極相連接的第2共通輸 出端子;第1,第3 FET的各閘極電極及第1控制端子予 以連接的連接機構,·以及用以連接第2,第4 FET的各閘 極電極及第2控制端子的連接機構,連接機構中,用以連 接第3 FET的閘極電極與第i控制端子的連接機構,與用 以連接第2 FET的閘極電極與第2控制端子的連接機構係 刀別在杯墊與FET元件之間,沿著銲墊延伸配置,並藉由 對第1,第2控制端子施加控制訊號以解決課題。 此外’其特徵為:連接機構係由電阻所形成。 此外,其另一特徵為:連接機構的電阻係係形成於基 板上的兩》辰度領域。 此外,其另一特徵為:以連接機構的電阻,在銲墊與 FET元件之間,沿著銲墊延展配置的任何一方的電阻,係 與連接開關元件的FET的閘極電極的金屬配線交叉。 此外,其另一特徵為:在對應第丨、第2輸入端子的 各銲墊以及對應第3、第4輸入端子的各銲墊,依第卜第 2、第3、第4輸入端子的順序,沿著晶片的一邊配置在晶 片周邊部;對應第i、第2共通輸出端子的各鲜塾以及對 應第1'第2控制端子的各銲墊,依第丨控制端子、第1 八通輸出端子帛2共通輸出端子、第2控制端子的順序, I沿著晶片一邊的對邊配置於晶片周邊部 本紙張尺giTi國家鮮(CNS)A4規格⑵0 x 297公爱· 6 313199 (請先閱讀背面之注意事項再填寫本頁) >_#
11 tame ϋ 一 I ·1 »ϋ an ϋ I in in in ϋ ϋ ϋ —ϋ ϋ H ·ϋ i^i i_n ϋ ΙΒ_1 ϋ— II ·ϋ I ϋ —ϋ ϋ— n I 530455 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(7 此外,其另一特徵為:在對應第1,第2輪入端子的 各鏵墊間的晶片周邊部以及對應第3,第4輪入端子的各 辉塾間的晶片周邊部,分別配置第】,第的元件部 的一部份以及第3,帛4 FET的元件部的—部份。此外,其另一特徵為:第1,第2及第3,第4fet 係由與通道層進行蕭特基接觸的閘極電極;及與通道層進 行歐姆接觸的源極與没極電極所形成。 此外,其另一特徵為:係以MESFET形成第 及第3,第4 FET。 第3 ’本發明具備有:用以將在通道層表面上裝設源 極電極,閘極電極及汲極電極的第丨,第2及第3,第4 FET、與第1,第2 FET的|调;)¾雪拉+、立上的各/原極電極或汲極電極相連接的 第1’第2輸入端子 '與第3’第4而的各源極電極或 汲極電極相連接的第3,第4輸入端子、與第i,第 的汲極電極或源極電極相連接的第丨共通輸出端子、與第 3,第4FET的汲極電極或源極電極相連接的第2共通'輸 出端子、與第1,第3 FET的各閘極電極及第i控制端子 予以連接的連接機構;及用以連接第2,第4 fet的各門 極電極與第2控制端子的連接機構予以積體化的化合物半 導體晶片;裝設有固定化合物半導體晶片的導體圖案的絕 緣基板;對應化合物半導體晶片的各電極的多數外部電、 極;用以連接化合物半導體晶片的各電極與外部電極的連 接機構;及用以被覆化合物半導體晶片的樹脂層,並藉由 將外部電極對準絕緣基板的中心線而以左右對 9 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 第2 (請先閱讀背面之注意事項再填寫本頁) 111111. •線丨t 7 313199 530455 —B7 五、發明說明(8 置,並使之對應化合物半導 決課題。 千V體日曰片的各電極的位置,以解 此外,其特徵為:外邱雪& & π职丄 L L ^ 卜邛电極係配置在絕緣基板的背面。 此外’其另一特徵為:化人 此^ 化口物丰導體晶片係8端子元 件’並配置有8個外部電極。 此外’其另—特徵為:8個外部電極,係朝絕緣基板 二心:,以左右對稱方式分別配置4個,並沿著絕緣基 :的-邊’依照第! ’第2輸入端子及第3,第4輸入端子 、頃序配置3外又沿著絕緣基板的—邊的對邊,依照第 1控制端子’第1共通輸出端子’第2共通輪出端子,第2 控制端子的順序配置。 此外,其另一特徵為:樹脂層表面上形成有用以顯示 外部電極極性的極性顯示標記。 第4’本發明具備有:將在通道層表面上裝設源極電 極,間極電極及沒極電極的第!,帛2及第3,第4fet、 與第1’第2FET的各源極電極或没極電極相連接的第\, 第2輸入端子、與第3’第4簡的各源極電極或沒極電 極相連接的第3’第4輸入端子、與第】,第2fet的汲 極電極或源極電極相連接的第!共通輸出端子、與第3, 第4 FET的汲極電極或源極電極相連接的第2共通輪出端 子、第1,第3 FET的各閘極電極及第j控制端子予以連 接的連接機構;與用以連接第2,第4 FET的各閘極電極 及第2控制端子的連接機構予以積體化的化合物半導體晶 _片;用以埋設化合物半導體晶片及固定有該晶片的導電圖 本紙張尺度刺中關家標準(CNS)A4規格⑵Q x 297公髮) 8 it 線 313199
五、發明說明(9 ) 經濟部智慧財產局員工消費合作社印製 9 案的絕緣樹脂層;對雁仆入i ^ 从 t應化合物丰導體晶片的各電極的多數 外部電極;用以連接人 稷化a物+導體晶片的各電極與外部電 極的連接機構;並藉由 龙稭由將外部電極對準絕緣樹脂層的中心 線而以左右對稱方戎西?罢 ^ ^ 飞配置’並使之對應化合物半導體晶片 的各電極的位置,以解決課題。 此外,其特徵為:外部電極係配置在絕緣基板的背面。 此外八另特徵為:化合物半導體晶片係8端子元 件,並配置有8個外部電極。 此外,其另一特徵為:8個外部電極,係朝絕緣基板 的中。線,以左右對稱方式分別配置*個,並沿著絕緣基 板的一邊,依照第1,第2輸入端子及第3,第4輸入端子 的順序配置,另外又沿著絕緣基板一邊的對邊,依照第j 控制端子,第1共通輸出端子,第2共通輸出端子,第2控 制端子的順序配置。 此外其另一特徵為·樹脂層表面上形成有用以顯系 外部電極極性的極性顯示標記。 [發明之實施形態] 以下參照第1圖到第17圖來說明本發明之實施形態。 第1圖,為本發明之化合物半導體開關電路裝置電路 圖。係由:於通道層表面設置源極電極,閘極電極與汲極 電極的第1,第2 FET的FETal、FETa2以及第3,第4 FET 的FETbl、FETb2 ;與第1,第2 FET的各源極電極(或汲 極電極)相連接的第1,第2輸入端子的INal、INa2 ;與第 3,第4 FET的各源極電極(或汲極電極)相連接的第3,第 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 313199 ^_________^ ________________________ 530455 A7 經濟部智慧財產局員工消費合作社印製 ______B7 _ 五、發明說明(l〇 ) 4輸入端子的INbl、INb2 ;與第1,第2 FET的各汲極電 極(或源極電極)相連接的第1共通輸出端子的OUTa;與第 3,第4 FET的汲極電極(或源極電極)相連接的第2共通輸 出端子的OUTb ;用以連接第1,第3 FET的FETal、FETbl 的各閘極電極與第1控制端子的Ctl-1的電阻Ral、Rbl ; 以及用以連接第2,第4 FET的FETa2、FETb2的各閘極 電極與第2控制端子的Ctl-2的電阻Ra2、Rb2所構成。 配置電阻Ral、Ra2以及Rbl,Rb2的目的在防止介由 閘極電極而對做為交流接地的控制端子Ctl-1、Ctl-2的直 流電位漏出高頻訊號。 第 1 ’ 第 2 FET 的 FETal ' FETa2 以及第 3,第 4 FET 的 FETbl、FETb2 係由 GaAs MESFET(耗盡型(depletion type)FET)所構成,而於GaAs基板上被積體化(參照第2 圖)。此外,由於第1,第2 FET的FETal、FETa2以及第 3,第 4 FET 的 FETbl、FETb2 係與第 20 圖(A),(B)所示 構造相同,故省略說明。 第1圖所示電路,係由2組使用第18圖(B)所示之GaAs MESFET之被稱做為單極雙投SPDT (Single Pole Double Throw)的化合物半導體開關電路裝置的原理性電路所構 成’其敢大的相異點係在於將各控制端子共通化,與雙連 開關化上。 其次,參照第1圖說明本發明之化合物半導體雙連開 關電路裝置的動作。 施加於第1,第2的控制端子ctl-l,Ctl-2的控制訊 本紙張尺度適用中國國家標準(CNS)A4規格⑵G x 297公髮) ----- (請先閱讀背面之注意事項再填寫本頁) 磨
· I I I I 線 1# 10 313199 530455 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(η ) 说係互補訊號,係在施加Η位準訊號的feT導通後,將施 加於輸入端子INal或INa2的任一方的輸入訊號,以及施 加於輸入端子INbl或INb2的任一方的輸入訊號分別傳達 給共通輸出端子OUTa及OUTb。 例如’當Η位準的訊號被施加於控制端子ctl_ 1時, 開關元件的FETal,FETbl即導通,而分別將輸入端子INal 的訊號傳達至輸出端子OUTa,而將輸入端子INbl的訊號 傳達至輸出端子OUTb。其次,當Η位準的訊號被施加於 控制端子Ctl_2時,則開關元件之FETa2,FETb2導通, 而分別將輸入端子INa2的訊號傳達至輸出端子〇UTa,而 將輸入端子INb2的訊號傳達至輸出端子〇UTb。 因此,會存在2種類的訊號,欲選擇其中之一的訊號 時’例如存在行電話等移動通訊機所使用的分碼多重擷取 (Code Division Multiple Access) CDMA 方式的訊號與全球 定位衛星GPS方式的訊號,而欲選擇其一時,只要將CDMA 方式的平衡訊號(或GPS方式的平衡訊號)連接到輸入端子 INal與INbl,而將GPS方式的平衡訊號(或CDMA方式的 平衡訊號)連接到輸入端子INa2與INb2,便可由輸出端子 OUTa,OUTb的兩端配合施加於控制端子Ctl-1,Ctl-2的 控制訊號的位準,取出CDMA方式的訊號或GPS方式的 訊號。亦即,可做為雙連開關元件動作。 第2圖係將本發明的化合物半導體開關電路裝置積體 化的化合物半導體晶片的一例。 於GaAs基板上,將執行開關的2組成對的FETal, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 11 313199 (請先閱讀背面之注意事項再填寫本頁) - ( — — — — — — 1— — — — — — — — — — — ϋ — — — — — — — — — — I- 530455 經濟部智慧財產局員工消費合作社印製 12 A7 __ ___B7 __ 五、發明說明(l2 ) FETa2以及FETbl,FETb2酉己置在中央部左右,各FET的 閘極電極上連接有電阻Ral,Ra2,Rbl,Rb2。另外,與 輪入端子INal、INa2、INbl、INb2,共通輸出端子〇uTa、 〇UTb,控制端子CtM、Cti_2相對應的銲墊係設置在基板 的周邊。此外,以虛線表示的第2層的配線係形成各FET 的閘極電極時同時形成的閘極金屬層(Ti/Pt/Au)2〇,以實線 表示的第3層的配線則是用以執行各元件的連接以及銲墊 的形成的銲墊金屬層(Ti/Pt/Au)30。與第i層的基板進行電 阻接觸的電阻金屬層(八11〇6/犯/八11)1〇係用以形成各|^丁的 源極電極,汲極電極以及各電阻兩端之取出電極,在第2 圖中’因與銲墊金屬層重疊,故無圖示。 第2圖所示之將本發明化合物半導體開關電路裝置予 以積體化的化合物半導體晶片,尚具備以下所說明之種種 優點。 首先,由於與第1,第2輸入端子對應的各銲墊間的 晶片周邊部以及對應第3,第4輸入端子的各銲墊間的晶 片周邊部分別配置有第1,第2FET的元件部的一部份以 及第3,第4FET的元件部的一部份,除了可拉開成對的 輸入端子的間距之外,在晶片面積的有效利用上具有相當 效果’並有助於晶片面積的縮小化。 其次,為了分別將2組的開關的控制端子予以共通 化,必須將成對而相異的2個FET的閘極電極與控制端 子,亦即FETal,FETbl個別的閘極電極與控制端子cu_ 1以及FETa2,FETb2個別的閘極電極與控制端子〇丨_)卒 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------- 313199 (請先閱讀背面之注意事項再填寫本頁) ^-------------------------------- 530455 A7 五、發明說明(n ) 以連接。以上的連接係分別藉由電阻Rai Rb^Ra2, ㈣進行’並改良該電阻的行進方式而進行。 在控制端子Cti]的相關說明方面,與FETai的閘極 電極連接的電阻Ral,係配置在控制端子ctM及輸入端子 漏的接合銲塾間的空間内,與相異的成對FETbl的間極 電極相連接的電阻Rbl,係在控制端子CtM及輸出端子 〇UTa的接合銲墊與開關元件的FETu,叩以2之間沿著 接合銲墊延伸配置,而在晶片中央上部與砰如的間極電 極連接。 其次,針對控制端子Ctl-2進行說明,與FETb2的閘 極電極連接的電阻Rb2,係配置於控制端子cu_2及輸入 端子INb2的接合銲墊之間的空間中,與相異之成對的 FETa2的閘極電極連接的電阻Ra2 ’係在控制端子cU_2 及輸出端子OUTb的接合銲墊與開關元件的FETb2, FETbl 之間&著接合知塾延伸配置,而在晶片中央上部與 的閘極電極連接。 藉此,電阻R沿著銲墊收縮,而幾乎不增加晶片面積。 此外,由於在電阻R與FET的閘極電極的連接上係採用交 叉方式,因此無須讓電阻環繞於晶片周邊,而能夠大幅控 制晶片面積的擴大。 在此,參照第3圖以說明用以連接電阻R以及各部的 配線的多層構造。 做為控制端子與各FET的閘極電極的連接裝置使用的 電阻R,係在基板11上形成源極領域與汲極領域的同時, 本紙張尺度過用中國國家標準(CNS)A4規格(210 X 297公釐) 313199 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 --I----^ -------------------------------- 13 530455 A7 B7
五、發明說明(M ) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 於植入離子的η+型的高濃度領域4〇中形成。該η+型的高 濃度領域40的兩端設置有第Ϊ層的電阻金屬層10,其他 邛刀被覆氮化膜41,而與第1層的電阻金屬層1〇接觸的 第3層的銲墊金屬層30則是在形成汲極電極與源極電極的 同時被設置。此時,因為連接各部的配線,例如連接電阻 Rbi的一側的端子與FETbl的閘極電極的端子的配線〇 於同時作成,故配線42與電阻Ra2可藉由氮化膜41實 現層間絕緣及交又配置。 、 另外,第4圖係將化合物半導體晶片119組裝於封裝 體而形成之化合物半導體晶片開關電路裝置圖示,(a)為^ 面圖,(B)為剖面圖。 化合物半導體晶片i 19的各電極係依照第2圖所示順 =配置,化合物半導體晶片丨19的各電極,係分別藉由接 〇線13 7引線部丨3 5,通孔i 3 3而與各位置相對應位置的 外部電極134進行電連接。 亦即以虛線表示之8個外部電極134,係朝絕緣基板 122的中心線,以左右對稱方式分別配置4個,並沿著絕 緣基板122的一邊,依照第1,第2輸入端子及帛3,第4 輸入端子的順序配置,另外又沿著絕緣基板122的一邊的 對邊,依照第1控制端子,帛!共通輸出端子,第2共通 輸出端子,第2控制端子的順序配置。 封裝體的周圍4側面,係由樹脂層138與絕緣基板122 的切副面开v成,封裝體上表面係由平坦化的樹脂層⑶的 形成’而封裝體的下表面則是以絕緣基板122的背面 本紙張尺度適用中關家標準(CNS)A4規格⑵G χ " 14 313199 f靖先閱讀背面之注音?事項再填寫本頁) Ύ - * — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 530455 B7 五、發明說明(15 側形成。 該化合物半導體開關電路裝置,係在絕緣基板122之 上被覆大約〇.3mm的樹脂層138以密封化合物半導體晶片 119。化合物半導體晶片119約有130μπι的厚度。島部125 與引線部 135a,13 5b,13 5c,135d 及 135e,135f,135g, 135h係位置於封裝體端面後方,只有各引線的連接部的切 斷部分露出於封裝體側面。 此外’封裝體表面侧為全面樹脂層138,背面側的絕 緣基板122的外部電極134a,134b,134c,134d及134e, 134f’ 134g,13411係以左右(上下)對稱的圖案配置,將使 電極的極性判斷變得困難,因此理想上最好在樹脂層138 的表面側形成凹部或印刷,並刻印表示極性標記。 接著,使用第5圖到第7圖,以詳細說明形成第4圖 所示構造的製造方法例。 第1步驟: 首先,準備如第5圖所示一般,朝縱橫方向配置多數 個,例如1 〇〇個對應丨個化合物半導體開關電路裴置的封 衣項域120的整片的絕緣基板122。絕緣基板122係由陶 瓷或玻璃環氧樹脂等形成的絕緣基板,在該些基板上重疊 1張或數張,而使合計板厚達到18〇至25〇μιη,以取得能 夠維持製造工程中的機械強度的板厚。 絕緣基板122的各封裝領域12〇的表面,形成鎢等金 2糊的印刷,及藉由金的電解電鍍所形成的導電圖案。這 j 由燒成完成各種金屬糊印刷的絕緣基板122,並
木標準(CNS)A4 規格⑵〇 x 297l:iT 313199 (請先閱讀背面之注意事項再填寫本頁) -------訂---------- 經濟部智慧財產局員工消費合作社印製 15 530455 B7 五、發明說明(1ό ) 藉由!解電鑛法於金屬糊上形成金電鍍層來取得。 弟6圖⑷為形成於絕緣基板122表面的導電圖案平面 圖’第6圖(B)為形成於絕緣基板122背面側的導電圖 面圖。 、 以虛線圍起的各封裝領域12〇,具有矩形形狀,該些 /相互以lGGgm的間隔朝縱橫方向配置。間隔形成其後 、、程序中的切割線124。導電圖案在各封裝領域12〇中形 成島部125與引線部135,該些圖案在各封裝領域120中 為同形狀。島部125係搭載化合物半導體晶# ιΐ9的位 置所在而引線部135為與化合物半導體晶片⑴的電極 銲墊進行接合線連接的部位。 兩條第1連結部127係利用連續圖案自島部125延伸 出來。該些線寬係以較島部125為窄的線寬,例如以。5醜 的線寬延伸配置。第!連結部127,越過切割線i24繼續 延伸至可與旁側的封裝領域12〇的島部125連接的位置。 而第1連結部127,則更進一步與包圍封裝領域的12〇的 周圍的共通連結部132相連接。 此外,各個第2連結部12 8係由引線部丨3 5,朝與第工 連結部127正交的方向延伸配置,並越過切割線124繼續 延伸至與旁側的封裝領域120的引線部135相連接的位 消 置,各相互鄰接的第2連結部128,更藉由第3連結部Up 於切割線124中連接。 另外’各個第4連結部130,則由位於封裝領域12〇 _内一邊的兩側引線部135,以與第1連結部127平行,而 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 16 線 313199 530455 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(Π ) 與第2連結部128正交的方向延伸,並越過切割線⑶延 伸至與旁側的封裝領域12〇的引線部135相連接的位置。 第4連結部130,則與包圍封裝領域12〇的周圍的妓通連 結部m相連接。此外’第4連結部13〇,更藉由第5連 結部131,於切割線124内與第i連結部127連接。 如此’藉由第1、第2、第3、第4、第5連結部127、 128、129、13〇、131的延伸’可讓各封裝領域12〇的島部 125與引導部135進行電連接。 參照第6圖(B) ’可知絕緣基板122上,係依照各封裝 領域12〇設置通孔133。通孔133内部由鎢等導電材料所 埋設。其背面,又對應各通孔133形成外部電極13“, 134b,134c,md,以及 134e,134f,134g,134h。該些 外部電極 134a,134b,134C,134d,以及 134e,134f,134g, 134h,係形成於從封裝領域12〇的端側向後退約〇 〇5至 0.1 mm的圖案上。並以電性方式介由各通孔而與共通連結 部132相連接。 然後,藉由將導電圖案做為一方的電極的電解電鑛, 於導電圖案上形成金電鍍層。由於各導電圖案係介由共通 連結部132進行電連接,故可使用電解電鍍的方法。 第2步驟:參照第7圖(A) 如此’在形成金電鍍層的絕緣基板122的各封裝領域 120’進行化合物半導體晶片up的晶粒黏合,接合線黏 合。化合物半導體晶片11 9藉由銀糊等黏合劑固定於島部 125表面,並利用各接合線ι37連接化合物半導體晶片119
17 313199 530455 五、發明說明(μ ) 的電極銲墊與引線部135a,135b,U5c,U5d及13&, 135f,135g,135h。 第3步驟:參照第7圖(B) 耩由移送至絕緣基板122上方的供料器(無圖示)滴下 (/瞿注)預定置的環氧液體樹脂,而以共通的樹脂層被 覆化合物半導體晶片119全面。例如在!片絕緣基板122 上搭載100個化合物半導體晶片119時,將1〇〇個全部的 化合物半導體晶片119全面被覆。液體樹脂,係使用例如 CV576AN(松下電工製)。由於所滴下的液體樹月旨黏性較 咼,且具有表面張力,故其表面呈彎曲。 第4步驟:參照第7圖(c) 消 訂 將樹脂層138的彎曲表面加工成平坦面。在加工方法 上,可考慮使用:在樹脂硬化前藉由推押平坦之成形構件 加工成平坦面的方法,及對滴下之樹脂層138進行1〇〇至 200度,數小時的熱處理固化(硬化)使之硬化後,再藉由研 削其彎曲面加工成平坦面的方法。在研削方面,係使用研 磨裝置,研削樹脂層138表面,使樹脂層138表面能自絕 緣基板122達到一定之高度。平坦面,為了能夠在至少位 於最外側的化合物半導體晶片丨丨9自個別的化合物半導體 開關電路裝置分離時構成尺寸化的封裝體大小的樹脂外 形,而擴展到其端部。在刀片方面準備有各種厚度的刀片, 可藉由使用較厚的刀片反覆多次切削動作而使全體形成平 坦面。 I 第5步驟··參照第7圖(D) 1本紙張尺度適用中i國家標準Τ^Γ4規格(21〇x 297公餐) 313199 18 530455 B7 五、發明說明( 19 Μ !f:在各封裝㈣120中切斷樹脂層138而分離成 各化&物半導體開關電路 酤嬰^ 在切斷程序上係使用切割 裝置,利用切割刀片n Q、、儿 你 /口者切口彳線124同時切斷樹脂層 138與絕緣基板122,藉 褙 成依照各封裝領域120 力割的,合物半導體開關電路裝置。在切割步驟中,基板 122的力面貼有藍薄板(例如’商品名:—薄板,^ntec ,份有限公司製)並以切割刀片可到達藍薄板背面的切削 深度進行切斷。此時,裨由切 ^係由切割裝置自動辨識預先形成於 絕緣基S 122表面的接合標?己,並以此做為位置基準以進 行切割。 依照上述程序形成之化合物半導體開關電路裝置如第 4圖所示。 此外,參照第8圖到第16圖,以說明本發明之封裝體 構造的第2實施形態。第8圖為封裝體的剖面圖,因平面 圖與第4圖(A)及第6圖(A)所示之第!形態相同,故省略 說明。此乃將第1實施形態中的csp予以多晶片模組化而 成,其構造係將導電圖案埋設於成為支撐基板的絕緣性樹 脂中。 成為支撐基板的絕緣性樹脂220,將半導體晶片222 及多數的導電圖案(引線)221完全被覆,在引線221間的分 離溝231中填入絕緣性樹脂220,並與引線221的側面的 彎曲構造(雖省略圖示,但實際上其引線側面係呈彎曲狀) 欲合並牛固地結合。而引線2 2 1係藉由絕緣樹脂2 2 0所支 撐。由於被固定在形成島部的引線22 1A上的半導體晶片 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 313199 ------------- c請先閱讀背面之注意事項再填寫本頁)
訂---------線L 經濟部智慧財產局員工消費合作社印製 19 530455 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明(20 ) 222也一同被覆,並被統一模塑之故,而形成引線221及 半導體晶片222被埋設於絕緣樹脂220中的構造。在樹脂 材料上,環氧樹脂等熱硬化性樹脂可利用移轉模塑法實 現,聚銑亞胺樹脂,聚苯醚硫化物(polyphenylane sulfide^) 等熱可塑性樹脂可藉由射出成形來實現。 絕緣性樹脂220的厚度,可調整為可由半導體晶片222 的接合線225的最頂部被覆約50μηι的程度。該厚度可依 照所需強度增厚或削薄。 接合線225係用以連接半導體晶片222的各電極銲墊 和各引線22 1。藉由熱壓接之球形接合或超音波之楔形接 合同時進行引線接合,並將控制端子Ctrl-1,Ctrl-2,輸入 端子 INal,INbl,INa2,INb2,輸出端子 0UTa,〇UTb 連接各引線221。 導電圖案(引線)221B係對應配置在半導體晶片222外 圍的電極輝墊而設置。半導體晶片221係利用絕緣性黏合 劑250固定在島部221A。此外,被埋設於絕緣樹脂22〇 中’而導電圖案22 1的背面則露出於絕緣樹脂220。 半導體晶片222,係與第2實施形態相同,故省略其 詳細說明,在此,係一種化合物半導體的開關電路裝置, 其背面為半絕緣性的GaAs基板。由於係一種雙連開關電 路裝置,在晶片表面上,與控制端子CM」,Ctd_2,輸入 端子 INal,INbl,INa2,INb2,輪出端子 〇UTa,〇UTb 連接的8個電極銲墊係以包圍晶片外圍的方式配置,並利 用各接合線225連接電極銲墊及引線221B 〇此外,導電圖 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公爱) 20 313199 (請先閱讀背面之注意事項再填寫本頁) 0 1111111· ^^ I — — — — — — — — — — — — — — — — — — — — — — — 530455 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(21 ) 案22 1,半導體晶片222的gj $ >§ # ^ J 口疋領域,接合線225的 位置係與第4圖相同。 、 外部電極226,與半導體曰H 守餵日日片222的各電極相對應, 並以絕緣樹脂層220的中心飨盔 罢Λ义 ^線為準,以左右對稱方式各配 置4個,並沿著絕緣樹脂層 曰增220的一邊,依照第j,第2 的輸入端子及第3’第4的輪人端子的順序配置,另外又 沿著絕緣樹脂層的一邊的對邊,依照第】控制端子,第丄 共通輸出端子,第2共通輪ψ ,、遇縣)出鳊子,第2控制端子的順序 配置。以抗蝕劑227被覆導電圖案的各引線221,在適當 的位置上設置開π供給焊錫,並設置於絕緣樹脂層22〇背 面。藉此,可在安裝時藉由焊錫等的表面張力直接朝水平 方向移動並自行調整。 此外,封裝體表面側為全面樹脂層22〇,而背面側的 外部電極226,係以左右(上下)對稱之圖案配置,而不易進 行電極的極性判斷,因此最好是在樹脂層22〇的表面形成 凹部或印刷等,並刻印表示極性的標記。 參照第9圖到第16圖,以詳細說明本發明之第2實施 形態的製造方法例。 第1步驟: 首先’如第9圖到第11圖所示,準備導電箔23〇。於 除了至少形成複數個半導體晶片的封裝領域之導電圖案 221領域之導電箔230上,經由蝕刻而形成比導電箔230 之厚度略淺的分離溝231後,再形成導電圖案221。 如第9圖(A)所示,準備薄片狀的導電箔23〇。該導電 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐 21 313199 C請先閱讀背面之注音?事項再填寫本頁} * - ^l°Ja I H ϋ ϋ ϋ - -- - I I n i I 1_1 ϋ -ϋ ϋ I I ϋ ϋ ϋ ϋ ϋ ^1 i^i ί n n ϋ -
經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明(η ”在考慮焊料的附著性,接合性,電鍍性的前提下選擇 ,、材料,在材料方面,採用主要材料為Cu的導電菌,主 要材料為A1的導電箔或由卜⑻等合金所形成的導電辖等。 右考慮其後執行的蝕刻,則導電箔23〇的厚度以1(^m 至300从〇1程度的厚度為宜,在本發明中係採用 ⑽nce(英兩)盎司)的鋼箔。但是基本上在以上或 ΙΟμιη以下均可。如後述一般,最好能夠形成較導電箔 的厚度淺的分離溝231。 此外,可預先將片狀的導電箔230,以預定的寬度捲 成例如45mm的圓筒狀,再搬送至後述各步驟,或預先將 導電箱切割成預定的大小的窄長形後再搬送到後述的各步 驟中。 具體而言,如第9圖(B)所示,在窄長形的導電箔23〇 中以間隔方式排列多數個(在此為4至5個)形成多數封裝 領域的組件單元232。各組件單元232之間,設有縫隙233, 用以吸收進行模塑步驟等之加熱處理時所產生的導電箔 230的應力。此外,分度孔(index h〇le)234在導電箔 的兩側以一定之間隔設置,係使用於各步驟的定位上。 接著,形成導電圖案。 首先,如第10圖所示,在Cu箔23〇上,形成光阻劑 (耐蝕刻遮罩)PR,並將光阻劑PR圖案化使形成導電圖案 221領域之外的導電箔230可露出。此外,如第^圖仏) 所示,介由光阻劑PR選擇性地進行導電箔23〇的蝕刻。 本紙張尺度適用中國國€標準(CNS)A4規格(210 X 297公爱) 22 313199 (請先閱讀背面之注意事項再填寫本頁) 事 訂---------線- 530455 A7 五、發明說明(23 ) 在本V驟中,為了使藉由餘刻而形成的分離溝231的 深度平均且具有高精度’如第11圖(A)所示,乃將分離:盖 231的開口部朝下’而由設置在導電箔23〇下方的蝕刻液 的供給管260將蝕刻液朝上方喷灑。其結果接觸到蝕 液的刀離溝23 1的部分被予以蝕刻,#由於蝕刻液並不 殘留在分離溝231内而直接被排出,分離溝231的深度可 以钱刻時間控制,而得以形成平均且具有高精度的分離溝 231。此外,蝕刻液主要係採用氯化鐵或氯化鋼。 第11圖(B)係表示具體的導電圖案221。本圖為第9 圖(B)所示之一個組件單元232的放大圖。虛線所示部分為 1個封裝領域235,構成導電圖案22卜並在一個組件單元 232中以矩陣狀配列多數封裝領域235,並在每一封裝領域 235上設置相同的導電圖案221。 一 第2步驟: 線 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 其次,如第12圖所示,半導體晶片222,在導電圖案 221的島部221A進行晶粒黏接,並藉由夾具(無圖示)固定 在導電猪230的組件單元232的周緣,使導電箱23〇與加 熱單疋(無圖示)密接。之後,如第13圖所示,利用接合線 225並藉由熱壓接之球形接合或超音波之楔形接合,對分 別對應各電極銲塾的引線22 1B,同時進行引線接合處理。 藉此,與在各封裝領域中使用夾具進行引線接合的習知的 電路裝置的製造方法相比,能夠更有效地進行引線接合。 第3步驟: 在本步驟f ’如第14圖(A)所示,絕緣性樹脂層22〇 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公餐) 23 313199 530455 A7 ---—-------B7______ 五、發明說明(Μ ) (請先閱讀背面之注意事項再填寫本頁) 係藉由移轉模塑法或射出成形法將半導體晶片222及導電 圖案221完全覆蓋,並在導電圖案221間的分離溝23丨中 充填絕緣性樹脂220,而與導電圖案221的側面的彎曲構 造嵌合並緊密結合。而導電圖案221係由絕緣性樹脂220 所支撐。 此外,如第14圖(B)所示,在導電箔230表面上依照 每一集合組件單元232形成絕緣性樹脂層220。其結果, 將在導電箔230表面形成多數個絕緣性樹脂220。 另外,在絕緣性樹脂220形成後,再對絕緣性樹脂220 進行加熱,藉由退火處理來保持絕緣性樹脂22〇表面的平 坦性。當絕緣性樹脂220形成具有寬闊面積時,特別會因 為導電箔230與形成絕緣性樹脂220的模塑樹脂之間的熱 膨脹係數或迴流焊接(refl〇w)後在溫度降低下所產生的成 开> 收縮率的不同而使導電箔2 3 0產生翹^曲。結果將導致絕 緣性樹脂2 2 0表面也產生彎曲。此時,如上述一般,將絕 緣性樹脂220再予加熱,並藉由退火處理來形成絕緣性樹 脂2 2 0表面的平坦性。 經 濟 部 智 慧 財 產 局 員 工 消 t 合 作 社 印 製 此外’在本實施形態中,係針對導電箔2 3 〇的情況進 行就明’但是當基板係由石夕晶圓,陶莞基板,銅架等材料 形成時,其狀態亦同。 第4步驟: 本步驟,如第15圖所示,係利用化學或物理方式將導 電治230的背面予以去除,並分離以做為導電圖案221。 本步驟,係藉由研磨,磨削,蝕刻,雷射之金屬蒸發等處 本紙張尺度適用中國國家標準(CNS)A4規格⑵G X 297公爱) 24 313199 530455 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(25 ) 理實施。 實驗中’係藉由研磨裝置或磨削裝置對全面進行約 3〇μπι的磨削,而讓絕緣性樹脂22〇自分離溝ay中露出 其露出之面,在第14圖⑷中係以虛線表示。其結:: 成厚度約40μηχ的導電圖荦221 rfft八銳: ; 叼彳电口系“ i而分離。此外,亦可 緣性樹脂220露出之前,對導電箱咖行全面濕性飯刻後, 介由研磨或磨削裝置磨削全面,而使絕緣性樹脂22〇露 出。另外,亦可對導電箱230進行到達第14圖(八)之虛線 所不位置為止的全面性濕性蝕刻,而使絕緣性樹脂“Ο露 出。 路 其結果,形成導電圖t 221的背面露出於絕緣性樹脂 220的構造。亦即,充填於分離溝231的絕緣性樹脂 的表面與導電圖案221的表面,在實質上形成一致的構 造。因此,本發明的半導體裝置,具有:在安裝時可利用 焊錫等之表面張力直接朝水平方向移動進行自動調整的特 徵。 此外,可進行導電圖案221背面處理以獲得第8圖所 示之最終構造。亦即,根據需要在所露出的導電圖案221 上覆蓋焊錫等導電材以完成半導體裝置。 於前述步驟中進行導電箔230的背面蝕刻後,由導電 镇230將各組件單元232切斷。該組件單元232係利用絕 緣性樹脂220而與導電箔230的殘餘部連接,因此無須使 用切割模具便可機械式地將組件單元由導電箔2 3 〇的殘餘 部剝除。 本紙張尺度過用甲國國豕標準(CNS)A4規格(210 X 297公爱) 25 313199 (請先閱讀背面之注意事項再填寫本頁) -«1 ·_1 H ϋ MmMmm n^OJB n n ai_— n -線« 530455 A7
經濟部智慧財產局員工消費合作社印製 各組件單元232的背面中,如第15圖⑺)所示,露出 導電圖案221的背面,而各封裝領域235與形成導電圖案 221時一樣呈矩陣狀配置陳列。利用探測器探測由該導電 圖案221的絕緣性樹脂220露出的外部電極226,以個別 測定各封裝領域235的半導體晶片222的特性參數等,並 進行其優劣判斷,對於不良品則利用磁性墨水予以標示。 由於在本步驟中,無須進行傳統所需之電路裝置的表背判 別’及電極位置的辨識等,故可大幅縮短測定時間。 第5步驟: 在本步驟中,如第16圖,利用真空將組件單元232 吸附在切割裝置的載置台,利用切割刀242沿著各封裝領 域235間的切割線241切割分離溝23!的絕緣性樹脂22〇, 並分離成個別的電路裝置223。 在本步驟中’切割刀242以大致可切斷絕緣性樹脂220 的切削深度進行切割,並由切割裝置取出組件單元2 3 2後 以滾輪進行格塊分離。切割時,先辨視定位標記237,並 以此為基準進行切割。如一般所知,切割係朝縱方向切割 所有的切割線241後,將載置台旋轉90度而朝橫向切割線 241進行切割。 藉由上述步驟形成之第2實施形態的特徵為:在被覆 絕緣性樹脂220前,係以形成導電圖案221的導電箱23〇 做為支撐基板,做為支撐基板的導電箔23〇係做為電極材 料的必要材料。因此,具備有可大幅節省構成材料即可進 行作業的優點,而能夠達到成本降低的目的。
26 313199 (請先閱讀背面之注意事項再填寫本頁) Ψ;0
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五、發明說明( 經濟部智慧財產局員工消費合作社印製 此,導t於刀離溝231較導電辖230之厚度為淺,因 伯30並未分離為各個導電圖案221。因此,且 有:在一體做為片狀的導電箔23〇 八 r 包,白230使用,而進行絕緣性樹 月日220板塑時,可使搬送至模 女裝至模具的作業變得 極為輕鬆的特點。 ―、另外’在本實施形態中,係針對導M230的情況進 仃說明’但是當基板係由石夕晶圓,陶甍基板,銅架等材料 形成時,其狀態亦同。 第17圖為本發明之化合物半導體開關電路裝置的應 用例。 根據本發明,係沿著銲墊配置電阻R,藉由將交叉方 法運用在電阻R與FET閘極電極的連接上,^將2組獨立 的開關電路的個別的控制端子共通化。亦即,由於可藉由 與第2圖所示之銲墊配置相同的配置取出外部連接用電 極,故可簡化用以安裝本發明巾的化合物半導體開關電路 裝置的印刷基板的設計。 如第17圖所示,有2種類的輸入訊號,在使用本發明 之化合物半導體開關電路裝置選擇任何一方的訊號時,印 刷基板的配線’可只利用早一處的交又進行設計。亦即可 對INal ’ INb 1輸入A尺寸的訊號,而對wa2,iNb2輸入 B尺寸的訊號’並對應施加Ctl-l,Ctl-2互補訊號的控制 訊號的位準’由輸出端子OUTa’OUTb取出並利用a尺寸 或B尺寸的訊號。 [發明之效果] 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 27 313199 (請先閱讀背面之注咅?事項再填寫本頁) - 一 or I ϋ ϋ 1_1 ϋ n n Βϋ I 1 ϋ ·ϋ ϋ n ϋ n -1 -ϋ ·1 ·ϋ ϋ ϋ I ϋ ϋ ϋ ϋ ϋ ^1 530455 經濟部智慧財產局員工消費合作社印製 28 A7 B7 五、發明說明(28 ) 如以上詳述一般,藉由本發明可獲得以下各種效果。 第1,可使用化合物半導體開關元件的GaAs MESFET,而以1組的控制端子,構成可執行獨立之雙電 路的開關動作的雙連開關電路裝置。藉由該裝置,會存在 例如應用於行動電話等移動體通訊機的分碼多重擷取 CDMA方式的訊號及全球衛星定位系統Gps方式的訊號, 在選擇其中一個訊號時,可簡化電路配置並縮小印刷基板 的安裝面積。 * 第2,内建2個獨立的開關電路,因將其控制端子共 通化,可使其封裝體尺寸小型化,比使用2個單一開關電 路裝置,更能縮小印刷基板的安裝面積。 第3,由於在用以連接控制端子與開關元件FET的閘 極電極的電阻R的配置上進行改良,同時係沿著接合銲墊 在接合銲墊與開關元件FET之間做延伸配置,故幾乎不會 增加晶片面積。 第4 ’將2組的開關電路的控制端子共通化並設置為ι 組時,在連接控制端子與開關元件的閘極電極時,為避開 交叉而必須在銲墊外侧圍繞配線,而在不必要的狀況下擴 增晶片面積,但在改良用以連接的電阻與連接用的金屬配 線的配置後,可使兩者進行立體式交叉而不會增加晶片面 積。 第5,因抑制銷的數量的增加,並使之形成較使用引 線架的封裝體更小型化的封裝冑,且5|線端子不冑出的構 造二故可的佔有面積,以達成高密度的封裝 ^紙張尺度翻中咖家鮮(CNS)A4規格⑵Q χ 公髮) 313199 (請先閱讀背面之注意事項再填寫本頁) 訂---------線—▲ A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(29 [圖面之簡單說明] 第1圖為用以說明本發明的電路圖 第2圖為用以說明本發明的平面圖 第3圖為用以說明本發明的剖面圖 第4圖為用以說明本發明的(A)平面 ^ 5圖為用以說明本發明的斜視圖 弟6圖(A)及⑻為用以說明本發明的平面圖。 第7圖(A)至(D)為用以說明本發明的剖面圖。 第8圖為用以說明本發明的剖面圖。 第9圖(A)及(B)為用以說明本發明的平面圖。弟10圖為用以說明本發明的剖面圖。 第11圖為用以說明本發明的(A)剖面圖及平面圖 第12圖為用以說明本發明的(A)剖面圖及(B)平面圖 第13圖為用以說明本發明的(A)剖面圖及(B)平面圖 第14圖為用以說明本發明的(A)剖面圖及(b)平面圖 第15圖為用以說明本發明的剖面圖及(B)平面圖 第16圖為用以說明本發明的平面圖及(b)剖面圖 弟1 7圖為本發明之應用例顯示圖。 第18圖為用以說明先前技術的(a)剖面圖及(b)電路 第19圖為用以說明先前技術的平面圖。 第20圖為用以說明先前技術的(A)平面圖及(B)剖面 圖及(B)剖面圖 (請先閱讀背面之注意事項再填寫本頁) -------訂---------線I應 圖 圖 第21圖為用以說明先前技術的(A)平面圖及(b)剖面 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公釐) 29 313199 I ϋ H · A7 B7
1、發明說明(30 ) 經濟部智慧財產局員工消費合作社印製 _ 〇 [元件符號說明] 1 基板 3 閘極電極 10 電阻金屬層 13、14 汲極電極 17 閘極領域 19 没極領域 30 銲墊金屬層 53 > 119 化合物半導體晶片 55 導電性黏合劑 57 線 120 封裝領域 124 切割線 128 第2連結部 130 第4連結部 132 共通連結部 134a 至 134h、226 135a 至 135h 137 ^ 225 接合線 139 切割刀片 221 引線 221B 導電圖案(引線) 223 ^ 233 縫隙 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 2 ' 12 通道領域 4 ' 5 源極/汲極電極 H 基板 15、16 源極電極 18 源極領域 2〇 閘極金屬層 42 配線 54 、 125 島部 56 引線端子 58 樹脂 122 絕緣基板 127 第1連結部 129 第3連結部 131 第5連結部 133 通孔 外部電極 W線部 138 樹脂層 220 絕緣性樹脂 221A 島部的引線 222 半導體晶片 227 抗餘劑 (請先閱讀背面之注意事項再填寫本頁) r -
_ ·ϋ ϋ ϋ n ·ϋ ϋ 1 I ϋ ϋ n ϋ n ϋ ϋ ·ϋ I in -H ^1 ·-1 ϋ· n i-i ϋ i^i ϋ -ϋ I 30 313199 530455 A7 _B7_ 五、發明說明(31 ) 230 導電箔 231 分離溝 232 組件單元(Block) 234 分度孔(index hole) 235 封裝領域 237 定位標記 241 切割線 242 切割刀 250 絕緣性黏合劑 260 供給管
Ctl-1、Ctl-2、Ctrl-1、Ctrl-2 控制端子 INal、INa2、INbl、INb2 輸入端子 OUTa、OUTb 輸出端子 PR 光阻劑 R、Ral、Ra2、Rbl、Rb2 電阻 (請先閱讀背面之注意事項再填寫本頁) 麝 經濟部智慧財產局員工消費合作社印製 訂------- -!線 --------- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 31 313199

Claims (1)

  1. 530455 六 申請專利範圍 L 一種化合物半導體開關電路裝置,具備有:用以將在通 道層表面上裝設源極電極,閘極電極及汲極電極的第 卜第2及第3,第4FET;與前述第!,第2FET的各 源極電極或汲極電極相連接的第丨,第2輸入端子;與 刖述第3,第4 FET的各源極電極或汲極電極相連接的 第3,第4輸入端子;與前述第i,第2 FET的汲極電 極或源極電極相連接的第丨共通輸入端子;與前述第 3第4 FET的沒極電極或源極電極相連接的第2共通 輸入端子;前述第1,第3 FET的各閘極電極及第!控 制知子予以連接的連接機構;以及用以連接前述第2, 第4 FET的各閘極電極及第2控制端子的連接機構,並 對刖述第1,第2控制端子施加控制訊號。 2·如申請專利範圍第1項之化合物半導體開關電路裝置, 其中,前述第1,第2及第3,第4FET,係由與前述 通道層進行蕭特基接觸的閘極電極;與前述通道層進行 歐姆接觸的源極與汲極電極所構成的。 3 ·如申哨專利範園第1項之化合物半導體開關電路裝置, /、中’刖述第1,第2及第3,第4 FET,係由MESFET 所形成。 一種化合物半導體開關電路裝置,具備有··用以將在通 道層表面上裝設源極電極,閘極電極及汲極電極的第 1第2及第3,第4 FET ’·與前述第1,第2 FET的各 源極電極或汲極電極相連接的第1,第2輸入端子;與 則述第3,第4 FET的各源極電極或汲極電極相連接的 訂 參 4. 本紙張尺度適用中國國家標準(CNS)A4規格(21G X 297公董) 313199 530455 A8B8C8D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 第3,第4輸入端子;與前述第1,第2 FET的各汲極 電極或源極電極相連接的第1共通輸出端子;與前述第 3 ’第4 FET的汲極電極或源極電極相連接的第2共通 輪出端子;與前述第1,第3 FET的各閘極電極及第、 控制端子予以連接的連接機構;以及用以連接前述第 2 ’第4 FET的各閘極電極及第2控制端子的連接機構, 在前述連接機構中,連接前述第3 FET的閘極電極與前 述第1控制端子的連接機構與連接前述第2 FET的閘極 電極與前述第2控制端子的連接機構,係分別在銲墊與 FET元件之間沿著銲墊延伸配置,對前述第1,第2控 制端子施加控制訊號。 5·如申請專利範圍第4項之化合物半導體開關電路裝置, 其中’前述連接機構係由電阻所形成。 6.如申請專利範圍第4項之化合物半導體開關電路裝置, 其中’刖述連接機構的電阻係在基板上的高濃度區域中 形成。 7·如申請專利範圍第4項之化合物半導體開關電路裝置, 其中’作為前述連接機構的電阻,並在銲墊與Fet元 件之間沿著銲墊延伸配置的任一方的電阻,係與連接前 述開關7〇件的FET的閘極電極的金屬配線相互交叉。 8·如申凊專利範圍第4項之化合物半導體開關電路裝置, 其中’對應前述第1,第2輸入端子的各銲墊與對應前 述第3’第4輸入端子的各銲墊,係按照第1,第2, 第3 ’第4輸入端子的順序沿著晶片的一邊配置在晶片
    33 313199 (請先閲讀背面之注意事項再填寫本頁) » -裝 訂--------- P 530455 A8 B8 C8 D8 六、申請專利範圍 周邊部’對應前述共通輸出端子的各銲墊以 及對應刚述第1,第2控制端子的各銲塾,係按照第1 控制端子,f i共通輸出端子,第2共通輸出料,第 2控制端子的順序,沿著前述晶片的一邊的對邊配置在 晶片的周邊部。 9·如申請專利範圍第4項之化合物半導體開關電路裝置, 其中,對應前述第1,第2輸入端子的各銲墊間的晶片 周邊部以及對應前述第3,第4輸入端子的各銲墊間的 晶片周邊部,分別配置有第1,第2 FET的元件部的一 部份以及第3,第4 FET的元件部的一部份。 10·如申请專利範圍第4項之化合物半導體開關電路裝 置,其中,前述第1,第2以及第3,第4FET係由與 前述通道層進行蕭特基接觸的閘極電極;及與前述通道 層進行歐姆接觸的源極與汲極電極所構成。 11·如申請專利範圍第4項之化合物半導體開關電路裝 置,其中,前述第1,第2及第3,第4 FET係由MESFET 所形成。 12·—種化合物半導體開關電路裝置,具備有··用以將在通 道層表面上裝設源極電極,閘極電極及汲極電極的第 1,第2及第3,第4 FET、與前述第1,第2 FET的各 源極電極或汲極電極相連接的第1,第2輸入端子、與 前述第3,第4 FET的各源極電極或汲極電極相連接的 第3’第4輸入端子、與前述第1,第2 FET的各汲極 電極或源極電極相連接的第1共通輸出端子、與前述第 (請先閱讀背面之注意事項再填寫本頁) -裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 34 313199 530455 金!
    六、申請專利範圍 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 3 ’第4 FET的汲極電極或源極電極相連接的第2共通 輪出端子、與前述第1,第3 FET的各閘極電極及第1 控制端子予以連接的連接機構;與用以連接前述第2, 第4 FET的各閘極電極與第2控制端子的連接機構予以 積體化的化合物半導體晶片; 裝設有固定前述化合物半導體晶片的導體圖案的 絕緣基板; 對應前述化合物半導體晶片的各電極的多數外部 電極; 用以連接前述化合物半導體晶片的各電極與前述 外部電極的連接機構;及 用以被覆前述化合物半導體晶片的樹脂層, 而將前述外部電極對準絕緣基板的中心線而以左 右對稱方式配置,並使之對應前述化合物半導體晶片的 各電極的位置。 i3·如申請專利範圍第12項之化合物半導體開關電路裝 置,其中,前述外部電極係被配置在前述絕緣基板 面0 14·如申請專利範圍第12項之化合物半導體開關電路裝 置,其中,前述化合物半導體晶片為8端子元件,且 備有8個前述外部電極。 、/、 15.如申請專利範圍第12項之化合物半導體開關電路裝 =中’前述8個外部電極,係以前述絕緣 〜線為中心而以左右對稱方式分別配置4 甲 _____ 並沿著絕 本紐尺度適用中ΪΪ家標準(CNS)A4規格咖χ挪公董) 〜 313199 (請先閱讀背面之注意事項再填寫本頁) I * n I I n »ϋ n n 一:0JB an _1 n mmme n ϋ ϋ 1 p 530455 經濟部智慧財產局員工消費合作社印製
    (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規袼(210 X 297公釐) 36 313199 » 裝 訂--------- 530455
    經濟部智慧財產局員工消費合作社印制衣 t、申請專利範圍 用以連接前述化合物半導體晶片的各電極與前述 外部電極的連接機構; 、而將則述外部電極對準前述絕緣樹脂層的中心線 曰X左右對稱方式配置,並使之對應前述化合物半導體 晶片的各電極的位置。 申明專利範圍帛i 7項之化合物半導體開關電路裝 置,、中,刚述外部電極係被配置在前述絕緣樹脂層的 背面。 19•如申請專利範園第17項之化合物半導體開關電路裝 置,其中,前述化合物半導體晶片》8端子元件,並具 備有8、個前述外部電極。 申-月專利範圍帛17:^之化合物+導體開關電路裝 置其中,刖述8個外部電極係以前述絕緣樹脂層的中 心線為中心而以左右對稱方式分別配置4個,並沿著前 述=緣樹脂層的—邊,按照前述第1,第2輸入端子以 及月〗述第3 ’第4輸入端子的順序配置,另外,又沿著 前述,緣樹脂層的-邊的對邊,按照前述第i控制^2蝻述第1共通輸出端子,前述第2共通輸出端子, 刖述第2控制端子的順序配置。 21.如申請專利範圍第17項之化合物半導體開關電路裝 置,其中,前述樹脂層的表面形成有可顯示前述外部電 極極性的極性顯示標記。 (請先閱讀背面之注意事項再填寫本頁} ,裝 n n ι ϋ^eJ« n I ·ϋ n «ϋ ϋ 1 313199
TW90129037A 2001-04-19 2001-11-23 Switch circuit device of compound semiconductor TW530455B (en)

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JP2001121292A JP2002314042A (ja) 2001-04-19 2001-04-19 化合物半導体スイッチ回路装置
JP2001121293A JP2002314043A (ja) 2001-04-19 2001-04-19 化合物半導体スイッチ回路装置
JP2001141894A JP2002343869A (ja) 2001-05-11 2001-05-11 化合物半導体スイッチ回路装置

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CN1381952A (zh) 2002-11-27
EP1251561A3 (en) 2006-05-24
US20020153585A1 (en) 2002-10-24
EP1251561A2 (en) 2002-10-23
KR100599364B1 (ko) 2006-07-14
US6882210B2 (en) 2005-04-19
CN1283044C (zh) 2006-11-01
KR20020082394A (ko) 2002-10-31

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