TWI222191B - Semiconductor switch circuit device and manufacturing method therefor - Google Patents

Semiconductor switch circuit device and manufacturing method therefor Download PDF

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Publication number
TWI222191B
TWI222191B TW92108884A TW92108884A TWI222191B TW I222191 B TWI222191 B TW I222191B TW 92108884 A TW92108884 A TW 92108884A TW 92108884 A TW92108884 A TW 92108884A TW I222191 B TWI222191 B TW I222191B
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TW
Taiwan
Prior art keywords
fet
electrode
circuit device
switch circuit
semiconductor switch
Prior art date
Application number
TW92108884A
Other languages
Chinese (zh)
Other versions
TW200308067A (en
Inventor
Tetsuro Asano
Mikito Sakakibara
Original Assignee
Sanyo Electric Co
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Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200308067A publication Critical patent/TW200308067A/en
Application granted granted Critical
Publication of TWI222191B publication Critical patent/TWI222191B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
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    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A problem of deterioration of isolation in a compound semiconductor switch circuit device caused by the leakage of high frequency signals through the molded resin is to be solved. Posts are provided around a FET and a seal metal supported by the posts is provided above the FET. Thus, when a normal resin molding operation is executed, the resin can't enter the space between the FET and the seal metal as the separating distance therebetween is small therefore the space over the FET becomes empty. Consequentially, the leakage of high frequency signals can be prevented by the seal metal shielding between the FET and molded resin and air of small dielectric constant shielding between the IN and OUT terminals of the FET.

Description

1222191 玖、發明說明 【發明所屬技術領域】 本發明係關於使用於高頻開關用途之半導體開關電路 裝置及其製造方法，特別是關於用以提昇高頻之隔離之半 導體開關電路裝置及其製造方法。 【先前技術】 由於行動電話等移動體用通訊機器，多使用GHz頻 ▼之微波，因此，在天線的切換電路或收發訊的切換電路 等之中，多使用可切換上述高頻訊號之開關元件（例如： 特開平9-181642號）。開關元件，一般多用以處理高頻訊 旎，故其多使用砷化鎵（〇aAs)之場效電晶體（以下稱之為 FET)，因此將别述開關電路本身集積化之單石微波積體 電路（MMIC)的研發亦隨之持續進行。在此，半導體開關 電路裝置係以化合物開關電路裝置為例進行說明。 第10圖（A)係顯示GaAs MESFET(金屬半導體場效電 晶體）之剖面圖。該電晶體係在無摻雜之GaAs基板i的 表面部分摻雜N型雜質以形成N型通道領域2，並設置 與通道領域2表面形成肖特基接觸之閘極電極3，及在閘 極電極3的兩側設置與GaAs表面形成歐姆接觸之源極、 汲極電極4、5者。該電晶體，係利用閘極電極3的電位， 在正下方的通道領域2内形成耗盡層，而控制源極電極4 與汲極電極5間之通道電流。 第1〇圖（B)係顯示使用GaAsFET之被稱為 SPDT(Smgle Pole Double几購丨單刀雙投）之化合物半導 314420R1 5 1222191 體開關電路裳置的原理的電路圖。 第1契第2之FET1、FET2的源極（或汲極）係連接於 共通輸人端子IN，各阳卜而2的閘極係經由電阻仏 R2連接於第！與第2控制端子叫、⑶小此外各阳 的汲極（或源極）係連接於第！與第2輸出端子〇υτι、 〇UT2。施加於第1與第2控制端子CtM、Ctl_2的訊號 係一種互補訊號，可使施加高位準（Hlevel)訊號之FE/ V通（ON)，而使施加於輸入端子IN之訊號傳送至任何一 方的輸出端子。電阻R1、R2，係根據下列目的而配置： 亦即，為了防止高頻訊號相對於形成交流接地之控制端子 CtM、Ctl-2之直流電位而經由閘極電極漏掉的情形。 第11圖，係顯示將第10圖所示之化合物半導體開關 電路裝置集積化而成之化合物半導體晶片的丨實例。 在GaAs基板的中央部配置進行開關之FETi與 FET2 ’而電阻！u、R2係連接於各fet之閘極電極。此 外，對應共通輸入端子、輸出端子、以及控制端子之各電 極焊塾 INPad、OUTIPad、〇UT2Pad、Ctl-lPad、CtldPad 係分別設置於基板的周邊。此外，虛線所示之第2層之配 線係在形成各FET之閘極電極時同時形成之閘極金屬層 (Ti/Pt/Au)20，而實線所示之第3層之配線係 用以進行各 凡件之連接及焊墊之形成的焊墊金屬層（Ti/pt/A…3〇。與 第1層之基板形成歐姆接觸之歐姆金屬（AuGe/Ni/Au)10 係用以形成各FET之源極電極、汲極電極以及各電阻兩 端之引出電極者，在第Π圖中，因與焊墊金屬層重疊而 6 314420R1 1222191 未顯示於圖中。 、，第12圖（A)係顯示第11圖所示之FET1部分之放大 平面圖®中，以_點鏈線圍繞之長方形領域乃形成於基 反11之通道領域12。由左側延伸之梳齒狀之第3層之焊 墊金屬層30係連接於輸出端子〇UT1之源極電極(或 汲極電極），其下方則是由第1層之歐姆金屬1〇所形成之 原極電極14(或;及極電極）。此外由右側延伸之梳齒狀之第 3層之焊墊金屬層3〇係連接於輸入端子之汲極電極 15(或源極電極），其下方則是由第1層之歐姆金屬10所 /成之汲極電極1 6(或源極電極）。兩電極係以梳齒相互咬 口之形狀σ又置’兩者之間由第2層之閘極金屬層Μ所形 成之閘極電極17係以梳齒形狀設置於通道領域12上。 第12圖（Β)係顯示該㈣之一部分之剖面圖。在基 板11上叹置η型通道領域i 2並在該通道領域的兩側設置 用來形成源極領域18與汲極領域19之^型高濃度領域， 同時在通道領域12上設置閑極電極17，並在高濃度領域 設置由第1層之歐姆金屬10所形成之源極電極14與沒極 電極16。此外，在其上方如前述-般設置由第3層之焊 整金屬層3 0所形成之诉搞雷& 〜风惑源極電極13與汲極電極15，並進 行各元件之配線等。 示υ圖係顯示前述半導體晶片經封裝後之剖 面構造。第13圖⑷為封裝剖面圖、第13圖(Β)係封裝後 之FET之冑份的放大、概略化之剖面圖。部的詳 細構造係與第12圖⑻相同。除形成各端子之電極焊墊上 314420R1 7 1222191 之外，於晶片全面番, Η ^ ^ ^ ^ y. 〇 ”、、保護膜之氮化膜50。形成有 開關兀件之化合物丰導#曰 一…，4 牛―體曰曰片63係藉由導電膏65等固定 ,^ 島邠上，化合物半導體晶片63之 各電極焊墊與引線62係藉由技 稽田接 a 線（bonding wire)64 連 接。半導體晶片63之周邊部八总上 P刀 係由與模塑模具形狀一 致的樹脂層80所覆蓋，而&〜^ 引線62之前端部分係導出於樹 脂層8 0之外部。 【發明内容】 發-明所欲解決之枯浙問翻 現今，為了架構可傳送更高密度資訊之無線網路而 日益增加對於可由傳統之2.4GHz頻帶提昇至5·頻帶 以及更高頻的製品的需求。然、而，將上述傳統構造之化人 物半導體開關電路裝置使用於高頻時，卻發現其隔離° (isolation)較設計值惡化之情形。如第u圖、第12圖所 示，FET係使成為訊號輸出與輸入端之源極電極13與汲 極電極15之間夾置閘極電極17而以梳齒狀配置。例如： 當FET1導通（ON)時，FET2關斷（OFF)，輸入FET2之高 頻A號’會在FET2的源極-沒極電極間、亦即在〗^丁 間被遮斷，而無法通過。然而，實際上，該源極_汲極電 極之間、亦即訊號的ΙΝ·〇υτ之間的構成係由微細圖案所 形成。亦即，在OFF側FET(FET2)之m-ουτ之間，因 高頻訊號通過模塑樹脂層80而漏洩之故，而使得隔離車交 設計值惡化。 該高頻訊號之漏汽’在2.4GHz頻帶無線區域網路 314420R1 8 1222191 (LAN)、藍牙用途等，2.4GHz程度的頻帶下，並不會造 成任何問題。但是，當漏洩發生在今後所期待之5GHz以 上的高頻帶時，則會導致隔離嚴重惡化的問題。 題之拮術年段 本發明係有鑑於上述之問題而完成者，其係一種由·· 在半導體基板表面設置源極電極、閘極電極及汲極電極而 成之至少-個FET;以及分別與和前述㈣之源極電極 或汲極電極連接之至少一個輸入端子、和前述ρΕτ之汲 極電極或源極電極連接之至少一個輸出端子、及用以對前 述FET施加DC電位之端子對應之電極焊墊所構成的半 導體開關電路裝置，其特徵為具備：設置於前述FET的 周圍之支柱；由前述支柱所支撐，至少覆蓋於前述 上之金屬層；以及覆蓋將前述FET集積化而成的晶片之 樹脂層。 此外’本發明係一種：在半導體基板上形成具有通道 ;二源極領域及汲極領域之FET，並形成分別與和前述 、接之輸入端子、輸出端子及用以施加DC電位之端 /應之電極知墊的半導體開關電路裝置之製造方法，其 :徵為具備：纟前述咖周圍形成支柱，並形成由前述、 柱所支撐’至少覆蓋於前述FET上之金屬層之步驟； 以及利用樹脂層霜芸 1 驟。 將-述Μ集積化而成的晶片之步 【實施方式】 以下，參昭篆]θ ^ » …、 圖至弟9圖，說明本發明之半導體開 9 314420R1 1222191 關電路裝置之實施形態。 第1圖係顯示本發明之第丨實施形態之化合物半導體 晶片之1實例。化合物半導體晶片，係形成在第11圖所 示佈局之曰曰片上配置密封金屬的構造。又，其電路圖與第 10圖（B)相同，FET的放大圖及剖面圖分別與第12圖（A)、 (B)相同，故省略這方面的說明。 在GaA基板的中央部配置進行開關之FET1與FET2， 而電阻Rl、R2係連接於各FET的閘極電極。此外，對應 共通輸入端子、輸出端子、以及控制端子之各電極焊墊 INPad、OUTIPad、〇UT2Pad、Ctl-lPad、Ctl-2Pad 係分別 設置於基板的周邊。此外，虛線所示之第2層之配線係在 形成各FET之閘極電極時同時形成之閘極金屬層 (Ti/Pt/Au)20，而實線所示之第3層之配線係用以進行各 元件之連接及焊墊之形成之焊墊金屬層（Ti/pt/Au)3〇。與 第1層之基板形成歐姆接觸之歐姆金屬（AuGe/Ni/Au)10 係用以形成各FET之源極電極、汲極電極以及各電阻兩 端之引出電極者，在第丨圖中，因與焊墊金屬層重疊而未 顯示於圖中。 在FET的周圍’將做為鈍化膜而全面設置之氮化膜 去除以使GaAs露出，並設置複數個支柱7丨。另外設置由 支柱71所支樓之密封金屬7〇。密封金屬7〇，係以可實質 覆盖FET上方全面之方式設置，且設有在Fet上方之複 數個孔。具體而言，該孔係寬2//m至5//m程度、長15 从m程度的槽孔90，係均等配置於密封金屬7〇上。 10 314420R1 1222191 如後所述，該槽孔9〇，係在為了實現利用密封金屬7〇 的中空構造而進行的阻劑（resist)去除步驟中，作為阻劑 去除液的通路。/亦即，槽孔的大小只要阻劑去除液能㈣ 而不會有阻劑殘留在密封金屬下，且樹脂模塑材不能流入 即可’並不限^上述的大小，槽孔的數量也不限於圖中所 不的數目。孔的形狀也一樣，不為槽形的孔亦可。各電極 焊塾部係於去除氮化膜後壓接接合線。 第2圖係顯示經樹脂模塑之第i圖之晶片之剖面圖。 第2圖（A)為封裝剖面圖，而第2圖（B)為FET部之放大剖 面圖。 如第2圖（A)所示，形成有具有FET72之開關元件之 化合物半導體晶片63係藉由導電膏65等固定安裝於引線 62之島部上，化合物半導體晶片63的各電極焊墊與引線 62係藉由接合線64來連接。半導體晶片63的周邊部分， 係由與模塑模具形狀一致之樹脂層8〇所覆蓋，而引線62 的前端部分係導出於樹脂層80外部。 密封金屬70,係由設置於FET72周圍之複數支柱71 所支撐’並设置於FET72的上方全面。支柱”與密封金 屬係一體形成，密封金屬70係由2//111至7//m之程 度的鍍金層所形成，FET72與密封金屬7〇之間係以工至 2 // m左右的距離隔開。 晶片63與引線62係以既知之方法進行樹脂模塑，但 因FET72與密封金屬70之間隔距離很小，故樹脂無法進 入該部分。此外，密封金屬70上設有槽孔9〇以避免殘留 314420R1 11 1222191 阻劑’但如本實施形態所示，當槽孔的寬度在2^至5 …間時樹脂即無法由此進入。亦即，士口圖所示由於 FET7:與密封金屬70之間’係形成中空部6〇,故可以實 現有尚頻訊號通過之FET表面形成中空之封裝構造。 第2圖（B)係概略顯示上述晶片之剖面圖。此外，fet 之詳細構造係與第12圖（5)相同。於做為輸入側之源極電 極13(或汲極電極15)與做為輸出側之汲極電極15(或源極 電極13)之間配置閘極電極17 ’實際上可將複數組之電極 集積化以形成"固而72。在本發明之構造中，係在前述 之FET72上6又置由支柱71所支撐之密封金屬7〇，由於密 封金屬70的外側係由樹脂層8〇所覆蓋，故ρΕτ72表面 形成中空部60。 本貫施形悲中，FET72表面與密封金屬7〇之間的距 離，係以樹脂層無法進入的距離設置。具體而言，該間隔 距離係在1至2 # m的程度，達到該厚度時，即使周圍藉 由移轉模塑（transfer m〇ld)等方法而被樹脂層8〇所覆蓋， 該樹脂亦不會進入到FET72上。此外，因槽孔9〇亦在2 //m至的程度，故樹脂無法由此流入，而使fet72 與岔封金屬70之間得以形成中空部6〇。亦即，如圖所示， 源極電極13、汲極電極15、閘極電極17與樹脂層8〇係 由密封金屬70所實質遮蔽，此外，因FET上形成中空狀， 故可利用比介電常數低之空氣在〇FF側之源極-汲極電極 間、亦即IN-OUT間形成遮斷。如此一來，即可將輸入〇FF 側FET之高頻訊號中、經由模塑樹脂層8〇而漏洩至輸出 314420R1 12 1222191 側的訊號完全遮蔽。 此外，封裝構造，係以沖切引線架之引線及移轉模塑 為例進行說明，但本發明同樣可實施於：在絕緣基板上形 成導電圖案而一併進行模塑之晶片尺寸封裳構造上。 如上所述’本貫施形悲係利用由支柱7 1所支撑之密 封金屬70,在FET72上設置中空部6〇 ’以防止開關元件 之IN-OUT間高頻訊號之漏洩。亦即，上述實施形態，係 以1個共通輸入端子與2個FET、2個out端子所構成 之SPDT開關為例進行說明。但是本發明同樣可實施於具 有分路（shunt)之SPDT;直列連接複數個ρΕτ而成之高功 率用SPDT ’具2個輸人；^子、2個輸出端子之DpDT(雙 刀雙投）等開關電路裝置；或是具有GND端子、電源端子 之開關電路#置中。另夕卜’亦可實施於使用高功率用途之 多閘極構造FET之開關電路裝置，以及非對稱spDT、 SPST(單刀單投）、SP3T(單刀三投）、时（單刀四投）等所 有開關電路裝置。 、在此，利用第3圖說明支柱71的形成位置。支柱71 系、可充刀支持遂封金屬7〇的方式，在FET 72的周圍 :置複數個。本實施形態中係先使GsAs基板露出然後才 又置支柱7 1 ’因此只要是沒有配置開關電路元件的装他 構成部份的任付Μ罢比1^ ~ 置白可δ又置，並不限於第i圖所示的位 Μ t在支枝71為直接連接於無摻雜的GSAS*板上的 义肩確保支柱71與構成和支柱71鄰接的開關^ 314420R1 13 置之元件101(例如FET的；及極領域等）的距離在以 m以上。此係唯恐因支板71與元件101的電位差而產生 、耗血層互相到達對方那一側所導致之兩者間之電性交互 作用影響到開關電路的動作之故。 因此’在支柱71所固著領域之GsAs基板表面 乂 k支柱7 1超出i # m以上的方式設置分離領域1222191 发明 Description of the invention [Technical field of the invention] The present invention relates to a semiconductor switch circuit device used for high-frequency switching applications and a manufacturing method thereof, and more particularly to a semiconductor switch circuit device used to improve high-frequency isolation and a manufacturing method thereof. . [Prior art] Since mobile communication devices such as mobile phones often use microwaves with a frequency of GHz, a switching element that switches the above-mentioned high-frequency signals is often used in a switching circuit for an antenna or a switching circuit for transmitting and receiving. (Example: JP-A-9-181642). Switching elements are generally used to process high-frequency signals. Therefore, they often use field effect transistors (hereinafter referred to as FETs) of gallium arsenide (〇aAs). Therefore, the monolithic microwave products of other switching circuits are integrated. Research and development of the body circuit (MMIC) has continued. Here, the semiconductor switch circuit device will be described using a compound switch circuit device as an example. Fig. 10 (A) is a sectional view showing a GaAs MESFET (metal semiconductor field effect transistor). In the transistor system, an N-type impurity is doped on the surface of an undoped GaAs substrate i to form an N-type channel region 2, and a gate electrode 3 forming a Schottky contact with the surface of the channel region 2 is provided. On both sides of the electrode 3, a source electrode and a drain electrode 4, 5 which form an ohmic contact with the GaAs surface are provided. This transistor uses the potential of the gate electrode 3 to form a depletion layer in the channel region 2 directly below it, and controls the channel current between the source electrode 4 and the drain electrode 5. Figure 10 (B) is a circuit diagram showing the principle of a compound semiconductor called SPDT (SMDle Pole Double 丨 single-pole double-throw) using GaAsFET 314420R1 5 1222191 body switch circuit. The source (or drain) of FET1 and FET2 of the first lease is connected to the common input terminal IN, and the gates of each of the two terminals are connected to the first via a resistor 仏 R2! The drain (or source) of each positive terminal is connected to the second control terminal, and the second control terminal. And second output terminals 〇υτι and 〇UT2. The signal applied to the first and second control terminals CtM and Ctl_2 is a complementary signal, which can apply the FE / V pass (ON) of a high level signal, and the signal applied to the input terminal IN is transmitted to either party. Output terminal. The resistors R1 and R2 are configured according to the following purposes: That is, in order to prevent the high-frequency signal from being leaked through the gate electrode with respect to the DC potential of the control terminals CtM and Ctl-2 forming an AC ground. Fig. 11 shows an example of a compound semiconductor wafer in which the compound semiconductor switch circuit device shown in Fig. 10 is integrated. The FETi and FET2 ′ for switching are arranged in the center of the GaAs substrate and the resistance is provided! u, R2 are connected to the gate electrode of each fet. In addition, the electrode pads INPad, OUTIPad, OUT2Pad, Ctl-1Pad, and CtldPad corresponding to the common input terminal, output terminal, and control terminal are respectively provided on the periphery of the substrate. In addition, the wiring of the second layer shown by a dotted line is a gate metal layer (Ti / Pt / Au) 20 which is formed at the same time when the gate electrode of each FET is formed, and the wiring of the third layer shown by a solid line is used The pad metal layer (Ti / pt / A ... 30) is formed to connect various pieces and the pads. The ohmic metal (AuGe / Ni / Au) 10 which forms ohmic contact with the substrate of the first layer is used for The source electrode, the drain electrode, and the lead-out electrodes at the ends of each resistor that form the FETs are not shown in the figure because of the overlap with the pad metal layer 6 314420R1 1222191. Figure 12 ( A) is an enlarged plan view showing the FET1 part shown in Figure 11. The rectangular area surrounded by the _ dot chain line is formed in the channel area 12 of the base 11. The comb-tooth-shaped third layer extends from the left side. The pad metal layer 30 is connected to the source electrode (or the drain electrode) of the output terminal OUT1, and below it is the original electrode 14 (or; and the electrode) formed by the ohmic metal 10 of the first layer. In addition, the comb-shaped third pad metal layer 30 extending from the right side is connected to the drain electrode 15 (or source electrode of the input terminal). Below) is the drain electrode 16 (or source electrode) made by the ohmic metal 10 of the first layer. The two electrodes are in the shape of a bite σ and placed between the two. The gate electrode 17 formed by the gate metal layer M of the second layer is arranged in a comb-tooth shape on the channel area 12. FIG. 12 (B) is a cross-sectional view showing a part of the ridge. Sigh on the substrate 11 The n-type channel region i 2 is set and two sides of the channel region are used to form a high-concentration region of the source region 18 and the drain region 19. At the same time, the idler electrode 17 is disposed on the channel region 12 and In the concentration range, the source electrode 14 and the non-electrode electrode 16 formed of the ohmic metal 10 of the first layer are provided. In addition, as described above, the formation of the third layer of the welded metal layer 30 is used. Lightning & ~ Wind confuses the source electrode 13 and the drain electrode 15, and performs wiring of each element, etc. The picture shows the cross-sectional structure of the aforementioned semiconductor wafer after being packaged. Figure 13 is a package cross-sectional view, and Figure 13 Figure (B) is an enlarged and schematic cross-sectional view of the weight of the FET after packaging. Detailed structure of the part Same as Figure ⑻. Except for forming the electrode pads of each terminal on 314420R1 7 1222191, the wafer is fully covered, ^ ^ ^ ^ ^ y. 〇 ”, the nitride film 50 of the protective film. The switch element is formed The compound Fengdao # 一一 ..., 4 牛 — 体 说 片 63 is fixed by conductive paste 65, etc. ^ On the island, the electrode pads and leads 62 of the compound semiconductor wafer 63 are connected by Jiji Tian. a wire (bonding wire) 64 connection. The P knife on the periphery of the semiconductor wafer 63 is covered by a resin layer 80 conforming to the shape of the mold, and the front end of the lead 62 is led out of the resin layer. 8 0 outside. [Summary of the Invention] The problem that Fa-Ming wants to solve is nowadays. In order to build a wireless network that can transmit higher density information, the number of products that can be upgraded from the traditional 2.4GHz band to the 5 · band and higher frequencies is increasing. Demand. However, when the above-mentioned conventional structured semiconductor switching circuit device is used at a high frequency, it is found that its isolation is worse than the design value. As shown in Fig. U and Fig. 12, the FET is arranged in a comb-tooth shape with the gate electrode 17 interposed between the source electrode 13 and the drain electrode 15 which are the signal output and input terminals. For example: When FET1 is on (ON), FET2 is off (OFF), the high-frequency A number 'of input FET2 will be blocked between the source-electrode electrode of FET2, that is, between ^ and D, and cannot be turned off. by. However, in practice, the structure between the source-drain electrodes, that is, the signal IN · 〇υτ is formed by a fine pattern. That is, between m-ουτ of the OFF-side FET (FET2), the high-frequency signal leaks through the molded resin layer 80, thereby deteriorating the design value of the isolated vehicle. The leakage of this high-frequency signal ’does not cause any problems in the 2.4GHz band wireless local area network 314420R1 8 1222191 (LAN) and Bluetooth applications. However, if leakage occurs in the high-frequency band above 5 GHz, which is expected in the future, it will cause a serious deterioration of isolation. The present invention was completed in view of the above problems, and is a type of at least one FET formed by providing a source electrode, a gate electrode, and a drain electrode on the surface of a semiconductor substrate; and respectively At least one input terminal connected to the source electrode or the drain electrode of the ㈣, at least one output terminal connected to the drain electrode or the source electrode of the ρEτ, and a terminal for applying a DC potential to the FET. The semiconductor switch circuit device composed of electrode pads includes: a pillar provided around the FET; a metal layer supported by the pillar and covering at least the aforementioned metal layer; and a layer formed by integrating the aforementioned FET. The resin layer of the wafer. In addition, the present invention relates to a method in which a FET having a channel, a two-source region and a drain region is formed on a semiconductor substrate, and the input terminal, the output terminal, and a terminal / response for applying a DC potential are formed respectively and connected to the foregoing. The method for manufacturing a semiconductor switch circuit device for electrode pads includes the following steps: forming a pillar around the aforementioned cavities and forming a metal layer supported by the aforementioned pillars to cover at least the aforementioned FET; and using a resin Layer frost Yun 1 step. The step of integrating the wafers described above [Embodiment] Hereinafter, reference is made to θ ^ »…, to FIG. 9 to illustrate the embodiment of the semiconductor device 9 314420R1 1222191 of the present invention. Fig. 1 shows an example of a compound semiconductor wafer according to a first embodiment of the present invention. The compound semiconductor wafer has a structure in which a sealing metal is arranged on a chip shown in the layout shown in FIG. 11. The circuit diagram is the same as that in FIG. 10 (B), and the enlarged view and cross-sectional view of the FET are the same as those in FIGS. 12 (A) and (B), and therefore descriptions thereof are omitted. The switching FET1 and FET2 are arranged in the center of the GaA substrate, and the resistors R1 and R2 are connected to the gate electrode of each FET. In addition, electrode pads INPad, OUTIPad, OUT2Pad, Ctl-1Pad, and Ctl-2Pad corresponding to the common input terminal, output terminal, and control terminal are respectively provided on the periphery of the substrate. In addition, the wiring of the second layer shown by a dotted line is a gate metal layer (Ti / Pt / Au) 20 which is formed at the same time when the gate electrode of each FET is formed, and the wiring of the third layer shown by a solid line is used A pad metal layer (Ti / pt / Au) 30 for connecting the components and forming the pads is performed. The ohmic metal (AuGe / Ni / Au) 10 which makes ohmic contact with the substrate of the first layer is used to form the source electrode, the drain electrode, and the lead-out electrodes of each resistance of each FET. In the figure, It is not shown in the figure because it overlaps with the pad metal layer. Around the FET ', a nitride film, which is provided as a passivation film, is completely removed to expose GaAs, and a plurality of pillars 7 are provided. In addition, the sealing metal 70 of the branch supported by the pillar 71 is provided. The sealing metal 70 is provided so as to substantially cover the entire area above the FET, and is provided with a plurality of holes above the Fet. Specifically, the holes are slot holes 90 having a width of about 2 // m to 5 // m and a length of about 15 to about m, which are uniformly arranged on the sealing metal 70. 10 314420R1 1222191 As will be described later, the slot 90 is used as a passage for the resist removal liquid in a resist removal step for realizing a hollow structure using a sealing metal 70. / That is, the size of the slot holes is not limited as long as the resist removal liquid can be used without leaving the resist agent under the sealing metal, and the resin molding material cannot flow in. 'The size is not limited. The number of slot holes is also It is not limited to the number shown in the figure. The shape of the hole is the same, and a hole other than a groove shape may be used. The electrode pads of each electrode are crimped to a bonding wire after removing the nitride film. Fig. 2 is a cross-sectional view showing the wafer of Fig. I molded by resin. Fig. 2 (A) is a cross-sectional view of the package, and Fig. 2 (B) is an enlarged cross-sectional view of the FET portion. As shown in FIG. 2 (A), the compound semiconductor wafer 63 on which the switching element having the FET 72 is formed is fixedly mounted on the island portion of the lead 62 by a conductive paste 65 or the like. Each electrode pad and lead of the compound semiconductor wafer 63 62 is connected by a bonding wire 64. The peripheral portion of the semiconductor wafer 63 is covered by a resin layer 80 conforming to the shape of the mold, and the front end portion of the lead 62 is led out of the resin layer 80. The sealing metal 70 is supported by a plurality of pillars 71 provided around the FET 72 and is provided over the entire surface of the FET 72. The "pillar" is integrally formed with the sealing metal system. The sealing metal 70 is formed by a gold plating layer of 2 // 111 to 7 // m. The distance between the FET72 and the sealing metal 70 is about 2 // m. The chip 63 and the lead 62 are resin-molded by a known method, but because the distance between the FET 72 and the sealing metal 70 is small, the resin cannot enter the part. In addition, a slot 9 is provided in the sealing metal 70. To avoid residual 314420R1 11 1222191 resist, but as shown in this embodiment, when the width of the slot is between 2 ^ and 5… the resin cannot enter through it. That is, the FET7: and sealing Between the metal 70, a hollow portion 60 is formed, so that a hollow package structure can be formed on the surface of the FET through which the frequency signal passes. Fig. 2 (B) is a schematic cross-sectional view of the wafer. In addition, the detailed structure of the fet It is the same as the figure (5) in Fig. 12. A gate electrode is arranged between the source electrode 13 (or the drain electrode 15) as the input side and the drain electrode 15 (or the source electrode 13) as the output side. 17 'In fact, the electrodes of the complex array can be integrated to form " Solid 72. In the structure of the present invention, the sealing metal 70 supported by the pillar 71 is placed on the FET 72, and the outside of the sealing metal 70 is covered by the resin layer 80. Therefore, the hollow portion 60 is formed on the surface of ρΕτ72. In this implementation, the distance between the surface of the FET72 and the sealing metal 70 is set at a distance that cannot be reached by the resin layer. Specifically, the separation distance is in the range of 1 to 2 # m, when the thickness is reached Even if the surrounding area is covered by the resin layer 80 by a method such as transfer molding, the resin will not enter the FET 72. In addition, the slot 90 is also between 2 // m to To the extent that the resin cannot flow in, a hollow portion 60 is formed between the fet72 and the bifurcated metal 70. That is, as shown in the figure, the source electrode 13, the drain electrode 15, the gate electrode 17 and The resin layer 80 is substantially shielded by the sealing metal 70. In addition, since the FET is formed in a hollow shape, air with a lower dielectric constant than the source-drain electrode on the 0FF side, that is, IN-OUT Interruption is formed. In this way, the high-frequency signal input to the FF side FET can be The signal leaked to the side of the output 314420R1 12 1222191 through the molding resin layer 80 is completely shielded. In addition, the package structure is explained by taking the lead of the lead frame and transfer molding as examples, but the present invention can also be implemented in : On a wafer-size sealing structure that forms a conductive pattern on an insulating substrate and molds it together. As described above, the "inherent shape" uses a sealing metal 70 supported by a pillar 71, and a hollow portion is provided on the FET 72. 60 ′ to prevent leakage of high-frequency signals between the IN-OUT of the switching element. That is, the above embodiment is described by taking an SPDT switch composed of a common input terminal, two FETs, and two out terminals as an example. However, the present invention can also be implemented in a SPDT with shunts; a high-power SPDT formed by in-line connection of a plurality of ρΕτ 'with 2 inputs; DpDT (double-pole double-throw) with two output terminals And other switching circuit devices; or a switching circuit # with a GND terminal and a power terminal is centered. In addition, it can also be implemented in switching circuit devices using multi-gate structure FETs for high power applications, as well as asymmetric spDT, SPST (single-pole single-throw), SP3T (single-pole three-throw), and time (single-pole four-throw). Switch circuit device. Here, the formation position of the pillar 71 will be described using FIG. 3. The pillar 71 is a type that can be filled with a knife to support the metal 70, and a plurality of them are placed around the FET 72. In this embodiment, the GsAs substrate is exposed first, and then the pillar 7 1 ′ is placed. Therefore, as long as it is a component that is not equipped with a switching circuit component, it can be replaced with δ. Limited to the position M t shown in Figure i. The branch 71 is a prosthetic shoulder directly connected to the undoped GSAS * board. The switch that ensures that the pillar 71 is adjacent to the structure 71 314420R1 13 The device 101 (such as a FET) And polar areas, etc.) at distances above m. This is because the electrical interaction between the two caused by the potential difference between the support plate 71 and the element 101 and the blood-consuming layers reaching each other will affect the operation of the switching circuit. Therefore, on the surface of the GsAs substrate in the area to which the pillar 71 is fixed, 乂 k pillar 7 1 is provided in a manner that exceeds i # m or more.

，最 100。 此實施形態中之分離領域為高濃度㈣100。ϋ此，即可 抑制因支柱71與鄰接的元件1〇1間的電位差而產生之基 板中的耗盡層的擴大，所以支柱71與鄰接的元件ι〇ι的 間隔距離d可接近至4 “ m程度（第3圖（a》。 另外，本實施形態中，雖以化合物半導體開關電路裝 置為例進行說明，惟不限於此，亦可在如第3圖⑻、（c) 之矽半導體開關電路裝置中實施。 矽半導體開關電路裴置中，基板2丨丨為例如〆型高 ί辰度矽基板，其上設有作為通道領域212之p —磊晶層。 通道領域212表面設有閘極氧化膜213，閘極氧化膜213 的表面設有閘極電極217。閘極電極217兩側的通道領域 2 1 2中係設置低濃度的雜質領域LD而具有所謂的 LDD(Light Doped Drain ;輕微摻雜的汲極）構造。藉此可 抑制通道電阻的降低及抑制短通道效應。再者，閘極電極 217的兩側設有形成源極領域218及汲極領域219之一型 高濃度領域。在源極領域218及汲極領域219上係用鋁（A1) 等設置源極電極216及汲極電極214，然後進行各元件的 配線等。 314420R1 14, Up to 100. The separation area in this embodiment is high-concentration ㈣100. This can suppress the expansion of the depletion layer in the substrate due to the potential difference between the pillar 71 and the adjacent element 101, so the distance d between the pillar 71 and the adjacent element ιι can be close to 4 " m degree (Fig. 3 (a). In this embodiment, although a compound semiconductor switch circuit device is taken as an example for description, it is not limited to this, and a silicon semiconductor switch as shown in Fig. 3 (c)) The semiconductor device is implemented in a circuit device. The substrate 2 is a high-degree silicon substrate, for example, a p-epitaxial layer as a channel field 212. A gate is provided on the surface of the channel field 212. The gate oxide film 213 is provided with a gate electrode 217 on the surface of the gate oxide film 213. A channel region 2 1 2 on both sides of the gate electrode 217 is provided with a low-concentration impurity region LD and has a so-called LDD (Light Doped Drain; Slightly doped drain) structure. This can reduce the decrease in channel resistance and suppress the short channel effect. Furthermore, the gate electrode 217 is provided on both sides with a high concentration forming one of the source region 218 and the drain region 219 Domain. In the source domain 218 and sink Department of aluminum (A1) field 219 is provided on the other of the source electrode 216 and drain electrode 214, and wiring elements, and the like. 314420R1 14

AVIAVI

在FET 101的周圍，將做A 為鈍化膜而全面設置的氮 化膜215去除，使基板211表面霞山 如\ 路出而設置分離領域1〇〇。 在为離領域100上設置支柱71、 封金屬70。 及由支柱71所支撐的密 上述例子中，基板211為 θ p坦石夕基板，其通常成為 助電位。在此種情況下，可在支柱71的正下方配置使 和基板211同程度的雜質擴散而形成的高濃度領域_， 來作為分離領域1()〇’使支柱71與鄰接的元件1〇1的例 如汲極領域219相分離（第3圖（B))。 ’、、;、而’此種構造在施加於密封金屬7〇的電位為漏 電位時雖沒有問題，但若為其他的DC電位，％會成為與 GND短路的狀態而有問題。因此，在這樣的情況下，可 設置LOCOS(局部氧化隔絕）氧化膜ι嶋來作為分離領域 100。在LOCOS氧化膜100b上配置支柱71，則支柱71 與鄰接兀件的擴散領域、基板2 i i之間不會發生電性交互 作用因此在饴封金屬7 0上施加怎樣的d c電位都沒問 題（第3圖（C))。 以下第4圖與第5圖係顯示本發明之第2實施形態。 如第4圖所不，亦可使覆蓋於FET上之密封金屬70延伸， 而使之與控制端子用電極焊墊CtMPad接觸。 在此’雄封金屬7 〇下方之晶片平面圖，係與第丨丨圖 所不之平面圖相同。此外，電路圖係與第1 〇圖（B)相同， FET之放大圖與剖面圖則分別與第12圖（A)、（B)相同， 故省略其說明。 15 314420R1 Ϊ222191 第5圖顯示晶片經樹脂模塑後之剖面圖。 如第5圖（A)所示，形成有開關元件之化合物半導體 晶片63係藉由導電膏65等固定安裝於引線62之島部上， 化合物半導體晶片63的各電極焊墊與引線62係藉由接合 線64來連接。半導體晶片〇的周邊部分，係由與模塑模 具形狀-致之樹脂層8G所覆蓋，而引線62的前端部分係 導出於樹脂層80外部。藉由在進行樹脂模塑時，以樹脂' 無法進入之程度的間隔距離，在FET72上設置由支柱所 支撐的密封金屬70，如此即可在樹脂模塑中，於 上形成中空部60。 苐5圖（B)為概略顯示上述晶片之剖面圖 的詳細構造係與第12圖⑻相同。於作為輸人側之源極電 極叫或沒極電極15)與作為輸出側之汲極電極15(或源極 電極1 3 )之間設置閘極電極1 屯u i /，將5亥4稷數組之電極集積 化以形成1個FET72。在本蛴明夕描、生士 "丄 ^ 你不&明之構造中，係在該等FET72 上全面設置密封金屬7〇，使嗜曰 從Θ日日片固定於引線上而進行 樹脂模塑。亦即’如圖所示，源極電極13、極極電極15 及閘極電極與樹脂層80之間實質上係由密封金屬7〇 所遮蔽。 此外，與第1實施形態相同，密封金屬70上’係設 置有寬2”至5" m的槽孔，槽孔符合該尺寸時樹脂即 無法流入。此外’密封金屬7〇與附間的距離亦在^ m至2/zm，故樹脂無法進入其間，而形成中空部6〇。Around the FET 101, the nitride film 215, which is completely provided as a passivation film, is removed, so that the surface of the substrate 211 is set in a separate area as shown in FIG. A pillar 71 and a sealing metal 70 are provided on the separation area 100. In the above example, the substrate 211 is a θ p tanzanite substrate, which usually becomes an auxiliary potential. In this case, a high-concentration region _ formed by diffusing impurities to the same degree as the substrate 211 may be disposed directly below the pillar 71 as the separation region 1 (). The pillar 71 and the adjacent element 101 may be disposed. For example, the drain region 219 is separated (Figure 3 (B)). ',,;,' This structure has no problem when the potential applied to the sealing metal 70 is a drain potential, but if it is another DC potential,% will be short-circuited to GND and there is a problem. Therefore, in such a case, a LOCOS (Local Oxidation Insulation) oxide film can be provided as the separation area 100. If the pillar 71 is arranged on the LOCOS oxide film 100b, no electrical interaction will occur between the pillar 71 and the diffusion area of the adjacent element, and the substrate 2 ii. Therefore, no matter what kind of dc potential is applied to the sealing metal 70 ( Figure 3 (C)). 4 and 5 below show a second embodiment of the present invention. As shown in FIG. 4, the sealing metal 70 covering the FET may be extended to contact the electrode pad CtMPad for the control terminal. The plan view of the wafer below the masculine metal 70 is the same as the plan view shown in FIG. In addition, the circuit diagram is the same as that in FIG. 10 (B), and the enlarged view and cross-sectional view of the FET are the same as those in FIGS. 12 (A) and (B), respectively, so the description is omitted. 15 314420R1 Ϊ222191 Figure 5 shows a cross section of the wafer after resin molding. As shown in FIG. 5 (A), the compound semiconductor wafer 63 on which the switching element is formed is fixedly mounted on the island portion of the lead 62 by a conductive paste 65 or the like, and each electrode pad of the compound semiconductor wafer 63 and the lead 62 are borrowed. They are connected by bonding wires 64. The peripheral portion of the semiconductor wafer 0 is covered by a resin layer 8G conforming to the shape of the mold, and the front end portion of the lead 62 is led out of the resin layer 80. When the resin molding is performed, the sealing metal 70 supported by the pillars is provided on the FET 72 at an interval to the extent that the resin cannot enter, so that the hollow portion 60 can be formed thereon in the resin molding. Fig. 5 (B) is a schematic view showing a detailed sectional view of the wafer, and the detailed structure is the same as Fig. 12 (a). A gate electrode 1 is provided between the source electrode on the input side or the non-electrode electrode 15) and the drain electrode 15 (or the source electrode 1 3) as the output side. The electrodes are integrated to form one FET 72. In the structure of this book, "Mr. You and You", the sealing metal 70 is fully installed on the FET72, so that the resin mold is fixed to the lead from the Θ-Japanese film. Plastic. That is, as shown in the figure, the source electrode 13, the electrode 15 and the gate electrode and the resin layer 80 are substantially shielded by a sealing metal 70. In addition, similar to the first embodiment, the sealing metal 70 is provided with a slot having a width of 2 ”to 5 " m, and the resin cannot flow in when the slot matches this size. In addition, the distance between the sealing metal 70 and the attachment Also in the range of ^ m to 2 / zm, the resin cannot enter there, and a hollow portion 60 is formed.

藉由該中W即可利用比介電常數低的空氣於0FF 314420R1 16 ' 的源極_汲極電極間、亦即IN-OUT之間形成遮斷， :此’即可將輸入⑽側FET之高頻訊號中，經由模塑 树脂：80而漏汽至輸出側之訊號完全遮蔽。 第5圖（c)係顯不控制端子用電極焊塾diPad部的 圖》又置於FET上之密封金屬7〇延伸至控制端子用 電極焊塾CtMPad，而與由閘極金屬層20、焊墊金屬層3C 所形成之控制端子用電極焊塾CtMpad接觸。密封金屬八 上’連接有接合線64。 本發明之開關電路裝置，係將之控制訊號 施加於前述控制端子CtM以進行開關動作因此，藉由 該構造亦可將3V或〇kDC電位施加於密封金屬7〇上。 DC電位相對於高頻而言為gnd電位因此可藉由瞻 電位於OFF側FET之源極-沒極電極間、亦即於in_〇ut 之間形成遮斷。因此，輸人⑽側贿之高頻訊號中， 以往經由模塑樹脂層80而漏茂至輸出側之訊號，會化為 以3次元方式擴散於空氣中的電磁場，而可由密封金屬7〇 將所有漏茂的部份吸收掉，故可實現隔離效果更佳 造。 在此’本實施形態、’係使密封金屬7〇與控制端子用 電極焊墊CtMPad接觸，但亦可使密封金屬7〇與控制端 子用電極焊墊Ctl-2Pad接觸。亦即，只要施加dc電位之 端子能夠與密封金屬形成連接即可，因此當開關電路裝置 為具有GND端子、電源電壓端子等之開關電路裝置時， -需使密封金屬70與GND端子、電源電屡端子用電極 314420R1 17 1222191 焊塾接觸即可。 此外’第6圖顯示本發明之第3實施形態。本實施形 悲為未在密封金屬70上設置槽孔之構造。在後文中仍有 詳細之說明’但本發明係藉由在阻劑上設置密封金屬70， 後再去除阻劑，而實現中空構造。此外，為去除該密封金 屬下方所殘留之阻劑，乃在密封金屬7〇上設置槽孔以做 為阻劑去除液之通路。但是，應去除阻劑之領域、亦即中 空部的面積較小時，即使不設置槽孔亦可去除阻劑。具體 而言’可實現中空構造之Fet部的面積，只要小於5〇 # mx 50 a m，便可在未設置槽孔之情況下全面設置密封金 屬’而利用密封金屬將FET上方完全遮蔽。 以下，利用第7圖至第9圖，說明本發明之開關電路 裝置之製造方法。 本發明之開關電路裝置的製造方法，係在半導體基板 上形成具有通道領域、源極領域及汲極領域之F]Eir，並形 成分別與和前述FET連接之輸入端子、輸出端子以及用 以施加DC電位之端子對應的電極焊墊之半導體開關電路 之製造方法，包括··於前述FET周圍形成支柱，並形成 由前述支柱所支撑至少覆蓋於前述FET上之金屬層之步 驟；以及利用樹脂層覆蓋將前述FET集積化而成的晶片 之步驟。 本發明之第1步驟，如第7圖所示，係利用既知之方 法，在半導體基板上形成開關電路裝置。亦即，在半導體 基板上形成具有通道領域、源極領域及汲極領域之fet， 314420R1 18 1222191 並形成與前述FET連接之輪人料、輸出端子用電極焊 墊、以及用以施加DC電位之端子用電極焊墊。 亦即’如第7圖（A)所示，以厚度約為1〇〇入至雇 A的貫穿離子注人用氮切膜覆蓋由GaAs等所形成之化 合物半導體基板η全面。接著，為了選擇動作層作為預 定之通道層12,進行用來賦予ρ_型之雜f(24Mg+)的離 子〉主入以及用來賦予η型之雜質(29Si+)的離子注入，而 於無摻雜基板U上形成p-型領域，並於其上形成η型通 道層12。此外，於預定之源極領域18與沒極領域19,預 定之配線層162及焊塾電極17〇下方之基板表面進行用來 賦予η型之雜質（29Si+)的注人。藉此，可形成η+型源極 領域18及㈣領域19，並同時在歡之焊墊電極17〇及 配線層162下方之基板表面形#高濃度領域16〇、161。 在此，藉由在焊墊電極170與配線層162之下方，設置超 出邊等領域之高濃度領域16〇、161 ’即使將焊墊電極η。 =己線層162直接設置於GaAs基板上，同樣可充分確保 破此間的隔離。 另外’可在形成面濃度領域丨6〇、丨6丨的同時亦在支 ，71形成領域下之基板表面形成作為分離領域之高濃度 ^域100。精此，支柱71和與之鄰接之構成開關電路裝 置的元件（例如FE丁的沒極領域等）的間隔距離可接近至4 β m的程度。 18與汲 層之電 。此外，如第7圖（B)所示，係於前述源極領域 極領域19上’依序真空蒸鍍而層積形成作為第i 314420R1 19 1222191 極之成為歐姆金屬層之AnGe/Ni/Au等3 ^，以形成第！ 源極電極“及第"及極電極16。接著藉由合金化熱處理 形成第1源極電極14與源極領域18、以及第丨沒極電極 16與汲極領域19之歐姆接合。 此外，係於前述通道層12與前述高濃度領域i6〇、i6i 序”工療鍍而層積形成作為第2層之電極之成為閑極 、屬層之Ti/Pt/Au等3層，以形成與通道層i 2接觸之閘 極17 ’第i焊墊電極17以及配線層IQ。 、此外，根據第7圖（C)，係於第！源極電極14與第j 汲極電極16以及第！焊塾電極17〇上，依序真空蒸錄而 層積形成作為第3層之電極之成為焊墊金屬層之τ"ρ"心 等3層以形成與第J源極電極} 4、帛工汲極電極1 &以 及第1 ；!：干墊電極丨7〇接觸之第2源極電極1 3與第2汲極 電極15以及第2焊塾電極177。 另外，矽半導體開關電路裝置的情形，係在設於省略 圖不之同/辰度基板上之磊晶層上，在預定的支柱形成領域 下形成由高濃度領域或L0C0S氧化膜所構成之分離領域 刚，同時形成開關電路裝置的元件，支柱及密封金屬係 以和以下相同的步驟形成（參照第3圖（B)、（C))。With this W, it is possible to use air with a lower dielectric constant than 0FF 314420R1 16 'to block between the source and drain electrodes, that is, between IN and OUT. In the high-frequency signal, the signal leaking to the output side through the molding resin: 80 is completely shielded. Fig. 5 (c) shows the figure of the non-control terminal electrode welding pad iPad. "The sealing metal 70 placed on the FET extends to the control terminal electrode welding pad CtMPad. The control terminals formed by the pad metal layer 3C are contacted with electrode pads CtMpad. A bonding wire 64 is connected to the sealing metal eight. The switching circuit device of the present invention applies a control signal to the aforementioned control terminal CtM to perform a switching operation. Therefore, a potential of 3 V or 0 kDC can be applied to the sealing metal 70 by this structure. The DC potential is a gnd potential relative to the high frequency. Therefore, it can be cut off by looking at the source-non-electrode between the OFF-side FET, that is, between in_out. Therefore, in the high-frequency signal of the input bribe, the signal that leaked to the output side through the molding resin layer 80 in the past will be converted into an electromagnetic field that is diffused into the air in a three-dimensional manner, and can be sealed by the sealing metal 70. All leaky parts are absorbed, so better isolation can be achieved. Here, in this embodiment, the sealing metal 70 is brought into contact with the electrode pad CtMPad for the control terminal, but the sealing metal 70 may be brought into contact with the electrode pad Ctl-2Pad for the control terminal. That is, as long as the terminal to which the dc potential is applied can be connected to the sealing metal, when the switching circuit device is a switching circuit device having a GND terminal, a power voltage terminal, etc.,-the sealing metal 70 and the GND terminal and the power supply must be electrically connected. The terminal electrode 314420R1 17 1222191 can be contacted by solder. In addition, Fig. 6 shows a third embodiment of the present invention. This embodiment has a structure in which a slot is not provided in the sealing metal 70. There will be a detailed description hereinafter, but the present invention realizes a hollow structure by providing a sealing metal 70 on the resist, and then removing the resist. In addition, in order to remove the resist remaining under the sealing metal, a slot is provided in the sealing metal 70 as a path for the resist removing liquid. However, when the area where the resist is to be removed, that is, the area of the hollow portion is small, the resist can be removed even if no slot is provided. Specifically, ‘the area of the Fet part with a hollow structure can be achieved, as long as it is less than 50 ㎡ # 50 a m, the sealing metal can be fully installed without a slot’, and the top of the FET can be completely shielded with a sealing metal. Hereinafter, a method for manufacturing a switching circuit device according to the present invention will be described with reference to FIGS. 7 to 9. The manufacturing method of the switching circuit device of the present invention is to form F] Eir with a channel field, a source field, and a drain field on a semiconductor substrate, and form input terminals, output terminals respectively connected to the foregoing FETs, and apply them. A method for manufacturing a semiconductor switch circuit with electrode pads corresponding to terminals of DC potential, including the steps of forming a pillar around the FET and forming a metal layer supported by the pillar to cover at least the FET; and using a resin layer A step of covering a wafer obtained by integrating the aforementioned FETs. As shown in Fig. 7, the first step of the present invention is to form a switching circuit device on a semiconductor substrate by a known method. That is, a fet having a channel area, a source area, and a drain area is formed on a semiconductor substrate, 314420R1 18 1222191, and a round material connected to the aforementioned FET is formed, an electrode pad for output terminals, and a DC potential are applied. Electrode pads for terminals. That is, as shown in FIG. 7 (A), a compound semiconductor substrate η formed of GaAs or the like is covered with a nitrogen cut film with a penetration ion implantation having a thickness of about 100 to 100 A. Next, in order to select the action layer as the predetermined channel layer 12, ion implantation to impart ρ_-type impurity f (24Mg +)> main implantation and ion implantation to impart n-type impurity (29Si +) were performed, and no doping was performed. A p-type region is formed on the hetero substrate U, and an n-type channel layer 12 is formed thereon. In addition, implantation is performed on the surface of the substrate below the predetermined source region 18 and the non-electrode region 19, the predetermined wiring layer 162, and the solder electrode 170, for imparting n-type impurities (29Si +). Thereby, the n + -type source region 18 and the samarium region 19 can be formed, and at the same time, the substrate surface shape #high concentration regions 16 and 161 below the pad electrode 17 and the wiring layer 162 can be formed at the same time. Here, under the pad electrode 170 and the wiring layer 162, a high-concentration region 160, 161 'in a region such as an edge is provided, even if the pad electrode η is provided. The line layer 162 is directly provided on the GaAs substrate, and the isolation between them can be sufficiently ensured. In addition, the high-concentration region 100, which is a separation region, can be formed on the surface of the substrate under the 71 formation region while forming the surface concentration regions 丨 60 and 丨 6 丨. In this way, the distance between the pillar 71 and the adjacent components (for example, the electrodeless area of the FE diode) constituting the switching circuit device can be close to 4 β m. 18 and the electricity of the drain. In addition, as shown in FIG. 7 (B), it is formed on the source region electrode region 19 by sequential vacuum evaporation and laminated to form an AnGe / Ni / Au which is an ohmic metal layer of the 314420R1 19 1222191 electrode. Wait 3 ^ to form the first! The source electrode "and" and the electrode electrode 16. Then, an ohmic junction between the first source electrode 14 and the source region 18, and the first electrode 16 and the drain region 19 are formed by alloying heat treatment. In addition, Based on the aforementioned channel layer 12 and the aforementioned high-concentration area i60 and i6i sequence "industrial treatment plating, three layers such as Ti / Pt / Au, which serve as the electrode of the second layer and become the idler electrode, are formed to form a layer with The gate electrode 17 ′ of the channel layer i 2 contacts the i-th pad electrode 17 and the wiring layer IQ. In addition, according to Figure 7 (C), tied to the first! The source electrode 14 and the j-th drain electrode 16 and the first! On the welding electrode 17, three layers of τ " ρ " which become the pad metal layer as the electrode of the third layer are sequentially laminated by vacuum evaporation to form the third layer electrode to form the J-th source electrode} 4. Drain electrode 1 & and 1;!: The second source electrode 13 and the second drain electrode 15 and the second welding electrode 177 which the dry pad electrode 70 contacts. In addition, in the case of a silicon semiconductor switching circuit device, a separation composed of a high-concentration area or an L0C0S oxide film is formed on a epitaxial layer provided on a substrate that is different from that shown in the figure and is formed under a predetermined pillar formation area. In the field, the elements, pillars, and sealing metal that simultaneously form the switching circuit device are formed in the same steps as those described below (see FIGS. 3 (B) and (C)).

本發明之第2步驟，如第8圖所示，係在前述FET 周圍开y成支柱，並形成由前述之支柱所支撐、至少覆蓋於 前述FET上之金屬層。 首先’如第8圖（A)所示，係於全面形成阻劑pR1， 並進仃光微影製程，在FET周圍之預定的支柱7 i形成領 20 314420R1 1222191 域選擇性地開孔’然後再將預定之支柱7i形成領域之氮 化膜予以去除GaAs基板露出。 圖中雖圖不僅i組之源極電極、汲極電極、閘極電 極仁只際上係如第1圖所示配置有複數組這## ρετ。 接著如第8圖（Β)所示，全面蒸鑛例如Ti/Pt/Au等 以心成電鍍用底層金屬i 8G。設置新阻劑pR2，並進行在 密封金屬70形成領域選擇性開孔之光微影製程。此外， 密封金屬形成領域上’因形成有可防止阻劑殘留之槽孔， 故槽孔刀〜留有阻劑pR2。在&，由於電鑛用阻劑 係塗佈於全面設置之電鍍用底層金屬上，故與形成支柱時 所設置之阻劑PR1之間，係藉由該電鍍用底層金屬180 而形成上下完全分離狀。 之後，進行鍍金並去除光阻劑PR2，同時以離子清洗 方式洗淨露出之底層金屬180。藉此，可形成與支柱71 體化且貝貝覆蓋FET72上方全面之密封金屬7〇。此 外，也於同時形成槽孔90(第8圖（〇)。 接著，藉由去除形成支柱71時所設置之阻劑pR1， 而在FET2與岔封金屬70之間形成中空部6〇。此時，當 岔封金屬70之面積過大時，即無法完全去除阻劑卩以， 而容易殘留阻劑PR1。為避免此種情形，而於密封金屬7〇 上設置槽孔90,將該槽孔90利用做為阻劑去除液之通路。 阻劑去除液，自鄰接之支柱71之間與槽孔9〇滲透，而將 密封金屬下之阻劑PR1完全去除。藉此形成中空部6〇(第 8 圖（D)) 〇 314420R1 1222191 FET72上之中空部6〇只要能夠遮蔽高頻訊號即可， 而無須没侍很厚。根據上述方法，即使為了形成中空部6〇 而設置密封金屬70 ’亦因接合線（bonding Wire)的高度夠 高，與之相比形成密封金屬所致之晶片厚度的增加可忽 視，因此封裝外形的厚度不會變大。 此外，第4圖所示之第2實施形態，係在使第8圖（A) 之支柱7 1部分露出之光微影製程中，使要與密封金屬川 接觸之控制端子用電極焊塾CtMPad部分亦同時開口。 之後，進行第8圖（B)至第8圖（D)之步驟，而如第8 圖（E)所不一般，形成與控制端子用電極焊墊 分接觸之密封金屬7〇。 本發明之第3步驟，係利用樹脂層覆蓋將前述FET 集積化而成的晶片。 半導體開關電路裝置在完成前段步驟後，即移行至進 行組裝的後段步驟。晶圓狀之半導體晶片經切割而分離為 個別之半導體晶片’將半導體晶片〇固定於引線62之島 後’利用接合線64使半導體晶片63的焊墊電極與^線 Μ連接。使用金屬細線做為接合線M，並利用眾所周知 之球形接合（baU bonding)進行連接。之後，再經由移轉模 塑進行樹脂封裝，而獲得第2圖(八)或第5圖⑷ 最 終構造。 Μ 在此’密封金屬70與FET72係以丄至2//m程度的 距離隔開設置’使樹脂無法進入該空間内。此夕卜因槽孔 90具有2"以5"m程度的寬度，故樹脂亦無法由此曰流 314420R1 22 入。亦即，藉由設 _ , 夏由支柱71所支撐之密封金屬70，即 可在一般的樹脂模塑 — 乂步驟中，於FET上形成中空部60。 精此，除可利用 .^ ^ 心封金屬在FET72與樹脂層80間形 成遮敝，同時亦可刹 』、 〜用比介電常數低之空氣於FET的源 極-汲極間，亦即關 P開關之IN-OUT間形成遮蔽，以達到防 止兩頻訊號漏洩之目的。 使封裳件内部呈中空狀之方法中有一種··將罩蓋（哪） 甘定於載置有半導體晶片之引線架上進行模塑之方法，但 疋此時’ f導致罩蓋之材料費、及固定罩蓋之工時數的成 本增加。然而，根據本發明之製造方法，X需藉由在晶圓 上形成該開關電路元件的晶圓製造步驟即可實現中空構 造，因此相較於在組裝步驟中實現中空構造，更具有可大 幅降低成本之優點。 在此’藉由第9圖說明本發明之第3實施形態（第6 圖）之製造方法。本實施形態，並不在密封金屬7〇上設置 槽孔’而以密封金屬70全面覆蓋於FET上。當要形成中 空部之FET形成領域面積小於5〇 # mx 5〇 # m時，密封 金屬70上可不設置槽孔。此乃因為當密封金屬7〇之面積 較小時’僅精由從鄰接之端子7 1間渗入之阻劑去除液即 可充分去除阻劑PR1之故。 亦即，在形成元件領域後，進行選擇性地在支柱7 1 部開孔的光微影製程，並於完成氮化膜之蝕刻後，形成錢 金之底層電極1 80。然後舖設新的阻劑PR2，並進行選擇 性地在密封金屬70部分開孔的光微影製程（第9圖（A))。 23 314420R1 1222191 之後’進行鐘金並去除阻劑PR2，並以離子清洗方式 洗淨露出之底層電極。接著再去除阻劑pR1，以形成中空 部60(第9圖（B))。 之後，進行樹脂模塑，而形成最终構造（第2圖（八）、 第5圖（A))。 發明之效杲 如以上所詳述一般，藉由本發明可獲得以下效果。 第1 ’在FET上設置密封金屬，使FET與密封金屬 間呈中空&，藉此，即可抑制〇FF側之而之源極-汲極 電極間(m-ουτ間)之高頻訊號的漏、;矣。除可利用密封金 屬遮蔽樹脂層貞FET之外，亦可利用比介電常數低的空 氣在FET之源極-汲極間形成遮蔽，亦即在開關的IN_0UT 間形成遮蔽，而防止高頻訊號之漏洩。 第2 ’使密封金屬與控制端子用電極焊墊接 觸’藉此’可更進一步提昇隔離效果。 本發明之開關電路步署 # t置係將0V或3V的控制訊號 施加於控制端子ctM以進行開關動作因此亦可夢由 該構造將3V 5戈0V之Dc電位施加於密封金㉟7〇。^電 ，相對於高頻而言為GND電位，因此，可藉由_電 在OFF側FET之源極j及極電極間形成遮斷、亦即在 !^〇UT間形成遮斷。因此，輸入㈣側FET之高頻訊 ^ 往經由模塑樹脂層80而漏泡至輸出側之訊號， ::為以3次元方式擴散於空氣中的電磁場，而可由密封 屬7〇將所有漏^的部份吸收掉，故可實現隔離效果更 314420R1 24 佳的構造。 此外根據本發明之製造太、表-Γ ^ a 電路裝置之製造# h 可在晶圓上形成開關In the second step of the present invention, as shown in FIG. 8, a pillar is formed around the FET, and a metal layer supported by the pillar and covering at least the FET is formed. First, 'as shown in Figure 8 (A), it is based on the comprehensive formation of the resist pR1, and the photolithography process is performed to form a collar 20 314420R1 1222191 in the predetermined pillar 7 i around the FET. The nitride film in the predetermined pillar 7i formation region is removed, and the GaAs substrate is exposed. Although the figure shows not only the source electrode, the drain electrode, and the gate electrode of the group i, the complex array ## ρετ is arranged as shown in FIG. 1. Next, as shown in FIG. 8 (B), a full-steaming process such as Ti / Pt / Au is performed to form the underlying metal i 8G for electroplating. A new resist pR2 is set, and a photolithography process for selectively opening holes in the formation area of the sealing metal 70 is performed. In addition, since a slot hole is formed in the sealing metal formation field to prevent the resist from remaining, the slot hole cutter ~ resistor pR2 remains. In &, because the resistive agent for electric mining is coated on the underlayer metal for plating which is provided in a comprehensive manner, it is completely formed up and down by the underlayer metal 180 for electroplating provided with the resister PR1 provided when the pillar is formed. Separated. After that, gold plating is performed to remove the photoresist PR2, and at the same time, the exposed underlying metal 180 is cleaned by ion cleaning. Thereby, a sealing metal 70 which is integrated with the pillar 71 and covers the entire area above the FET 72 can be formed. In addition, a slot 90 is also formed at the same time (FIG. 8 (0). Next, a hollow portion 60 is formed between the FET 2 and the branch sealing metal 70 by removing the resist pR1 provided when the pillar 71 is formed. This At this time, when the area of the fork sealing metal 70 is too large, the resist cannot be completely removed, and the resist PR1 is easily left. To avoid this, a slot 90 is provided on the sealing metal 70, and the slot is 90 is used as a passage for the resist removal liquid. The resist removal liquid penetrates between the adjacent pillars 71 and the slot 90 to completely remove the resist PR1 under the sealing metal. This forms a hollow portion 60 ( (Figure 8 (D)) 〇314420R1 1222191 Hollow portion 60 on FET72 can be used to shield high-frequency signals without having to be very thick. According to the above method, even if a sealing metal 70 is provided to form hollow portion 60, Also, the height of the bonding wire is high enough that the increase in the thickness of the wafer due to the formation of the sealing metal can be ignored, so the thickness of the package shape does not increase. In addition, the second one shown in Figure 4 The embodiment is based on part 1 of the pillar 7 of FIG. 8 (A). In the exposed light lithography process, the CtMPad portion of the electrode welding pad for the control terminal to be in contact with the sealed metal channel is also opened at the same time. After that, the steps of FIG. 8 (B) to FIG. 8 (D) are performed, and Fig. 8 (E) shows an unusual case in which a sealing metal 7 is formed in contact with the electrode pads for the control terminals. The third step of the present invention is to cover a wafer formed by integrating the aforementioned FETs with a resin layer. Semiconductor switch circuit After the device completes the previous steps, it moves to the later steps of assembly. The wafer-shaped semiconductor wafer is cut and separated into individual semiconductor wafers. 'After fixing the semiconductor wafer 0 to the island of the lead 62', the semiconductor wafer is bonded by the bonding wire 64. The pad electrode of 63 is connected to the wire M. A thin metal wire is used as the bonding wire M, and the connection is made by a well-known ball bonding (baU bonding). Then, resin molding is performed by transfer molding to obtain the second image (VIII) or Figure 5. ⑷ Final structure. Μ Here, 'the sealing metal 70 and FET72 are separated by a distance of about 丄 to 2 // m' so that resin cannot enter the space. The slot 90 has a width of about 2 " to 5 " m, so the resin cannot flow in from this flow 314420R1 22. That is, by setting _, the sealing metal 70 supported by the pillar 71 can be used in general Resin molding — In the step, a hollow portion 60 is formed on the FET. In addition, it can be used. ^ ^ The heart-sealing metal can form a shield between the FET 72 and the resin layer 80, and at the same time can also be used. The low constant air forms a shield between the source-drain of the FET, that is, between the IN-OUT of the P switch, so as to prevent the leakage of two-frequency signals. One of the methods to make the inside of the seal is hollow ... The method of molding the cover (which) is fixed on the lead frame on which the semiconductor wafer is placed, but at this time, 'f leads to the material cost of the cover. The cost of working hours for fixing the cover increases. However, according to the manufacturing method of the present invention, X needs to realize the hollow structure through the wafer manufacturing step of forming the switching circuit element on the wafer, and therefore, compared with implementing the hollow structure in the assembly step, it has a significant reduction. Cost advantage. Here, the manufacturing method of the third embodiment (Figure 6) of the present invention will be described with reference to Figure 9. In the present embodiment, the sealing metal 70 is not provided with a slot hole ', and the entire area of the FET is covered with the sealing metal 70. When the area of the FET formation region where the hollow portion is to be formed is less than 50 ° # mx 50 ° # m, the sealing metal 70 may not be provided with a slot. This is because when the area of the sealing metal 70 is small, the resist PR1 can be sufficiently removed only by the resist removing liquid that penetrates between the adjacent terminals 71. That is, after the element field is formed, a photolithography process for selectively opening holes in the pillar 7 1 is performed, and after the etching of the nitride film is completed, a gold bottom electrode 1 80 is formed. Then, a new resist PR2 is laid, and a photolithography process for selectively opening holes in the sealing metal 70 portion is performed (Fig. 9 (A)). 23 314420R1 1222191 After that, perform bell metal and remove the resist PR2, and clean the exposed bottom electrode by ion cleaning. Then, the resist pR1 is removed to form a hollow portion 60 (Fig. 9 (B)). Thereafter, resin molding is performed to form a final structure (FIG. 2 (8), FIG. 5 (A)). Effects of the Invention As described in detail above, the following effects can be obtained by the present invention. First, a sealing metal is provided on the FET so that the FET and the sealing metal are hollow & thereby, the high-frequency signal between the source-drain electrode (m-ουτ) on the 0FF side can be suppressed. Leak ,; 矣. In addition to using a sealed metal to shield the resin layer FET, it is also possible to use air with a lower dielectric constant to form a shield between the source and the drain of the FET, that is, to form a shield between the IN_0UT of the switch to prevent high-frequency signals Leak. The second "contacting the sealing metal with the electrode pad for the control terminal" can further improve the isolation effect. The switching circuit step #t of the present invention is to apply a control signal of 0V or 3V to the control terminal ctM to perform a switching operation. Therefore, it is also possible to apply this structure to apply a Dc potential of 3V to 5V to the sealing metal 〇70. ^ Electricity is GND potential relative to high frequency. Therefore, it is possible to use _Electricity to form an interruption between the source j and the electrode of the OFF-side FET, that is, to form an interruption between! ^ 〇UT. Therefore, the high-frequency signal of the input FET side ^ leaks to the output side through the molding resin layer 80, and :: is an electromagnetic field that diffuses into the air in a three-dimensional manner, and can be leaked by the sealing metal 70. ^ Part is absorbed, so it can realize a better structure with better isolation effect 314420R1 24. In addition, according to the present invention, the manufacture of the Tai-Mei-Γ ^ a circuit device manufacturing # h can form a switch on the wafer

衣&過备中輕易地在FET 中空封裝件之製 乂1f I邛。在 半導體曰片之以 有-種··將罩蓋固定於載置有 架而進行模塑之方法，但是此時，會導 ip ,,, 、 罩盍之工時數的成本增加。麸而， 根據本發明之掣生 日刀热而 路元株夕曰m ^ ,，只需利用在晶圓上形成該開關電Fabrication & preparation of FET hollow package easily 乂 1f I 邛. There are several types of semiconductor chips: a method of fixing the cover to a rack for molding, but at this time, the cost of the man-hours of the ip ,,,, and the mask increases. However, according to the invention, the sun-knife is hot and the road element is m ^, and only the switch circuit is formed on the wafer.

凡件之晶圓製造舟辨1 gf7~~TA 步驟中本W 貫現中空構造，相較於在組裝 V鄉中貫現中空構且 > 八有了大幅降低成本之優點。此外， = 且裝步驟中實現中空構造之方法，因並無法吸收化為以 =元方式擴散於空氣中的電磁場之漏茂訊號，故本發明 i造方法相較於在組裝步驟中形成中空構造，不僅可降 氐成本，同時亦有助於特性之提昇。 【圖式簡單說明】 第1圖係用以說明本發明之平面圖。 第2圖（A)及（B)係用以說明本發明之剖面圖。 第3圖（A)至（C)係用以說明本發明之剖面圖。 第4圖係用以說明本發明之平面圖。 第5圖（A)至（C)係用以說明本發明之剖面圖。 第6圖係用以說明本發明之平面圖。 第7圖（A)至（C)係用以說明本發明之製造方法之剖面 第8圖（A)至（E)係用以說明本發明之製造方法之剖面 圖。 314420R1 25 1222191 213 閘極氧化膜 215 氮化膜 217 閘極電極 219 汲極領域 214 汲極電極 216 源極電極 218 源極領域 Ctl-l，Ctl-2控制端子 FET1，FET2薄膜電晶體 IN輸入端子 LD 低濃度的雜質領域 〇UTl，OUT2輸出端子 PR1，PR2 阻劑 R1，R2 電 INPad，0UTlPad，0UT2Pad，Ctl-lPad，Ctl-2Pad 電極焊塾 27 314420R1In the wafer fabrication process of every piece of wafer, 1 gf7 ~~ TA steps have shown the hollow structure, compared with the hollow structure in the assembly V village and > Eight has the advantage of significantly reducing costs. In addition, the method of achieving a hollow structure in the assembly step cannot absorb and convert into a leaky signal of an electromagnetic field that diffuses into the air in a = element manner. Therefore, the manufacturing method of the present invention is compared to forming a hollow structure in the assembly step. , Not only can reduce the cost, but also help improve the characteristics. [Brief description of the drawings] FIG. 1 is a plan view for explaining the present invention. Figures 2 (A) and (B) are sectional views for explaining the present invention. 3 (A) to (C) are sectional views for explaining the present invention. Fig. 4 is a plan view for explaining the present invention. 5 (A) to (C) are sectional views for explaining the present invention. Fig. 6 is a plan view for explaining the present invention. Figures 7 (A) to (C) are cross-sections for explaining the manufacturing method of the present invention. Figures 8 (A) to (E) are cross-sections for explaining the manufacturing method of the present invention. 314420R1 25 1222191 213 Gate oxide film 215 Nitride film 217 Gate electrode 219 Drain area 214 Drain electrode 216 Source electrode 218 Source area Ctl-1, Ctl-2 control terminal FET1, FET2 thin film transistor IN input terminal LD Low-concentration impurity field 〇UT1, OUT2 output terminal PR1, PR2 Resistor R1, R2 Electric INPad, OUT1Pad, OUT2Pad, Ctl-1Pad, Ctl-2Pad Electrode welding pad 27 314420R1

Claims (1)

拾、申請專利範圍： Ί半導體_電路裝置，係由：在半導體基板表面 设置源極電極、閘極電極及汲極電極而成之至少一個 FET;以及分別與和前述ρΕΤ之源極電極或汲極電極 連接之至少一個輸入端子、和前述阳之沒極電極或 源極電極連接之至少一個輸出端子、及用以對前述FET 施加DC電位之端子對應的電極焊墊所構成，其特徵 為具備： 设於前述FET的周圍之支柱； 由前述支柱所支撐，至少實質覆蓋於前述FET上 之金屬層；以及 覆蓋將前述FET集積化而成的晶片之樹脂層。 2·如申請專利範圍第丨項之半導體開關電路裝置，其中， 由前述金屬層與前述FET所形成的空間係中空。 3· $申請專利範圍第i項之半導體開關電路裝置，其中， 月、J述金屬層與前述FET，係以前述樹脂層無法進入之 距離隔開。 4.如申請專利範圍第3項之半導體開關電路裝置，其中， 前述金屬層與前述FET係以〇.5…3…距離隔 開。 ^如申請專利範圍第1項之半導體開關電路裝置，其中， 前述金屬層係金屬電鍍層。 6.如申請專利範圍第1項之半導體開關電路裝置，其中， 前述金屬層上設有複數個孔。 314420R1 28 1222191 7·如申請專利範圍第1項之半導體開關電路裝置，其中， 过金屬層’係與和用以施加前述DC電位之端子對 應的電極焊墊接觸。 I如申請專利範圍第1項之半導體開關電路裝置，其中， 刖述金屬層係覆蓋前述FET上之全面而設置。 9·如申凊專利範圍帛1項之半導體開關電路裝置，其中， 、’述支柱之下的如述基板設有分離領域。 ▲申明專利範圍帛9項之半導體開關電路裝置，其中， 前述支柱與鄰接的該開關電路裝置之元件係相接近而 一種半導體開關電路裝置之製造方法，係在半導體基 板上形成具有通道領域、源極領域及汲極領域之FET， 並形成分別與和前被F p τ、* 及用以施加DC電位之端/子 '輸㈣子 子對應之電極焊塾之半導體 開關電路褒置之製造方法，其特徵為具備： 在周圍形成支柱，並形成由前述支柱所 以：4質覆蓋於前述啦上的金屬層之步驟； 步驟。 〜^木檟化而成的晶片 12.如申請專利範圍第u項之 方法，其中，具備：至少於，Π關電路裝置之製 並於形成前述金屬#後 ^L ETi形成阻劑遮罩 述而與前述金屬;之/除前述阻劑遮罩，而使男 屬層之間形成中空之步驟。 314420R1 29 1222191 13.如申請專利範圍第12項之半導體開關電路裝置之，】 方法’其中’在形成前述金屬層時，係於該金屬1 製造 形成複數個孔，並在去除前述阻劑遮罩之步驟e上 前述孔利用做為阻劑遮罩去除液之通道。 ’將 14·如申請專利範圍第丨丨項之半導體開關電路裝 ， 方法，其中，前述金屬層係由金屬畲^ 之製造 蜀电鍍所形成。 15.如申請專利範圍第U項之半導體開關電路裝置制 方法，其中，在形成前述支柱之前，力之製造 在支桎形成領托 的前述基板表面形成分離領域。 #織 314420R1 30Scope of patent application: ΊSemiconductor_circuit device, which is composed of: at least one FET formed by setting a source electrode, a gate electrode, and a drain electrode on the surface of a semiconductor substrate; and a source electrode or a drain connected to the aforementioned ρΕΤ respectively. The at least one input terminal connected to the electrode electrode, the at least one output terminal connected to the anode electrode or the source electrode, and an electrode pad corresponding to a terminal for applying a DC potential to the FET are characterized in that: : A pillar provided around the FET; a metal layer supported by the pillar, at least substantially covering the FET; and a resin layer covering a wafer obtained by integrating the FET. 2. The semiconductor switch circuit device according to the first item of the patent application, wherein the space formed by the metal layer and the FET is hollow. 3. The semiconductor switch circuit device according to item i of the patent application scope, wherein the metal layer of the month and the J is separated from the FET by a distance that the resin layer cannot enter. 4. The semiconductor switch circuit device according to item 3 of the scope of patent application, wherein the metal layer and the FET are separated by a distance of 0.5 ... 3 .... ^ The semiconductor switch circuit device according to the first patent application range, wherein the aforementioned metal layer is a metal plating layer. 6. The semiconductor switch circuit device according to item 1 of the patent application scope, wherein the metal layer is provided with a plurality of holes. 314420R1 28 1222191 7. The semiconductor switch circuit device according to item 1 of the patent application range, wherein the through metal layer is in contact with an electrode pad corresponding to a terminal for applying the aforementioned DC potential. I The semiconductor switch circuit device according to item 1 of the scope of patent application, wherein the metal layer is provided so as to cover the entire surface of the FET. 9. The semiconductor switch circuit device according to claim 1 of the patent scope, wherein the substrate under the pillars as described above is provided with a separation field. ▲ The semiconductor switch circuit device with a patent scope of 9 items, wherein the aforementioned pillar is close to the adjacent components of the switch circuit device and a method of manufacturing a semiconductor switch circuit device is to form a semiconductor substrate with a channel field and a source on the semiconductor substrate. Manufacturing method of FETs in the electrode field and the drain field, and forming a semiconductor switch circuit arrangement corresponding to the electrode pads corresponding to the front end F p τ, * and the terminal / sub-input terminal for applying a DC potential It is characterized by having the steps of: forming a pillar around and forming the pillar by the pillar, so: a step of covering the metal layer on the substrate; ~ ^ Woodenized wafer 12. The method according to item u of the patent application scope, which includes: at least, the system of the circuit device and the formation of a resist mask after forming the aforementioned metal # ^ L ETi And the aforementioned metal; and / or the step of removing the aforementioned resist mask to form a hollow between the male layers. 314420R1 29 1222191 13. As for the semiconductor switch circuit device of the 12th scope of the patent application, the method 'wherein' is to form a plurality of holes in the metal 1 when forming the aforementioned metal layer, and remove the aforementioned resist mask The aforementioned hole in step e is used as a channel for the resist masking removal liquid. 14. A method for mounting a semiconductor switch circuit according to item 丨 丨 in the scope of application for a patent, wherein the aforementioned metal layer is formed by metal electroplating. 15. The method of manufacturing a semiconductor switch circuit device according to the U.S. patent application scope, wherein, before forming the aforesaid pillar, the manufacturing of the force forms a separation area on the surface of the substrate on which the collar is formed. #Woven 314420R1 30
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