JP4945895B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device with high moisture resistance and high output that operates at a high frequency of, for example, 1 GHz or more.

  In an integrated circuit for ultra-high-speed optical communication, or an integrated circuit used in microwave or millimeter wave, etc., it has been structured so as to be accommodated in a hermetically sealed package. There was no need to consider.

  However, in recent years, it has become an era in which cost reduction is severely demanded, and bare chip mounting using a package that is reduced in price by making it non-hermetic is being put into practical use.

  When mounting a semiconductor chip on a bare chip, it must be sealed with a mold resin in order to ensure moisture resistance of the semiconductor chip.

  Conventionally, a mold resin-sealed semiconductor device is known, and in such a semiconductor device, it is also known to cover with a dielectric film in order to protect the gate (for example, Patent Document 1). , See Patent Document 2).

  In order to maintain the performance of the semiconductor chip at a higher frequency, flip chip mounting is performed. In that case, in order to ensure connection reliability, an underfill made of, for example, epoxy resin is provided between the chip and the mounting substrate. Injection and solidification is performed.

  In order to adjust the coefficient of thermal expansion, a filler made of silica having a diameter of about 10 μm is mixed with the mold resin and underfill used when performing such bare chip mounting.

  FIG. 9 is a plan view of the main part showing a conventional semiconductor device mounted on a bare chip. In FIG. 9, 1 is a thin line gate, 2 is a source, 3 is a drain, 10 is a gate wiring connecting the thin line gates, 13G Represents a wiring for deriving a gate wiring, and 13D represents a wiring for deriving a drain.

  FIG. 10 is a side view of a principal part showing a portion of the semiconductor device shown in FIG. 9 cut along a line XX in the figure. The same reference numerals as those used in FIG. In the figure, reference numeral 21 denotes a protective film made of SiN, 31 denotes an active region (transistor region), and 50 denotes a semiconductor substrate.

  FIG. 11 is a cutaway side view of the main part showing a state in which the semiconductor device shown in FIG. 10 is covered with a mold resin, and the cut surface is the same as the line XX in FIG. The same symbols used indicate the same parts or have the same meaning.

  In the figure, 51 is a filler, 51D is a portion where the gate wiring is damaged by the filler, and 52 is a mold resin.

  In the semiconductor device shown in FIG. 11, in order to mold with the mold resin 52, a portion to be molded is put into a mold, and the resin is press-fitted into the mold, but a protective film covering the gate wiring 10 21 is formed to be quite thin and is usually about 0.2 μm, and is damaged when the filler 51 mixed in the mold resin 52 collides with the protective film 21.

  When the protective film 21 is damaged, moisture easily enters from that portion, and the moisture resistance of the semiconductor device is lowered. In order to avoid this, if the protective film 21 is made thicker, it will be considered that it can withstand the damage caused by the filler 51. However, in such a case, the film stress of the protective film increases, and the film peels off. As a result, a process failure occurs and the manufacturing yield decreases. In addition, the deposition time of the protective film and the etching process time for opening the pad window become long, and thus the manufacturing cost increases. Furthermore, the protective film 21 made of SiN or the like has a relatively large dielectric constant of about 8. Therefore, when the thickness is increased, the parasitic capacitance increases and the high-frequency characteristics deteriorate, making it difficult to realize a high-performance semiconductor device. Become.

  12 is a fragmentary side view showing a case where the semiconductor device shown in FIG. 10 is flip-chip mounted. The cut surface of the semiconductor device is a line XX as in FIG. The same symbols as used in the above description represent the same parts or have the same meaning.

  In the figure, reference numeral 60 denotes a mounting substrate, and the semiconductor device is upside down. Therefore, the surface side of the semiconductor device is opposed to the mounting substrate 60, and an underfill 53 is injected and solidified therebetween.

Also in this case, when the underfill 53 is injected between the mounting substrate 60 and the surface side of the semiconductor device, an accident occurs in which the filler 51 damages the protective film 21, and the semiconductor device sealed with the mold resin described with reference to FIG. The exact same problem occurs as in.
JP-A-7-94642 Japanese Patent Laid-Open No. 8-83813

  According to the present invention, it is possible to realize a high-frequency and high-power semiconductor device with low manufacturing cost by ensuring the high moisture resistance by suppressing the problem of moisture resistance deterioration of the semiconductor device in the conventional bare chip mounting by a simple configuration. To.

  The semiconductor device according to the present invention is basically provided with a protective metal film that covers a gate wiring connecting a plurality of thin line-shaped gates constituting a comb-shaped gate through an insulating film.

  By adopting the above means, in a semiconductor device to be mounted on a bare chip or a semiconductor device to be mounted on a flip chip, even if a mold resin or underfill in which a thermal expansion coefficient is adjusted by mixing a filler is used, As a result, there is no possibility that the protective film such as the gate wiring is damaged. Therefore, the penetration of moisture is reduced, and a high-frequency and high-power semiconductor device in which high moisture resistance is ensured can be easily realized.

  In the semiconductor device according to the present invention, a protective metal film is further disposed on a protective film made of an insulator covering a gate wiring connecting a plurality of thin gates, and the gate protective film and the gate wiring are damaged from the outside. As a result, a high-frequency and high-power semiconductor device with improved moisture resistance is obtained.

  FIG. 1 is a plan view of a principal part showing a semiconductor device according to the present invention, and FIG. 2 is a side view of a principal part showing a part of the semiconductor device of FIG. 1 cut along a line XX in the figure. The same symbols as those used in FIGS. 9 to 12 represent the same parts or have the same meaning.

  The semiconductor device shown in FIGS. 1 and 2 is different from the semiconductor device shown in FIGS. 9 to 12 in that a protective metal film 41 is formed on the protective film 21 covering the gate wiring 10 connecting the plurality of thin line gates 1. It is a point that is formed. In this case, the region width of the gate wiring 10 exposed without being covered with the protective metal film 41 can be made smaller than the diameter of the filler (for example, 10 μm). It is possible to avoid damage, and further damage to the protective film 21, and therefore moisture penetration is suppressed and moisture resistance is improved. Further, since the protective metal film 41 can be formed by changing the layout pattern only and can be formed simultaneously with other wiring such as the drain wiring 13D, the number of processes does not increase.

  3 is a cutaway side view of the main part showing a state in which the semiconductor device described with reference to FIGS. 1 and 2 is covered with a mold resin, and the cut surface is a line XX as in FIG. The symbols used in FIGS. 9 to 12 represent the same parts or have the same meaning.

  Since the semiconductor device according to the present invention has the structure described with reference to FIGS. 1 and 2, even if the surface of the semiconductor device is molded with resin as shown in FIG. The protective film 21 covering the film is not damaged. Therefore, there is less risk of moisture entering and reliability is improved.

  4 is a cutaway side view of a principal part showing a state where the semiconductor device described with reference to FIGS. 1 and 2 is flip-chip mounted. The cut surface of the semiconductor device is a line XX as in FIG. The symbols used in FIGS. 3 and 9 to 12 represent the same parts or have the same meaning.

  Also in the case of flip-chip mounting as shown in FIG. 4, since the semiconductor device according to the present invention has the structure described with reference to FIGS. 1 and 2, an underfill is formed between the mounting substrate 60 and the surface side of the semiconductor device. When 53 is injected, the protective film 21 covering the gate wiring 10 is not damaged by the filler 51. Therefore, there is less risk of moisture entering and reliability is improved.

  By the way, it is preferable that the protective metal film 41 shown in FIG. 2 has an interval L with other wirings, for example, an interval L with the drain wiring 13D of 10 μm or less. The reason is that the diameter of the current filler 51 is about 10 μm at the minimum, and therefore, if the interval L is set to 10 μm or less, the filler 51 can be prevented from entering the portion.

  Further, if the protective metal film 41 is not connected to any terminal and is in a so-called floating state, the parasitic capacitance does not increase, which is preferable for a semiconductor device operating at a high frequency.

  As another means for suppressing an increase in parasitic capacitance due to the provision of the protective metal film 41, it is effective to reduce the area of the protective metal film 41 as much as possible to reduce the overlap with the gate wiring 10. is there.

  FIG. 5 is a plan view of a principal part showing a semiconductor device in which the area of the protective metal film is reduced, and FIG. 6 is a side view of the principal part showing a part of the semiconductor device of FIG. 5 cut along line XX in the figure. The symbols used in FIGS. 1 to 4 and FIGS. 9 to 12 represent the same parts or have the same meaning.

  The semiconductor device shown in FIGS. 5 and 6 is different from the semiconductor device described with reference to FIGS. 1 to 4 in that the protective metal film 41 does not cover the entire gate wiring 10 and the transistor is manufactured. This is to cover the minimum necessary area only on the side close to the region 31. By doing so, an increase in parasitic capacitance due to the formation of the protective metal film 41 is also suppressed, and at a high frequency. A semiconductor device suitable for operation is realized.

  By the way, the reason why the protective metal film 41 is formed so as to cover the side close to the active region is that moisture intrusion is generally caused by electromigration and accelerated in proportion to the potential difference. Usually, in the case of a high-power semiconductor device, the potential difference between the gate wiring 10 and the drain wiring 13D is the largest, and strengthening this portion is effective for improving electromigration resistance. Leave on the 13D side.

  FIG. 7 is a plan view of a principal part showing a semiconductor device in which a protective metal film is connected to a source wiring. FIG. 8 is a side view of a principal part showing a part of the semiconductor device in FIG. 7 cut along line XX in the figure. The symbols used in FIGS. 1 to 6 and 9 to 12 represent the same parts or have the same meaning.

  The semiconductor device shown in FIGS. 7 and 8 is different from the semiconductor device described with reference to FIGS. 1 to 6 in that the protective metal film 41 is connected to the source wiring 13S. In this case, the grounding parasitic capacitance is Although it increases, the area covered with the protective metal film 41 becomes wider when compared with the semiconductor device described with reference to FIGS. 5 and 6, so that damage to the gate wiring 10 due to the filler is reduced. Therefore, it is effective for ensuring moisture resistance.

It is a principal part top view showing the semiconductor device by this invention. FIG. 2 is a cutaway side view of a main part showing a location where the semiconductor device of FIG. 1 is cut along line XX in the drawing. FIG. 3 is a cut-away side view of an essential part showing a state where the semiconductor device described with reference to FIGS. 1 and 2 is covered with a mold resin. FIG. 3 is a cutaway side view of a main part showing a state where the semiconductor device described with reference to FIGS. 1 and 2 is flip-chip mounted. It is a principal part top view showing the semiconductor device which reduced the area of the protective metal film. FIG. 6 is a fragmentary cutaway side view showing a location where the semiconductor device of FIG. 5 is cut along line XX in the drawing. It is a principal part top view showing the semiconductor device which connected the protective metal film with the source wiring. FIG. 8 is a fragmentary cutaway side view showing a location where the semiconductor device of FIG. 7 is cut along line XX in the drawing. It is a principal part top view showing the conventional semiconductor device mounted with a bare chip. FIG. 10 is a cutaway side view of a main part showing a location where the semiconductor device shown in FIG. 9 is cut along line XX in the drawing. It is a principal part cutting side view showing the state which coat | covered the semiconductor device shown in FIG. 10 with the mold resin. FIG. 11 is a cutaway side view of a main part showing a case where the semiconductor device shown in FIG. 10 is flip-chip mounted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Fine line gate 2 Source 3 Drain 10 Gate wiring which connects thin line gate 13G Wiring which derives gate wiring 13D Wiring which derives drain 13S Wiring which derives source 21 Protection film 31 Active region (transistor region)
41 Protective metal film 50 Semiconductor substrate 51 Filler 51D Location where gate wiring is damaged by filler 52 Mold resin 53 Underfill 60 Mounting substrate

Claims (4)

A semiconductor device comprising a protective metal film that covers a gate wiring formed outside an active region connecting a plurality of thin-line gates formed on an active region constituting a comb-shaped gate only outside the active region via an insulating film Is mounted on a mounting substrate by flip chip mounting, and an underfill resin is filled between the semiconductor device and the mounting substrate . 2. The gap between the protective metal film that covers the gate wiring only outside the active region through the insulating film and the other metal film is less than the diameter of the filler contained in the mold resin or underfill. Semiconductor device. 3. The semiconductor according to claim 1, wherein the protective metal film that covers the gate wiring only outside the active region through the insulating film is provided in a floating state without being connected to any terminal. apparatus. 4. The semiconductor device according to claim 1, wherein a protective metal film that covers the gate wiring only outside the active region via an insulating film is formed only on a side close to the transistor region.

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