JP6326781B2

JP6326781B2 - Field effect transistor

Info

Publication number: JP6326781B2
Application number: JP2013240850A
Authority: JP
Inventors: 俊介湊
Original assignee: Nichia Corp
Current assignee: Nichia Corp
Priority date: 2013-11-21
Filing date: 2013-11-21
Publication date: 2018-05-23
Anticipated expiration: 2033-11-21
Also published as: JP2015103549A

Description

本発明は、電界効果トランジスタに関する。 The present invention relates to a field effect transistor.

電界効果トランジスタは、ソース電極、ドレイン電極、ゲート電極を含んで構成される。この電極構造の一例として、特許文献１には、フィンガー状の電極構造が開示されている。特許文献１に開示された電極構造では、半導体層の上に、それぞれフィンガー状のソース電極とドレイン電極が、互いに所定の間隔を隔てて交互に形成され、ソース電極とドレイン電極の間にゲート電極が形成されている。以下、本明細書において、ソース電極とドレイン電極が所定の間隔を隔てて対向している領域を動作領域という。特許文献１の電界効果トランジスタでは、動作領域の上に絶縁膜を形成して、その絶縁膜の上にソースパッド電極、ドレインパッド電極及びゲートパッド電極を分離して形成し、ソース電極とソースパッド電極間、ドレイン電極とドレインパッド電極間及びゲート電極とゲートパッド電極間とがそれぞれ、ソース電極、ドレイン電極及びゲート電極の上の絶縁膜に形成された開口部を介して接続されている。また、本明細書において、ソース電極、ドレイン電極及びゲート電極の種類を特定する必要がなく、パッド電極と区別する必要があるときは、ソース電極、ドレイン電極及びゲート電極を単に電極といい、ソースパッド電極、ドレインパッド電極及びゲートパッド電極を単にパッド電極という。 The field effect transistor includes a source electrode, a drain electrode, and a gate electrode. As an example of this electrode structure, Patent Document 1 discloses a finger-like electrode structure. In the electrode structure disclosed in Patent Document 1, finger-like source electrodes and drain electrodes are alternately formed on a semiconductor layer at predetermined intervals, and a gate electrode is provided between the source electrode and the drain electrode. Is formed. Hereinafter, in this specification, a region where a source electrode and a drain electrode are opposed to each other with a predetermined interval is referred to as an operation region. In the field effect transistor of Patent Document 1, an insulating film is formed on an operation region, and a source pad electrode, a drain pad electrode, and a gate pad electrode are separately formed on the insulating film, and the source electrode and the source pad are formed. The electrodes, the drain electrode and the drain pad electrode, and the gate electrode and the gate pad electrode are connected to each other through an opening formed in an insulating film on the source electrode, the drain electrode, and the gate electrode. In addition, in this specification, when it is not necessary to specify the types of the source electrode, the drain electrode, and the gate electrode and it is necessary to distinguish from the pad electrode, the source electrode, the drain electrode, and the gate electrode are simply referred to as an electrode. The pad electrode, drain pad electrode, and gate pad electrode are simply referred to as pad electrodes.

特開２０１２−２３０７４号公報JP 2012-23074 A

しかしながら、ソース電極、ドレイン電極及びゲート電極の直上に形成された開口部を介して当該電極とパッド電極とを接続する構造では、例えば、開口部の側面が傾斜面となった場合など、その傾斜面に沿って形成されたパッド電極（例えば、ドレインパッド電極）と隣接する電極（例えば、ゲート電極）との間の距離が隣接する電極間の距離（例えば、ドレイン電極とゲート電極間の距離）より小さくなる場合があり、絶縁破壊が起こりやすくなるという問題があった。かかる問題を解決するためには、開口部の側面の傾斜を小さく、すなわち、傾斜面を垂直に近づける等、対応が容易でなく、ひいては製造コストの上昇を招くことになる。 However, in the structure in which the electrode and the pad electrode are connected via the opening formed immediately above the source electrode, the drain electrode, and the gate electrode, for example, when the side surface of the opening becomes an inclined surface, the inclination The distance between a pad electrode (for example, drain pad electrode) formed along the surface and the adjacent electrode (for example, gate electrode) is the distance between adjacent electrodes (for example, the distance between the drain electrode and gate electrode) In some cases, the dielectric breakdown is likely to occur. In order to solve such a problem, it is not easy to deal with such as making the inclination of the side surface of the opening small, that is, making the inclined surface close to vertical, and this leads to an increase in manufacturing cost.

そこで、本発明は、電極とパッド電極間の絶縁破壊対策が容易な電界効果トランジスタを提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect transistor that can easily take measures against dielectric breakdown between an electrode and a pad electrode.

以上の目的を達成するために、本発明に係る電界効果トランジスタは、
半導体層の上に、
複数のソースフィンガー部を含むソース電極と、
複数のドレインフィンガー部を含み、前記ソースフィンガー部と前記ドレインフィンガー部とが交互に配列されるように設けられたドレイン電極と、
それぞれ前記ソースフィンガー部と前記ドレインフィンガー部の間に設けられた複数のゲートフィンガー部を含むゲート電極と、
前記ソース電極と前記ドレイン電極と前記ゲート電極とを覆う絶縁膜と、
該絶縁膜上に互いに分離して設けられたソースパッド電極とドレインパッド電極とゲートパッド電極と、
を含み、
前記ドレイン電極と前記ドレインパッド電極とを電気的に接続するドレインパッド電極接続部と、前記ゲート電極と前記ゲートパッド電極とを電気的に接続するゲートパッド電極接続部とが、前記ソースフィンガー部と前記ドレインフィンガー部とが前記ソースフィンガー部及び前記ドレインフィンガー部の長手方向と直交する方向に対して所定の間隔をあけて対向する動作領域の外側の接続領域に位置することを特徴とする。 In order to achieve the above object, a field effect transistor according to the present invention provides:
On the semiconductor layer,
A source electrode including a plurality of source finger portions;
A drain electrode including a plurality of drain finger portions, and the source finger portions and the drain finger portions are alternately arranged;
Gate electrodes each including a plurality of gate finger portions provided between the source finger portion and the drain finger portion;
An insulating film covering the source electrode, the drain electrode, and the gate electrode;
A source pad electrode, a drain pad electrode, and a gate pad electrode provided separately from each other on the insulating film;
Including
A drain pad electrode connecting portion that electrically connects the drain electrode and the drain pad electrode, and a gate pad electrode connecting portion that electrically connects the gate electrode and the gate pad electrode, The drain finger portion is located in a connection region outside the operation region facing the direction perpendicular to the longitudinal direction of the source finger portion and the drain finger portion at a predetermined interval.

以上のように構成された本発明に係る電界効果トランジスタは、ドレインパッド電極接続部とゲートパッド電極接続部とを、前記動作領域の外側の接続領域に設けているので、パッド電極と電極間の必要な間隔を容易に確保できる。
したがって、本発明によれば、電極とパッド電極間の絶縁破壊対策が容易な電界効果トランジスタを提供することが可能になる。
ここで、パッド電極と電極間の必要な間隔とは、

（ｉ）ソースパッド電極とドレイン電極間の間隔及びドレインパッド電極とソース電極間の間隔については、動作領域におけるソース電極とドレイン電極間の間隔より大きいことであり、
（ｉｉ）ドレインパッド電極とゲート電極間の間隔及びゲートパッド電極とドレイン電極間の間隔については、動作領域におけるドレイン電極とゲート電極間の間隔より大きくすることである。 In the field effect transistor according to the present invention configured as described above, the drain pad electrode connection portion and the gate pad electrode connection portion are provided in the connection region outside the operation region. Necessary intervals can be easily secured.
Therefore, according to the present invention, it is possible to provide a field effect transistor that can easily take measures against dielectric breakdown between the electrode and the pad electrode.
Here, the necessary distance between the pad electrode and the electrode is

(I) The distance between the source pad electrode and the drain electrode and the distance between the drain pad electrode and the source electrode are larger than the distance between the source electrode and the drain electrode in the operation region;
(Ii) The distance between the drain pad electrode and the gate electrode and the distance between the gate pad electrode and the drain electrode are set larger than the distance between the drain electrode and the gate electrode in the operation region.

本発明に係る実施形態の電界効果トランジスタの電極構成を示す平面図である。It is a top view which shows the electrode structure of the field effect transistor of embodiment which concerns on this invention. 図１のＡ部を拡大して示す平面図である。It is a top view which expands and shows the A section of FIG. 図１のＢ部を拡大して示す平面図である。It is a top view which expands and shows the B section of FIG. 図２のＳ１に沿った縦断面を示す断面図である。It is sectional drawing which shows the longitudinal cross section along S1 of FIG. 図３のＳ２に沿った縦断面を示す断面図である。It is sectional drawing which shows the longitudinal cross section along S2 of FIG. 図３のＳ３に沿った縦断面を示す断面図である。It is sectional drawing which shows the longitudinal cross section along S3 of FIG.

以下、図面を参照しながら本発明に係る実施形態の電界効果トランジスタについて説明する。実施形態の電界効果トランジスタは、本発明に係る電極構造をＧａＮ系ＨＥＭＴに適用した例を示している。ＧａＮ系ＨＥＭＴは、例えば、図４〜図６に示すように、基板６０と、基板６０の上に形成されたアンドープＧａＮ層５２、アンドープＧａＮ層５２の上に形成されたアンドープＡｌＧａＮ層５１とを含む。実施形態の電界効果トランジスタは、アンドープＡｌＧａＮ層の表面に本発明に係る電極構造を形成することにより構成される。尚、ＧａＮ系ＨＥＭＴは、アンドープＧａＮ層とアンドープＡｌＧａＮ層の界面近傍に形成される２次元電子ガス層（チャネル）を利用するものである。
以下、本発明に係る電極構造について詳細に説明する。 Hereinafter, field effect transistors according to embodiments of the present invention will be described with reference to the drawings. The field effect transistor of the embodiment shows an example in which the electrode structure according to the present invention is applied to a GaN-based HEMT. For example, as shown in FIGS. 4 to 6, the GaN-based HEMT includes a substrate 60, an undoped GaN layer 52 formed on the substrate 60, and an undoped AlGaN layer 51 formed on the undoped GaN layer 52. Including. The field effect transistor of the embodiment is configured by forming the electrode structure according to the present invention on the surface of an undoped AlGaN layer. The GaN-based HEMT utilizes a two-dimensional electron gas layer (channel) formed in the vicinity of the interface between the undoped GaN layer and the undoped AlGaN layer.
Hereinafter, the electrode structure according to the present invention will be described in detail.

図１は、本発明に係る実施形態の電界効果トランジスタの電極構成を示す平面図である。図２は、図１のＡ部を拡大して示す平面図であり、図３は、図１のＢ部を拡大して示す平面図である。図２及び図３は、ゲート電極、ソース電極２０及びドレイン電極３０の構成を示すための図であり、ゲート、ソース及びドレインの各パッド電極及び絶縁膜等は省いて描いている。 FIG. 1 is a plan view showing an electrode configuration of a field effect transistor according to an embodiment of the present invention. 2 is an enlarged plan view showing a portion A of FIG. 1, and FIG. 3 is an enlarged plan view showing a portion B of FIG. FIGS. 2 and 3 are diagrams for illustrating the configuration of the gate electrode, the source electrode 20, and the drain electrode 30, and the gate electrode, the source and drain pad electrodes, the insulating film, and the like are omitted.

図１〜図３に示すように、ソース電極２０は、複数のソースフィンガー部２４と、ソースフィンガー部２４の一端がそれぞれ連結されたソース連結部２３とを含み、ソースフィンガー部２４が櫛の歯に相当する櫛形形状を有する。
ドレイン電極３０は、複数のドレインフィンガー部３４と、ドレインフィンガー部３４の一端がそれぞれ連結されたドレイン連結部３３とを含み、ドレインフィンガー部３４が櫛の歯に相当する櫛形形状を有する。 As shown in FIGS. 1 to 3, the source electrode 20 includes a plurality of source finger portions 24 and a source connecting portion 23 to which one ends of the source finger portions 24 are respectively connected, and the source finger portion 24 is a comb tooth. It has a comb shape corresponding to.
The drain electrode 30 includes a plurality of drain finger portions 34 and a drain connection portion 33 to which one ends of the drain finger portions 34 are respectively connected. The drain finger portion 34 has a comb shape corresponding to comb teeth.

本実施形態において、ソース電極２０とドレイン電極３０とは、ソースフィンガー部２４とドレインフィンガー部３４とが交互に配列されるように配置される。ソースフィンガー部２４とドレインフィンガー部３４は、ほぼ同じ長さを有しており、ソースフィンガー部２４の先端とドレイン連結部３３との間の最短距離と、ドレインフィンガー部３４の先端とソース連結部２３との間の最短距離とは、ソースフィンガー部２４とドレインフィンガー部３４間の間隔と同程度に設定される。 In the present embodiment, the source electrode 20 and the drain electrode 30 are arranged so that the source finger portions 24 and the drain finger portions 34 are alternately arranged. The source finger part 24 and the drain finger part 34 have substantially the same length, the shortest distance between the tip of the source finger part 24 and the drain connection part 33, and the tip of the drain finger part 34 and the source connection part. The shortest distance between the source finger portion 24 and the drain finger portion 34 is set to be approximately equal to the distance between the source finger portion 24 and the drain finger portion 34.

ここで、本明細書において、複数のソースフィンガー部２４の先端を通る直線と、ドレインフィンガー部３４の先端を通る直線に挟まれた領域を動作領域３という。また、ソースフィンガー部２４のうちの動作領域３内に位置する部分をソース動作部２１といい、ドレインフィンガー部３４のうちの動作領域３内に位置する部分をドレイン動作部３１という。ソース動作部２１とドレイン動作部３１とは所定の一定の間隔で対向し、交互に配置される。 Here, in this specification, a region sandwiched between a straight line passing through the tips of the plurality of source finger portions 24 and a straight line passing through the tips of the drain finger portions 34 is referred to as an operation region 3. Further, a portion of the source finger portion 24 located in the operation region 3 is referred to as a source operation portion 21, and a portion of the drain finger portion 34 located in the operation region 3 is referred to as a drain operation portion 31. The source operation unit 21 and the drain operation unit 31 face each other at a predetermined constant interval and are alternately arranged.

また、ソースフィンガー部２４のうちのソース動作部２１の一端からそれぞれ延伸され、ソース連結部２３に至る部分をソース延伸部２２といい、ドレインフィンガー部３４のうちのドレイン動作部３１の一端からそれぞれ延伸され、ドレイン連結部３３に至る部分をドレイン延伸部３２という。 In addition, the portion extending from one end of the source operation portion 21 of the source finger portion 24 and reaching the source connection portion 23 is referred to as the source extension portion 22, and from the one end of the drain operation portion 31 of the drain finger portion 34. A portion that is extended and reaches the drain connecting portion 33 is referred to as a drain extending portion 32.

また、ソース電極２０及びドレイン電極３０において、複数のソース延伸部２２とソース連結部２３とからなる部分をソース接続部といい、ドレイン延伸部３２とドレイン連結部３３とからなる部分をドレイン接続部という。 Further, in the source electrode 20 and the drain electrode 30, a portion including the plurality of source extending portions 22 and the source connecting portions 23 is referred to as a source connecting portion, and a portion including the drain extending portions 32 and the drain connecting portions 33 is referred to as a drain connecting portion. That's it.

以上のように構成された実施形態の電界効果トランジスタは、動作領域３の両側に接続領域を有し、その一方の接続領域（第１接続領域１）に、ソース接続部が配置され、他方の接続領域（第２接続領域２）に、ドレイン接続部が配置される。 The field effect transistor of the embodiment configured as described above has connection regions on both sides of the operation region 3, a source connection portion is arranged in one connection region (first connection region 1), and the other A drain connection portion is disposed in the connection region (second connection region 2).

実施形態の電界効果トランジスタにおいて、ソース電極２０は、ソース連結部２３に設けられたソースパッド電極接続部２９を介してソースパッド電極２６に接続される。また、ドレイン電極３０は、ドレイン連結部３３に設けられたドレインパッド電極接続部３９を介してドレインパッド電極３６に接続される。ここで、ソースパッド電極接続部２９は、絶縁膜４２に形成された開口部２８の内周面及び底面に設けられたソースパッド電極２６からなり、開口部２８の底面でソース電極２０に接続されている。また、ドレインパッド電極接続部３９は、絶縁膜４２に形成された開口部３８の内周面及び底面に設けられたドレインパッド電極３６からなり、開口部３８の底面においてドレイン電極３０に接続されている。 In the field effect transistor of the embodiment, the source electrode 20 is connected to the source pad electrode 26 via the source pad electrode connection part 29 provided in the source connection part 23. The drain electrode 30 is connected to the drain pad electrode 36 via the drain pad electrode connecting portion 39 provided in the drain connecting portion 33. Here, the source pad electrode connecting portion 29 is composed of the source pad electrode 26 provided on the inner peripheral surface and the bottom surface of the opening 28 formed in the insulating film 42, and is connected to the source electrode 20 on the bottom surface of the opening 28. ing. The drain pad electrode connecting portion 39 includes a drain pad electrode 36 provided on the inner peripheral surface and the bottom surface of the opening 38 formed in the insulating film 42, and is connected to the drain electrode 30 on the bottom surface of the opening 38. Yes.

ゲート電極１０は、複数のゲートフィンガー部１４と、ゲートフィンガー部１４の一端がそれぞれ連結されるゲート連結部１３とからなり、ゲート連結部１３に設けられたゲートパッド電極接続部１９を介してゲートパッド電極１６に接続される。ここで、ゲートパッド電極接続部１９は、絶縁膜４２に形成された開口部の内周面及び底面に設けられたゲートパッド電極１６からなり、開口部の底面においてゲート電極１０に接続されている。ゲート電極１０についても、ゲートフィンガー部１４のうちの動作領域３内に位置する部分をゲート動作部１１といい、ゲート動作部１１の一端とゲート連結部１３とを繋ぐ部分をゲート延伸部１２という。また、ゲート延伸部１２とゲート連結部１３とからなる部分をゲート接続部といい、ゲート接続部は、第１接続領域１又は第２接続領域、好ましくは図２に示すように第１接続領域１に配置される。すなわち、ソース・ゲート間の電位差はドレイン・ゲート間の電位差よりはるかに小さいので、第１接続領域にゲート接続部を設けることにより、保護膜を介して交差するゲートフィンガー部１４とソース連結部間の短絡の防止が容易となる。
また、ソースパッド接続部は、図２に示すように、ゲートパッド接続部より動作領域に近い位置に配置されることが好ましい。このように配置して、動作領域からソースパッド接続部までの距離を短くすると、ソースパッド接続部から動作領域までのソース配線の配線抵抗を小さくできる。これに対して、ゲート電極及びゲートパッド接続部には、電流がほとんど流れないので、ゲートパッド接続が動作領域から離れて配置されても配線抵抗の影響は少ない。 The gate electrode 10 includes a plurality of gate finger portions 14 and a gate connecting portion 13 to which one end of the gate finger portion 14 is connected, and the gate electrode 10 is gated through a gate pad electrode connecting portion 19 provided in the gate connecting portion 13. Connected to the pad electrode 16. Here, the gate pad electrode connecting portion 19 includes the gate pad electrode 16 provided on the inner peripheral surface and the bottom surface of the opening formed in the insulating film 42, and is connected to the gate electrode 10 on the bottom surface of the opening. . Also for the gate electrode 10, a portion of the gate finger portion 14 located in the operation region 3 is referred to as a gate operation portion 11, and a portion connecting one end of the gate operation portion 11 and the gate connection portion 13 is referred to as a gate extension portion 12. . Further, a portion composed of the gate extending portion 12 and the gate connecting portion 13 is referred to as a gate connecting portion, and the gate connecting portion is the first connecting region 1 or the second connecting region, preferably the first connecting region as shown in FIG. 1 is arranged. That is, since the potential difference between the source and the gate is much smaller than the potential difference between the drain and the gate, by providing the gate connection portion in the first connection region, the gate finger portion 14 and the source connection portion intersecting with each other through the protective film are provided. It becomes easy to prevent short circuit.
Further, as shown in FIG. 2, the source pad connection portion is preferably disposed at a position closer to the operation region than the gate pad connection portion. When the distance from the operation region to the source pad connection portion is shortened in this way, the wiring resistance of the source wiring from the source pad connection portion to the operation region can be reduced. On the other hand, since almost no current flows through the gate electrode and the gate pad connection portion, even if the gate pad connection is arranged away from the operation region, the influence of the wiring resistance is small.

ゲート電極１０において、ゲートフィンガー部１４は１つのソースフィンガー部２４に対して、２つのゲートフィンガー部１４が対応するように設けられている。具体的には、２つのゲートフィンガー部１４が対応するソースフィンガー部２４の両側に沿って延びており、そのソースフィンガー部２４の先端で互いに接続される。 In the gate electrode 10, the gate finger portion 14 is provided so that two gate finger portions 14 correspond to one source finger portion 24. Specifically, the two gate finger portions 14 extend along both sides of the corresponding source finger portions 24 and are connected to each other at the tips of the source finger portions 24.

以上、主として各電極の平面形状について説明したが、本実施形態において、各電極は立体的には以下のように構成されている。 The planar shape of each electrode has been mainly described above, but in the present embodiment, each electrode is configured as follows in a three-dimensional manner.

ソース電極２０は、図５に示すように、半導体層５０に接して設けられたソースコンタクト電極２７とソース電極配線２５とによって構成される。具体的には、ソース動作部２１は、ソースコンタクト電極２７と、ソースコンタクト電極２７上に設けられたソース電極配線２５とによって構成される。ソース接続部は、図２及び図４に示すように、半導体層５０の表面に形成された保護膜４１上に形成されたソース電極配線２５によって構成されている。
ここで、保護膜４１は、図４〜６に示すように、半導体層５０において、ゲート電極１０とソースコンタクト電極２７とドレインコンタクト電極３７とが形成されていない表面に形成されて、半導体層５０の表面を保護している。 As shown in FIG. 5, the source electrode 20 includes a source contact electrode 27 and a source electrode wiring 25 provided in contact with the semiconductor layer 50. Specifically, the source operation unit 21 includes a source contact electrode 27 and a source electrode wiring 25 provided on the source contact electrode 27. As shown in FIGS. 2 and 4, the source connection portion is constituted by the source electrode wiring 25 formed on the protective film 41 formed on the surface of the semiconductor layer 50.
Here, as shown in FIGS. 4 to 6, the protective film 41 is formed on the surface of the semiconductor layer 50 where the gate electrode 10, the source contact electrode 27, and the drain contact electrode 37 are not formed. Protect the surface.

また、ドレイン電極３０は、半導体層５０に接して設けられたドレインコンタクト電極３７とドレイン電極配線３５とによって構成される。具体的には、ドレイン動作部３１は、ドレインコンタクト電極３７と、ドレインコンタクト電極３７上に設けられたドレイン電極配線３５とによって構成される。ドレイン接続部は、半導体層５０の表面に形成された保護膜４１上に形成されたドレイン電極配線３５によって構成されている。 The drain electrode 30 includes a drain contact electrode 37 and a drain electrode wiring 35 provided in contact with the semiconductor layer 50. Specifically, the drain operation unit 31 includes a drain contact electrode 37 and a drain electrode wiring 35 provided on the drain contact electrode 37. The drain connection portion is constituted by a drain electrode wiring 35 formed on the protective film 41 formed on the surface of the semiconductor layer 50.

以上のように構成されたゲート電極１０、ソース電極２０及びドレイン電極３０はそれぞれ、絶縁膜４２の上に形成されたゲートパッド電極１６、ソースパッド電極２６及びドレインパッド電極３６に以下のようにして接続される。 The gate electrode 10, the source electrode 20, and the drain electrode 30 configured as described above are respectively formed on the gate pad electrode 16, the source pad electrode 26, and the drain pad electrode 36 formed on the insulating film 42 as follows. Connected.

ゲート電極１０は、絶縁膜４２に形成された開口部を介してゲートパッド電極１６と接続される。実施形態の電界効果トランジスタにおいて、開口部は、ゲート連結部１３の上に設けられ、ゲート連結部１３とゲートパッド電極１６とが接続される。以上のように、実施形態の電界効果トランジスタでは、開口部がゲート連結部１３の上に設けられ、ゲート連結部１３とゲートパッド電極１６とが接続されるので、ゲートパッド電極１６とソース電極２０間の最も短い距離が、ゲート動作部１１とソース動作部２１間の間隔より狭くなることがない。以上の実施形態では、開口部をゲート連結部１３の上に設けてゲート連結部１３とゲートパッド電極１６とを接続するようにした。しかしながら、本発明において開口部の位置はゲート連結部１３の上に限定されるものではなく、ゲート接続部において、開口部の側面の傾斜を考慮して、ゲートパッド電極１６とソース電極２０間の最短距離が、ゲート動作部１１とソース動作部２１間の間隔より大きくなるような位置に開口部を形成するようにしても良い。また、ゲート接続部において開口部の位置を設定する際、半導体層５０の上面を投影面として半導体層５０に直交する方向から平面視したときに、上記投影面において、ゲートパッド電極接続部１９とソース電極２０間の最短距離が、ゲート動作部１１とソース動作部２１間の間隔より大きくなるような位置に開口部の位置を設定してもよい。 Gate electrode 10 is connected to gate pad electrode 16 through an opening formed in insulating film 42. In the field effect transistor of the embodiment, the opening is provided on the gate coupling portion 13, and the gate coupling portion 13 and the gate pad electrode 16 are connected. As described above, in the field effect transistor according to the embodiment, since the opening is provided on the gate connection portion 13 and the gate connection portion 13 and the gate pad electrode 16 are connected, the gate pad electrode 16 and the source electrode 20 are connected. The shortest distance between the gate operation unit 11 and the source operation unit 21 does not become narrower. In the above embodiment, the opening is provided on the gate connecting portion 13 so as to connect the gate connecting portion 13 and the gate pad electrode 16. However, in the present invention, the position of the opening is not limited to the position on the gate connecting portion 13, and the gate connection portion is arranged between the gate pad electrode 16 and the source electrode 20 in consideration of the inclination of the side surface of the opening. The opening may be formed at a position where the shortest distance is larger than the distance between the gate operation unit 11 and the source operation unit 21. Further, when setting the position of the opening in the gate connection portion, when viewed from above in a direction orthogonal to the semiconductor layer 50 with the upper surface of the semiconductor layer 50 as the projection surface, the gate pad electrode connection portion 19 and The position of the opening may be set such that the shortest distance between the source electrodes 20 is larger than the distance between the gate operation unit 11 and the source operation unit 21.

ソース電極２０は、図４に示すように、絶縁膜４２に形成された開口部２８を介してソースパッド電極２６と接続される。実施形態の電界効果トランジスタにおいて、開口部２８は、図４に示すように、ソース連結部２３の上に設けられ、ソース連結部２３とソースパッド電極２６とが接続される。以上のように、実施形態の電界効果トランジスタでは、開口部２８がソース連結部２３の上に設けられ、ソース連結部２３とソースパッド電極２６とが接続されるので、ソースパッド電極２６とゲート電極１０又はドレイン電極３０間の最短距離が、ソース動作部２１とゲート動作部１１間及びソース動作部２１とドレイン動作部３１の間隔より狭くなることがない。以上の実施形態では、開口部２８をソース連結部２３の上に設けてソース連結部２３とソースパッド電極２６とを接続するようにした。しかしながら、本発明において開口部２８の位置はソース連結部２３の上に限定されるものではなく、ソース接続部において、開口部２８の側面の傾斜を考慮して、ソースパッド電極２６とゲート電極１０間の最短距離及びソースパッド電極２６とドレイン電極３０間の最短距離が、ソース動作部２１とゲート動作部１１間及びソース動作部２１とドレイン動作部３１の間隔より大きくなるような位置に開口部２８を形成するようにすればよい。さらに、開口部２８の側面の傾斜を考慮して、ソースパッド電極２６とゲート電極１０間の最短距離及びソースパッド電極２６とドレイン電極３０間の最短距離が、ソース動作部２１とゲート動作部１１間及びソース動作部２１とドレイン動作部３１の間隔より大きくなるような位置に開口部２８を形成する限り、ソース動作部２１上に設けてもよい。
また、ソース接続部において、開口部２８の位置を設定する際、半導体層５０の上面を投影面として半導体層５０に直交する方向から平面視したときに、上記投影面において、ソースパッド電極接続部２９とゲート電極１０間の最短距離及びソースパッド電極接続部２９とドレイン電極３０間の最短距離が、ソース動作部２１とゲート動作部１１間及びソース動作部２１とドレイン動作部３１の間隔より大きくなるような位置に開口部２８の位置を設定してもよい。 As shown in FIG. 4, the source electrode 20 is connected to the source pad electrode 26 through the opening 28 formed in the insulating film 42. In the field effect transistor of the embodiment, as shown in FIG. 4, the opening 28 is provided on the source coupling portion 23, and the source coupling portion 23 and the source pad electrode 26 are connected to each other. As described above, in the field effect transistor of the embodiment, the opening 28 is provided on the source coupling portion 23 and the source coupling portion 23 and the source pad electrode 26 are connected. 10 or the shortest distance between the drain electrodes 30 does not become narrower than the distance between the source operation unit 21 and the gate operation unit 11 and the distance between the source operation unit 21 and the drain operation unit 31. In the above embodiment, the opening 28 is provided on the source connecting portion 23 to connect the source connecting portion 23 and the source pad electrode 26. However, in the present invention, the position of the opening 28 is not limited to the position on the source connecting portion 23, and the source pad electrode 26 and the gate electrode 10 are taken into consideration in the source connection portion in consideration of the inclination of the side surface of the opening 28. The opening is located at such a position that the shortest distance between them and the shortest distance between the source pad electrode 26 and the drain electrode 30 are larger than the distance between the source operation unit 21 and the gate operation unit 11 and between the source operation unit 21 and the drain operation unit 31. 28 may be formed. Further, in consideration of the inclination of the side surface of the opening 28, the shortest distance between the source pad electrode 26 and the gate electrode 10 and the shortest distance between the source pad electrode 26 and the drain electrode 30 are the source operation unit 21 and the gate operation unit 11. The opening 28 may be provided on the source operation unit 21 as long as the opening 28 is formed at a position larger than the gap between the source operation unit 21 and the drain operation unit 31.
Further, in setting the position of the opening 28 in the source connection portion, the source pad electrode connection portion in the projection plane when viewed from above in a direction orthogonal to the semiconductor layer 50 with the upper surface of the semiconductor layer 50 as the projection plane. 29 and the shortest distance between the gate electrode 10 and the shortest distance between the source pad electrode connection portion 29 and the drain electrode 30 are larger than the distance between the source operation portion 21 and the gate operation portion 11 and between the source operation portion 21 and the drain operation portion 31. The position of the opening 28 may be set at such a position.

ドレイン電極３０は、図５に示すように、絶縁膜４２に形成された開口部３８を介してドレインパッド電極３６と接続される。実施形態の電界効果トランジスタにおいて、開口部３８は、図５に示すように、ドレイン連結部３３の上に設けられ、ドレイン連結部３３とドレインパッド電極３６とが接続される。以上のように、実施形態の電界効果トランジスタでは、開口部３８がドレイン連結部３３の上に設けられ、ドレイン連結部３３とドレインパッド電極３６とが接続されるので、ドレインパッド電極３６とゲート電極１０又はソース電極２０間の最短距離が、ドレイン動作部３１とゲート動作部１１間及びドレイン動作部３１とソース動作部２１の間隔より狭くなることがない。以上の実施形態では、開口部３８をドレイン連結部３３の上に設けてドレイン連結部３３とドレインパッド電極３６とを接続するようにした。しかしながら、本発明において開口部３８の位置はドレイン連結部３３の上に限定されるものではなく、ドレイン接続部において、開口部３８の側面の傾斜を考慮して、ドレインパッド電極３６とゲート電極１０間の最短距離及びドレインパッド電極３６とソース電極２０間の最短距離がそれぞれ、ドレイン動作部３１とゲート動作部１１間及びドレイン動作部３１とソース動作部２１の間隔より大きくなるような位置に開口部３８を形成するようにすればよい。
また、ドレイン接続部において、開口部３８の位置を設定する際、半導体層５０の上面を投影面として半導体層５０に直交する方向から平面視したときに、上記投影面において、ドレインパッド電極接続部３９とゲート電極１０間の最短距離及びドレインパッド電極接続部３９とソース電極２０間の最短距離がそれぞれ、ドレイン動作部３１とゲート動作部１１間及びドレイン動作部３１とソース動作部２１の間隔より大きくなるような位置に開口部３８の位置を設定するようにしてもよい。 As shown in FIG. 5, the drain electrode 30 is connected to the drain pad electrode 36 through an opening 38 formed in the insulating film 42. In the field effect transistor of the embodiment, as shown in FIG. 5, the opening 38 is provided on the drain coupling portion 33, and the drain coupling portion 33 and the drain pad electrode 36 are connected to each other. As described above, in the field effect transistor of the embodiment, the opening 38 is provided on the drain coupling portion 33 and the drain coupling portion 33 and the drain pad electrode 36 are connected. 10 or the shortest distance between the source electrodes 20 does not become narrower than the distance between the drain operation unit 31 and the gate operation unit 11 and the interval between the drain operation unit 31 and the source operation unit 21. In the above embodiment, the opening 38 is provided on the drain coupling portion 33 so as to connect the drain coupling portion 33 and the drain pad electrode 36. However, in the present invention, the position of the opening 38 is not limited to the position on the drain coupling portion 33, and the drain pad electrode 36 and the gate electrode 10 are taken into consideration in the drain connection portion in consideration of the inclination of the side surface of the opening 38. Openings are made at positions where the shortest distance between them and the shortest distance between the drain pad electrode 36 and the source electrode 20 are larger than the distance between the drain operation unit 31 and the gate operation unit 11 and between the drain operation unit 31 and the source operation unit 21. The portion 38 may be formed.
Further, when setting the position of the opening 38 in the drain connection portion, when the upper surface of the semiconductor layer 50 is used as a projection surface and viewed from the direction orthogonal to the semiconductor layer 50, the drain pad electrode connection portion is formed on the projection surface. 39 and the shortest distance between the drain pad electrode connecting portion 39 and the source electrode 20 are determined by the distance between the drain operating portion 31 and the gate operating portion 11 and the distance between the drain operating portion 31 and the source operating portion 21, respectively. You may make it set the position of the opening part 38 to the position which becomes large.

以上のように構成された実施形態の電界効果トランジスタでは、ソースパッド電極接続部とドレインパッド電極接続部とゲートパッド電極接続部とを、動作領域３の外側の第１及び第２の接続領域１，２に設けているので、パッド電極と電極間の必要な間隔を容易に確保できる。
したがって、実施形態の電界効果トランジスタによれば、電極とパッド電極間の絶縁破壊対策が容易な電界効果トランジスタを提供することが可能になる。
ここで、パッド電極と電極間の必要な間隔とは、
（ｉ）ソースパッド電極２６とドレイン電極３０間の間隔及びドレインパッド電極３６とソース電極２０間の間隔については、動作領域３におけるソース電極２０とドレイン電極３０間の間隔より大きいことであり、
（ｉｉ）ドレインパッド電極３６とゲート電極２０間の間隔及びゲートパッド電極１６とドレイン電極３０間の間隔については、動作領域３におけるドレイン電極３０とゲート電極１０間の間隔より大きくことである。 In the field effect transistor of the embodiment configured as described above, the source pad electrode connection portion, the drain pad electrode connection portion, and the gate pad electrode connection portion are connected to the first and second connection regions 1 outside the operation region 3. , 2, the necessary spacing between the pad electrode and the electrode can be easily secured.
Therefore, according to the field effect transistor of the embodiment, it is possible to provide a field effect transistor that can easily take measures against dielectric breakdown between the electrode and the pad electrode.
Here, the necessary distance between the pad electrode and the electrode is
(I) The distance between the source pad electrode 26 and the drain electrode 30 and the distance between the drain pad electrode 36 and the source electrode 20 are larger than the distance between the source electrode 20 and the drain electrode 30 in the operation region 3;
(Ii) The distance between the drain pad electrode 36 and the gate electrode 20 and the distance between the gate pad electrode 16 and the drain electrode 30 are larger than the distance between the drain electrode 30 and the gate electrode 10 in the operation region 3.

以上のように構成された実施形態の電界効果トランジスタでは、ソース電極１０は、動作領域３において半導体層に接して形成されたソースコンタクト電極２７とソースコンタクト電極２７の上に形成されたソース電極配線２５を含んでいるので、ソース電極１０の抵抗を低くできる。
また、ドレイン電極３０は、動作領域３において半導体層に接して形成されたドレインコンタクト電極３７とドレインコンタクト電極３７の上に形成されたドレイン電極配線３５を含んでいるので、ドレイン電極３０の抵抗を低くできる。 In the field effect transistor of the embodiment configured as described above, the source electrode 10 includes the source contact electrode 27 formed in contact with the semiconductor layer in the operation region 3 and the source electrode wiring formed on the source contact electrode 27. 25, the resistance of the source electrode 10 can be lowered.
Further, since the drain electrode 30 includes a drain contact electrode 37 formed in contact with the semiconductor layer in the operation region 3 and a drain electrode wiring 35 formed on the drain contact electrode 37, the resistance of the drain electrode 30 is reduced. Can be lowered.

以上のように構成された実施形態の電界効果トランジスタでは、ソースコンタクト電極２７及びドレインコンタクト電極３７が形成された表面を除いて半導体層の表面を覆う保護膜４１を有し、ソース電極配線２５とドレイン電極配線３５をそれぞれソースコンタクト電極２７上及びドレインコンタクト電極３７上から保護膜４１上に連続して形成され、保護膜４１上に形成されたソース電極配線２５とドレイン電極配線３５とによってそれぞれ第１及び第２の接続領域１，２のソース電極２０とドレイン電極３０とが構成されている。
以上のような構成にすることにより、ソースコンタクト電極２７及びドレインコンタクト電極３７として半導体層と良好なオーミック接触が得られる材料を選択し、ソース電極配線２５とドレイン電極配線３５として抵抗の小さい材料を選択することができる。
このように、オーミック用の電極と配線用の電極を分けることで、それぞれの機能に応じて適した材料を選択することが可能になり、良好なオーミック特性と低い抵抗の配線を両立できる。尚、本実施形態では、オーミック用の電極と配線用の電極を分けたが、本発明はこれに限定されるものではなく、ソース電極配線２５とドレイン電極配線３５をそれぞれソースコンタクト電極２７上及びドレインコンタクト電極３７と一体化して一種類の材料で構成するようにしてもよい。 The field effect transistor of the embodiment configured as described above has a protective film 41 that covers the surface of the semiconductor layer except the surface on which the source contact electrode 27 and the drain contact electrode 37 are formed. The drain electrode wiring 35 is continuously formed on the source contact electrode 27 and the drain contact electrode 37 on the protective film 41, and the drain electrode wiring 35 is formed by the source electrode wiring 25 and the drain electrode wiring 35 formed on the protective film 41, respectively. The source electrode 20 and the drain electrode 30 in the first and second connection regions 1 and 2 are configured.
With the above-described configuration, a material that can provide good ohmic contact with the semiconductor layer is selected as the source contact electrode 27 and the drain contact electrode 37, and a material with low resistance is used as the source electrode wiring 25 and the drain electrode wiring 35. You can choose.
In this manner, by separating the ohmic electrode and the wiring electrode, it is possible to select a material suitable for each function, and both good ohmic characteristics and low resistance wiring can be achieved. In this embodiment, the ohmic electrode and the wiring electrode are separated. However, the present invention is not limited to this, and the source electrode wiring 25 and the drain electrode wiring 35 are respectively formed on the source contact electrode 27 and The drain contact electrode 37 may be integrated with a single material.

以上のように構成された実施形態の電界効果トランジスタでは、ソースフィンガー部２４は、第１接続領域１に位置するソース延伸部２２を含み、該ソース延伸部２２の一端がソース連結部２３に接続され、
ドレインフィンガー部３４は、第２接続領域２に位置するドレイン延伸部３２を含み、該ドレイン延伸部３２の一端がドレイン連結部３３に接続され、
ゲートフィンガー部１４は、第１接続領域１に位置するゲート延伸部１２を含み、該ゲート延伸部１２の一端がゲート連結部１３に接続されている。
以上の構成により、パッド電極と電極間の必要な間隔をより容易に確保できる。 In the field effect transistor according to the embodiment configured as described above, the source finger portion 24 includes the source extension portion 22 located in the first connection region 1, and one end of the source extension portion 22 is connected to the source connection portion 23. And
The drain finger part 34 includes a drain extension part 32 located in the second connection region 2, and one end of the drain extension part 32 is connected to the drain connection part 33.
The gate finger portion 14 includes a gate extension portion 12 located in the first connection region 1, and one end of the gate extension portion 12 is connected to the gate connection portion 13.
With the above configuration, a necessary interval between the pad electrode and the electrode can be more easily ensured.

以上の実施形態の電界効果トランジスタにおいては、ソースパッド電極接続部２９をソース連結部２３上のソースフィンガー部２４が連結された部分の近傍にそれぞれ分割して設け、ドレインパッド電極接続部３９をドレイン連結部３３上のドレインフィンガー部３４が連結された部分の近傍にそれぞれ分割して設け、さらにゲートパッド電極接続部１９をゲート連結部１３上のゲートフィンガー部１４が連結された部分の近傍にそれぞれ分割して設けた。これにより、各パッド電極接続部とフィンガー部の先端の距離を大きくできるので、電極間の上記必要な間隔をより容易に確保できる。 In the field effect transistor of the above embodiment, the source pad electrode connection portion 29 is divided and provided in the vicinity of the portion where the source finger portion 24 on the source connection portion 23 is connected, and the drain pad electrode connection portion 39 is provided as the drain. The drain finger part 34 on the connecting part 33 is divided and provided in the vicinity of the connected part, and the gate pad electrode connecting part 19 is provided in the vicinity of the part on the gate connecting part 13 to which the gate finger part 14 is connected. Divided and provided. Thereby, since the distance of each pad electrode connection part and the front-end | tip of a finger part can be enlarged, the said required space | interval between electrodes can be ensured more easily.

以上の実施形態の電界効果トランジスタでは、ソースフィンガー部２４とドレインフィンガー部３４とを全体にわたって規則的に交互に配列し、ソースフィンガー部２４とドレインフィンガー部３４の各間にそれぞれゲートフィンガー部１４を配置した。
しかしながら、本発明はこれに限定されるものではなく、必ずしも素子全体にわたって規則的に電極が配置されている必要はない。
すなわち、電極配置の一部において、ソースフィンガー部２４とソースフィンガー部２４、ドレインフィンガー部３４とドレインフィンガー部３４及びゲートフィンガー部１４とゲートフィンガー部１４とが他のフィンガー部を挟むことなく隣接していてもよいし、ソースフィンガー部２４とソースフィンガー部２４の間又はドレインフィンガー部３４とドレインフィンガー部３４の間にゲートフィンガー部１４が設けられた電極配置となる部分が一部に含まれていてもよい。 In the field effect transistor of the above embodiment, the source finger portions 24 and the drain finger portions 34 are regularly and alternately arranged throughout, and the gate finger portions 14 are respectively provided between the source finger portions 24 and the drain finger portions 34. Arranged.
However, the present invention is not limited to this, and the electrodes need not be regularly arranged over the entire element.
That is, in a part of the electrode arrangement, the source finger portion 24 and the source finger portion 24, the drain finger portion 34 and the drain finger portion 34, and the gate finger portion 14 and the gate finger portion 14 are adjacent to each other without sandwiching other finger portions. Or part of the electrode arrangement in which the gate finger portion 14 is provided between the source finger portion 24 and the source finger portion 24 or between the drain finger portion 34 and the drain finger portion 34 is included in part. May be.

以上の実施形態の電界効果トランジスタにおいては、ソースパッド電極接続部２９をソース連結部２３上のソースフィンガー部２４が連結された部分の近傍にそれぞれ分割して設けた。しかしながら、本発明はこれに限定されるものではなく、例えば、複数に分割することなくソース連結部２３の上にライン状に一体化したソースパッド電極接続部を形成するようにしてもよい。
また、同様に、ドレインパッド電極接続部３９及びゲートパッド電極接続部１９についても、ドレイン連結部２３上及びゲート連結部１３上においてそれぞれ、複数に分割することなくライン状に一体化したドレインパッド電極接続部及びゲートパッド電極接続部を形成するようにしてもよい。このようにすると、図２等に示したパッド電極接続部をそれぞれ分割して形成する実施形態として示した構成に比較すると必要な最短距離を確保するために小型化は制限されるが、パッド電極接続部における接続抵抗を低くできるという利点がある。 In the field effect transistor of the above embodiment, the source pad electrode connection portion 29 is divided and provided in the vicinity of the portion where the source finger portion 24 on the source connection portion 23 is connected. However, the present invention is not limited to this. For example, the source pad electrode connecting portion integrated in a line shape may be formed on the source connecting portion 23 without being divided into a plurality of portions.
Similarly, the drain pad electrode connection part 39 and the gate pad electrode connection part 19 are also integrated on the drain connection part 23 and the gate connection part 13 in a line shape without being divided into a plurality of lines. You may make it form a connection part and a gate pad electrode connection part. In this way, the pad electrode connection portion shown in FIG. 2 or the like is divided and formed, but the size reduction is limited in order to secure the necessary shortest distance as compared with the configuration shown as the embodiment. There is an advantage that the connection resistance in the connection portion can be lowered.

以上の実施形態の電界効果トランジスタにおいては、ソースパッド電極接続部２９、ドレインパッド電極接続部３９及びゲートパッド電極接続部１９をそれぞれソース連結部２３上、ドレイン連結部３３上及びゲート連結部１３上に形成するようにしたが、本発明はこれに限定されるものではなく、パッド電極接続部がそれぞれ連結部から各延伸部に延在して形成されていてもよい。 In the field effect transistor of the above embodiment, the source pad electrode connection part 29, the drain pad electrode connection part 39, and the gate pad electrode connection part 19 are placed on the source connection part 23, the drain connection part 33, and the gate connection part 13, respectively. However, the present invention is not limited to this, and the pad electrode connecting portion may be formed by extending from the connecting portion to each extending portion.

１第１接続領域
２第２接続領域
３動作領域
１０ゲート電極
１１ゲート動作部
１２ゲート延伸部
１３ゲート連結部
１４ゲートフィンガー部
１６ゲートパッド電極
１８開口部
１９ゲートパッド電極接続部
２０ソース電極
２１ソース動作部
２２ソース延伸部
２３ソース連結部
２４ソースフィンガー部
２５ソース電極配線
２６ソースパッド電極
２７ソースコンタクト電極
２８開口部
２９ソースパッド電極接続部
３０ドレイン電極
３１ドレイン動作部
３２ドレイン延伸部
３３ドレイン連結部
３４ドレインフィンガー部
３５ドレイン電極配線
３６ドレインパッド電極
３７ドレインコンタクト電極
３８開口部
３９ドレインパッド電極接続部
４１保護膜
４２絶縁膜 DESCRIPTION OF SYMBOLS 1 1st connection area | region 2 2nd connection area | region 3 Operation | movement area | region 10 Gate electrode 11 Gate operation | movement part 12 Gate extending | stretching part 13 Gate connection part 14 Gate finger part 16 Gate pad electrode 18 Opening part 19 Gate pad electrode connection part 20 Source electrode 21 Source Operation part 22 Source extension part 23 Source connection part 24 Source finger part 25 Source electrode wiring 26 Source pad electrode 27 Source contact electrode 28 Opening 29 Source pad electrode connection part 30 Drain electrode 31 Drain operation part 32 Drain extension part 33 Drain connection part 34 Drain finger part 35 Drain electrode wiring 36 Drain pad electrode 37 Drain contact electrode 38 Opening 39 Drain pad electrode connection part 41 Protective film 42 Insulating film

Claims

On the semiconductor layer,
A source electrode including a plurality of source finger portions;
A drain electrode including a plurality of drain finger portions, and the source finger portions and the drain finger portions are alternately arranged;
Gate electrodes each including a plurality of gate finger portions provided between the source finger portion and the drain finger portion;
An insulating film covering the source electrode, the drain electrode, and the gate electrode;
A source pad electrode, a drain pad electrode, and a gate pad electrode provided separately from each other on the insulating film;
Including
A drain pad electrode connecting portion that electrically connects the drain electrode and the drain pad electrode, and a gate pad electrode connecting portion that electrically connects the gate electrode and the gate pad electrode, Located in the connection region outside the operation region facing the drain finger part with a predetermined interval,
The drain pad electrode connection portion is composed of a part of the drain pad electrode provided on the inner peripheral surface and the bottom surface of the opening formed in the insulating film, and is connected to the drain electrode at the bottom surface,
The inner peripheral surface is inclined so as to expand as the distance from the surface of the drain electrode increases.
The field effect transistor, wherein the shortest distance among the distances connecting the drain pad electrode and the gate electrode provided on the inner peripheral surface is larger than the distance between the drain finger portion and the gate finger portion in the operation region.

The source finger part includes a source extension part extending from the operation area to the connection area, and the source electrode further includes a source connection part that connects ends of the plurality of source extension parts,
The drain finger part includes a drain extension part extending from the operation area to the connection area, and the drain electrode further includes a drain connection part that connects ends of the plurality of drain extension parts,
The gate finger part includes a gate extension part extending from the operation area to the connection area, and the gate electrode further includes a gate connection part that connects ends of the plurality of gate extension parts,
The source pad electrode connection part, the drain pad electrode connection part, and the gate pad electrode connection part that electrically connect the source electrode and the source pad electrode are respectively the source connection part, the drain connection part, and the gate connection. The field effect transistor according to claim 1, which is provided in the portion.

On the semiconductor layer,
A source electrode including a plurality of source finger portions;
A drain electrode including a plurality of drain finger portions, and the source finger portions and the drain finger portions are alternately arranged;
Gate electrodes each including a plurality of gate finger portions provided between the source finger portion and the drain finger portion;
An insulating film covering the source electrode, the drain electrode, and the gate electrode;
A source pad electrode, a drain pad electrode, and a gate pad electrode provided separately from each other on the insulating film;
Including
And each of the drain electrodes and a plurality of drain pad electrode connection portion for electrically connecting the drain pad electrode, and a plurality of gate pad electrode connection portion for electrically connecting to each said gate electrode and said gate pad electrode The source finger portion and the drain finger portion are located in a connection region outside the operation region facing each other with a predetermined interval,
The drain pad electrode connection portion is composed of a part of the drain pad electrode provided on the inner peripheral surface and the bottom surface of the opening formed in the insulating film, and is connected to the drain electrode at the bottom surface,
When the upper surface of the semiconductor layer is used as a projection plane and the plane is viewed from a direction orthogonal to the semiconductor layer, the minimum distance between the drain pad electrode connection portion and the gate electrode on the projection plane is the drain in the operation region. rather greater than the distance between the finger portions and the gate finger unit,
The source finger part includes a source extension part extending from the operation area to the connection area, and the source electrode further includes a source connection part that connects ends of the plurality of source extension parts,
The drain finger part includes a drain extension part extending from the operation area to the connection area, and the drain electrode further includes a drain connection part that connects ends of the plurality of drain extension parts,
The gate finger part includes a gate extension part extending from the operation area to the connection area, and the gate electrode further includes a gate connection part that connects ends of the plurality of gate extension parts,
A plurality of source pad electrode connection portions, the drain pad electrode connection portions, and the gate pad electrode connection portions that electrically connect the source electrode and the source pad electrode, respectively, are the source connection portion, the drain connection portion, and Provided in the gate connecting portion;

The plurality of source pad electrode connection portions are respectively provided in the vicinity of the end of the source extension portion on the source connection portion,
The plurality of drain pad electrode connection portions are respectively provided in the vicinity of the terminal end of the drain extension portion on the drain connection portion,
The plurality of gate pad electrode connection portions are provided in the vicinity of a terminal end of the gate extension portion on the gate connection portion, respectively .

The source electrode includes a source contact electrode formed in contact with the semiconductor layer in the operation region and a source electrode wiring formed on the source contact electrode,
The drain electrode, the any one of claims 1 to 3 comprising a drain electrode wiring formed on the semiconductor layer in contact with the formed drain contact electrode and the drain contact electrode in said operating region The field effect transistor as described.

A protective film is provided to cover the surface of the semiconductor layer except for the surface on which the source contact electrode and the drain contact electrode are formed, and the source electrode wiring and the drain electrode wiring are respectively on the source contact electrode and the drain contact. A source electrode and a drain electrode of the connection region are formed by the source electrode wiring and the drain electrode wiring formed on the protective film continuously from the electrode, respectively. The field effect transistor according to claim 4 .