JPS63156364A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase power capacity without decreasing a cut-off frequency, by forming a plurality of gate electrodes, whose gate width does not exceed a limit value, over which linearity is impaired, and connecting the gates in parallel with gate wirings. CONSTITUTION:Schottky gate electrodes 4, whose gate width does not exceed a limit value, over which linearity is impaired, are formed in parallel on a semi-insulating substrate comprising GaAs through a buffer layer 2 and an operation layer 3. A gate wiring 10 is led out of one end part of each of a plurality of Schottky gate electrodes 4 and connected to a common gate wiring 10', which is formed in the direction of the gate length. A source wiring 11 is led out of one end part of each source electrode 7 and connected to a common source wiring 11'. A drain wiring 12 is led out of one end part of each drain electrode 8 and connected to a common. drain wiring 12.. Since a plurality of unit GaAs MESFETs are connected in parallel, the power capacity can be increased without decreasing a cut-off frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device with a low gate, and more specifically, to a semiconductor device with an increased power capacity without lowering the cut-off frequency.

<Prior art and problems to be solved by the invention> Current semiconductor devices represented by JC and LSI have become mainstream, with junction type, MOS type, etc. FETs as main elements. .

The above FET was developed with the focus on the ability to apply a predetermined potential voltage to the gate to create a depletion layer between the source and drain, and to control the current depending on how this depletion layer spreads. It has advantages such as low power consumption and easy control, and because of these advantages, it is used in semiconductor devices such as the above-mentioned IC and LSI.

In order to increase the power capacity of these FETs,
It is necessary to increase the drain saturation current by increasing the gate width. Furthermore, in order to increase the cutoff frequency, it is necessary to shorten the gate length.

In order to obtain high gain at high cut-off frequencies, research has been actively conducted on shortening the gate length to reduce the carrier migration distance between the source and drain. are being manufactured.

On the other hand, if the power capacity is increased by increasing the gate width, there are no disadvantages as in the case of shortening the gate length.

However, there are limits to increasing the gate width due to current resist technology. That is, the outline of the gate forming process is as follows: formation of polycrystalline silicon on a semiconductor substrate -> coating of resist - formation of resist pattern - ion implantation - formation of gate electrode. In the above case, due to the problem of adhesion between the resist and the semiconductor substrate, the resist peels off and an accurate resist pattern cannot be formed. Therefore, if the gate width is increased, it is difficult to form a gate with good linearity, and if the distance between the source and drain is increased in anticipation of gate distortion, the cutoff frequency will decrease, making it difficult to form a gate with good linearity. There is a problem that the desired performance cannot be achieved.

Specifically, in the current gate formation technology, when the gate length is formed to approximately 1 μm in order to increase the cutoff frequency, the gate width that can be formed in a straight line is approximately 50 μm.
My taste was the limit.

<Objective of the Invention> The present invention has been made in view of the above-mentioned interlayer point, and an object thereof is to provide a semiconductor device that can increase the power capacity without lowering the cut-off frequency.

Means for Solving the Problems> In order to achieve the above object, a semiconductor device of the present invention includes a plurality of gates having a gate width that does not exceed a limit value that impairs linearity, and at least one source and drain are formed corresponding to the
A gate wiring connecting the plurality of gates, a source wiring and a drain wiring connecting the sources and the drains in parallel in the gate width direction are formed.

In the above semiconductor device, a plurality of gates are formed with a gate width that does not exceed a limit value that impairs linearity, and at least one source and drain are formed facing each other in correspondence with the plurality of gates. By connecting multiple gates, sources, and drains in parallel in the gate width direction using gate wiring, source wiring, and each drain wiring, it is possible to maintain a gate width that does not exceed a limit value that impairs linearity, that is, a cutoff frequency. Since the gate width is set within a range that does not reduce the cut-off frequency, the FE can increase the overall power capacity without reducing the cut-off frequency by connecting multiple gates in parallel.
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<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 shows a G a A s as an embodiment of the present invention.
FIG. 2 is a plan view showing an M E S F E T, and FIG. 2 is an enlarged vertical cross-sectional view of FIG. Schottky gate electrodes (4) with a gate width that does not exceed a limit value that impairs linearity are formed in parallel, and high concentration impurity regions formed by ion implantation using the Schottky gate electrodes (4) as a mask are alternately formed. source area (5)
, a drain region (6), and a source electrode [7), on the source region IS and the drain region (6), respectively.
and a drain electrode (8).

A gate wiring line is drawn out from one end of the plurality of Schottky gate electrodes (4) and connected to a common gate wiring (10') formed in the gate length direction. A source wiring (11') and a drain wiring (12') are formed in parallel with the gate wiring (9), and the source wiring (11) is drawn out from one end of the source electrode (71) to form a common source wiring (11). '), and a drain wiring (12) is drawn out from one end of the drain electrode (8) and connected to a common drain wiring (12').

To explain the structure of the semiconductor device in more detail together with the manufacturing process, a semi-insulating substrate (1) made of GaAs
AQ is implanted into the surface of the active layer (3) by selective ion implantation to form a layer that can serve as a buffer layer (2) below the active layer (3).

Next, ions that can become impurities (for example, Si'') are implanted by selective ion implantation to form a layer that can become the active layer (3).
Electrode materials with Schottky contacts (e.g. WSi
) is formed to a thickness of about 5,000 by a conventionally known method. Then, a resist is applied to the electrode material, and a resist pattern is formed by irradiating ultraviolet rays using a mask to form several stages of Schottky gate electrodes (4) with a gate width that does not exceed a limit value that impairs linearity. Reactive ion etching (RIE) using the above resist pattern as a mask
Schottky gate electrode (4) is created by processing the electrode material using the method
form.

Thereafter, ion implantation is performed using the Schottky gate electrode 4) as a mask to form a layer (source region (9) and drain region (6)) that can become a high concentration impurity region, and then, for example, a SiN film is formed as a protective film. (not shown) is formed to a thickness of approximately 1200 nm by plasma CVD method, and annealed in N! gas at 800°C for 2 minutes to activate the implanted impurity ions and activate the active layer (
3], a high concentration impurity region (5) (6) is formed, and the region into which +V is implanted is crystallized to form a buffer layer.

Thereafter, the SiN is removed, the source electrode region and the drain electrode region are patterned by normal photolithography, and a metal material having ohmic contact with GaAs (for example, Au/Ge) is deposited by a conventionally known method, and lift-off is performed. Remove metal material from unnecessary areas by method. Then, the remaining metal material is alloyed by sintering at 400°C for about 5 minutes, and the source electrode (
7), and the drain electrode (8) is formed to form the unit C, a.
A s M E S F E T]9) is obtained.

Regarding the Schottky gate electrode (4) with a gate width that does not exceed the limit value that impairs linearity, to explain in more detail, in order to increase the power capacity, it is desirable to form the gate width as large as possible, and the cutoff frequency In order to increase the gate length, it is desirable to make the gate length as short as possible. That is, the width should not exceed the range in which the Schottky gate electrode (4) can be formed in a straight line using the current gate forming technology.

Schottky gate electrode (8) formed in parallel with a gate width that does not exceed a limit value that impairs linearity, and a source electrode (
'7), by connecting the drain electrodes (8) in parallel, a plurality of units G a A S M E S F E
Since T (9) are connected in parallel, the power capacity can be increased without lowering the cut-off frequency. Further, even at very high frequencies, each unit gate operates uniformly, so there is almost no phase difference between the output signals from each drain, so power amplification at a high cut-off frequency is possible.

FIG. 3 is a plan view showing a GaAs MESFET as another embodiment of the semiconductor device of the present invention, in which buffer layers and Schottky gate electrode (4) with a gate width that does not exceed a limit that impairs linearity through the active layer (3)
are formed in a row at predetermined intervals, and Schottky gate electrodes (
4) is formed as a source region (5) and a drain region (6) in the center, a source electrode ('7] and a drain electrode (8) are respectively formed on the above layers, and a plurality of units are formed. M E S F E T (9) are formed at predetermined intervals in the width direction. Gate wiring (g) connecting each Schottky gate electrode (14) is formed, and a plurality of source electrodes (7) are formed. ), one source wiring connects (
11), one drain wiring (12) is formed to connect the drain electrodes (8) in several stages.

Therefore, the unit GaAs MESFET (9
) are connected in parallel.

Schottky gate electrodes (4) having a gate width that does not exceed the limit value that impairs the linearity, that is, a gate width that does not lower the cutoff frequency, are formed in a row at predetermined intervals, and a plurality of Schottky gate electrodes (41) are connected to the gate wiring n. By connecting the unit GaAsMES FET (9)
By connecting them in parallel, the power capacity can be increased without lowering the cutoff frequency of the entire GaAsFET.

It should be noted that this invention is not limited to the above-described embodiments; for example, the gate electrode (4) can be made of a metal gate, and various design changes can be made without changing the gist of the invention. make it possible.

<Effects of the Invention> As described above, according to the semiconductor device of the present invention, a plurality of gate electrodes having a gate width that does not exceed a limit value that impairs linearity can be formed, and the gates can be connected in parallel with each other by gate wiring. This has the unique effect of increasing the power capacity without lowering the cut-off frequency.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment of the semiconductor device of the present invention. FIG. 2 is an enlarged vertical sectional view. FIG. 3 is a plan view showing another embodiment. (4)...Schottky gate electrode, (sword...source electrode, (8)...drain electrode, (foundation)...
・Gate wiring, (11)... Source wiring, (1
2)...Drain wiring. Patent applicant: Sumitomo Electric Industries, Ltd. Agent: Hirokatsu Kamei 1. ′,...1・Remains (and 3 others> −---−1“

Claims (1)

[Claims] 1. In a semiconductor device in which a gate is formed between a source and a drain that are formed facing each other, a plurality of gates are formed with a gate width that does not exceed a limit value that impairs linearity, and , at least one source and drain are formed corresponding to the plurality of gates,
A semiconductor device characterized in that a gate wiring, a source wiring, and a drain wiring are formed to connect the plurality of gates, sources, and drains in parallel in the gate width direction. 2. A plurality of gates with a gate width that does not exceed a limit value that impairs linearity are formed between a source and a drain that are formed in parallel with each other, and one end of the plurality of gates is The above claims are connected to a common gate wiring, one end of the source is connected to the common source wiring, and one end of the drain is connected to the common drain wiring. The semiconductor device according to item 1.