TW449844B - Ball grid array package having an integrated circuit chip - Google Patents

Ball grid array package having an integrated circuit chip Download PDF

Info

Publication number
TW449844B
TW449844B TW087103626A TW87103626A TW449844B TW 449844 B TW449844 B TW 449844B TW 087103626 A TW087103626 A TW 087103626A TW 87103626 A TW87103626 A TW 87103626A TW 449844 B TW449844 B TW 449844B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
heat sink
package
grid array
tracking layer
Prior art date
Application number
TW087103626A
Other languages
English (en)
Inventor
Tae-Sung Jeong
Ki-Tae Ryu
Tae-Keun Lee
Keun-Hyoung Choi
Han-Shin Youn
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019970019144A external-priority patent/KR100220249B1/ko
Priority claimed from KR1019970019145A external-priority patent/KR19980083734A/ko
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW449844B publication Critical patent/TW449844B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/20753Diameter ranges larger or equal to 30 microns less than 40 microns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Description

丨 9 844 6 五、發明説明( A7 B7 經濟部中央標準局I工消費合作社印製 <發明之範圍> =明係有關於一種具有例如積體電路晶片等電子元 ,尤其制有_ —種球形網袼陣列找者。該 匕裴具有輕減重量與減小製造成本的優點。 <發明之背景> 在早期,積體電路晶片係以金屬或究器包裝。以 =器形成半導體包裝時具有優異的熱特性。然而亦有例 σ冋製造成本與其製造技術須耗費時間等的缺點。 為了解決這種缺點,已有許多包裝方式被推荐,其中 最醒目者為一種㈣模造包裝。尤其是一種塑膠模造球形 ,同格陣列包裝可排除傳統表面安裝微細間距塑勝包裝所遇 技術上的困難者。塑膠模造球形網格陣列包裝又可免除將 包裝引伸至積體電路包裝外部邊緣的需要1膠模造球形 網格陣列X可料較小的包裝及絲㈣—印刷電路板上 的極為接近間_包裝。總而言之,球形網格陣列包裝提 供了較短的互連長度之結果改進了其電氣雜。如上揭優 點,連同球形齡陣列包裝的低廉成本,使球形網格陣列 包裝成為一理想的包裝方式而可應用於許多積體電路包裝 上。 第1圖表示一傳統的球形網格陣列包裝的剖面。該圖中 所示之球形網格陣列包裝包含一連接於積體電路圖型的互 連基板1及以可黏性預成劑3附著於基板1的積體電路晶片 2,且具有複數的接合襯墊2a於上部表面上。基板〗的電路 圖型與積體電路晶片2上的接合襯墊2a亦互相連接。同時為 本纸伕尺度適用中國國家標準(CNS ) A4洗格(210Χ297公釐) (诗先K讀背^之注意事項再填寫本丈) ----—------- 、1r 線— A7 B7 449844 五、發明説明(> ) 了從外界環境保護積體電路晶片2的表面,基板丨的導線接 合部份與積體電路晶片2乃以環氧樹脂5封裝。在基板1的下 部表面係附著於複數的軟焊球6以便與形成於一^板(未標 示)上的電源端子做電氣上的連接。 第1圊所示的球形網格陣列包裝降低積體電路晶片的 可靠性’尤有甚者其散熱魏較錢招來積料路晶片的 破壞。為了發散這種積體電路晶片所產生㈣於包 部,即有-耗電更多的問題。同時包裝的整體厚度勢必非 常的厚。 最近為了改善球形網格陣列包裝的散熱特性’開發了 一種具有散熱板的超級球形網格陣列包裝,以該散熱板來 驅散所產生的熱。 第2圖即表示具有散熱板的超級球形網格陣列包裝的 剖面圖。參照該圖,該互連基板包含:由銅製成之三導電 性追蹤層18 ’及夾於導電性追蹤層1δ之三絕緣層lr^尤= 特別的係’互連基板包含全部六層,其最底科電性追縱 層18係安置更底於最底層絕緣層17 ^因此’該絕緣層u 係安置於互連基板最上層。最上層絕緣層17_著於散熱 板11。另外,複數的通孔19係形成於互連基板,通孔19: 各内壁係以導電性金屬電氣連接導電性追蹤層18而加以鍍 膜。一絕緣焊接罩15係形成於最底層追蹤層18,除了球形 區,整個區域係曝露在外。其中,該最上層追蹤層18作為 接地及中間之追蹤層18作為傳輸信號。 這些中間及最上層追縱層18係曝露於井區16,接著各 本纸張尺度適J?i巾關家網L ( eNS )从胁(21QX 297公瘦) ----------裝-----.丨訂--—---線 (铐先K讀背面之注意項再填寫本A ) 經濟部中央榉率局貝工消費合作杜-Sr製 經濟部中央棣率局員工消費合作衽印製 \Ί 9 844 ---〜— —*— ---*—1 ~^ —------------ 五、發明説明($) 別曝露追蹤層18以接合用積體電路晶片10電氣上連接於金 屬導線。整體井區16區域係以封囡材料14封固。同時,一 軟焊球20欲安裝於主機板上,係附著於曝露於絕緣浑接罩 15之最底層追蹤層18,即係於球形區。 其實’與第1圖比較’第2圖所示之超級砵形網格陣列 包裝具有極佳之散熱特性。然而,由於第2圖之包裝有六層 互連基板及一散熱板附著,因此亦有其缺點。因此,然而 由於第2圊的超級球形網格陣列包裝重量大,因而產生一問 題’即是超級球形網格陣列包裝無法應用於筆記本型,袖 珍型電腦或格狀電話等要求輕量的裝置。又由於有昂貴的
兩層或更多銅層的遮覆,因此產生成本高昂而包裝的厚度 太厚的缺點。 X <發明之總論> 為了%決上揭問題,本發明的目的之一乃在提供一種 積體電路元件的包裝,其具有優異的散熱能力,重量輕, 尽度小及製造成本低廉等優點。 以達到本發明所述之目的,球形網格陣列包裝具有以 下組成份: 〜一中央具有井區之互連基板,絕緣層兩側形成第一及 ^二導電性㈣層…與互連基板相同大小之散熱板具有 井區,其係附著於第二導電性追蹤層。具有一接合襯墊 ^積體電路晶片係置於互連基板與散熱板之井 區内,接著 了接σ襯墊係以金屬導線電氣接合於第—導電性追縱層。 同時,一作為接地之接合襯墊係以另一金屬導線電氣連接 本紐从· 297 公沒 _ -----------裝------訂------線 _ (請先閱讀背釭之注意r項再填寫本久) 經濟部中央榇準局員工消費合作社印製 4 9 844 B7 五、發明説明(l|_ ) 附著於第二導電性追蹤層。因此,第二導電性追蹤層係作 為接地,而第一導電性追蹤層係作'為傳輸信號。 整體導線接合部份與丼區係以封固材料封固。其中, 較佳地,積體電路晶片與散熱板處於同一平面上。第一導 電性追蹤層係部份曝露於絕緣焊接罩,及軟焊球係曝露附 著於部份第一導電性追蹤層。 另一方面,第二散熱板較佳的係附著於位於同一平面 上之散熱板版面及積體電路晶片。此外,亦較佳地形成一 於第二散熱板中央曝露積體電路晶片之開口。 第二散熱板亦可與第一散熱板相同,即係,散熱板係 置於積體電路晶片之邊緣。然而,第二散熱板小於第一散 熱板。因此,於第一散熱板邊緣上形成一空間,較佳地此 空間係以周邊絕緣層填充,以防止濕氣滲入第二散熱板。 此情況,省略第一散熱板。 <附圖之簡單說明> 第1圖為傳統球形網格陣列包裝之剖面圖; 第2圖為具有散熱板傳統的超級球形網格陣列包裝之 剖面圖; 第3圖為本發明球形網格陣列包裝第一實施例之剖面 圖; 第4圖為本發明形成於包裝之井區平面圖; 第5圖為一透視圖,表示每一實施例之包裝在製造時使 用一塊狀加熱器; 第6圖為本發明之球形網格陣列包裝第二實施例之剖 本纸張尺度適用中國國家標準(CNS ) Α4現#( 2 ί 〇 X 297公釐) (諸先K讀背氣之注意Ϋ·項再填®) -裝. 訂 4 49844 A 7 B" 五 :¾濟部中央標準局員工消費合作社印製 '發明説明 面圖; 第7圖為本發明之球形網格陣‘列包裝第三實施例之到 面圖; 第8圖為本發明之球形網格陣列包裝第四實施例之剖 面圖; 弟9圖為一曲線圖,係就本發明之第一至第三貫施例中 對各別包裝之散熱特性評估所做模擬試驗的結果; 第10圖為一曲線圖,表示第9圖所示之熱抵抗值轉換成 粍功值之關係; 第11A至11C圊表示本發明之包裝第一實施例中接合用 導線特性的曲線圖; 第12A至12C圖表示本發明之包裝第一實施例中封裝特 性的曲線圖; 第13A至13C圖表示本發明之包裝第一實施例_接合用 導線特性的曲線圖; 弟14A至14C圖表示本發明之包裝第一實施例令封裝.特 性的曲線圖;及 第15A至15C圖表示本發明之包裝在第一實施例中球的 裝著特·性的曲線圖。 <圖式中元件名稱與符號對照> 】:勒反 14 :封固材料 19 :通孔 17,32 :絕緣層 5 :環祕脂 16,36 :井區 18’31a’31b:導電性追職 1卜35 :散熱板 本紙張尺度逋用中國國家揉隼(CNS ) M現格(210X297公釐) 61 :塊狀加熱器 70 ’ 80 :第二散熱板 74 :開口 100,200,300,400 :包裝 449844 A7 _____ B7 - 五、發明説明(^) ’ 20 » 34 - 39 :金屬導線 37 :圓形耳部 42 :封固材料 12 ’ 38 :黏合劑(材料) 2 ’ 10 ’40 :積體電路晶片 35a ’ 40a ’ 50a ’ 7〇a,80a :第一表面 2a ’ 41 :接合襯墊 50 :互連基板 62 :真空孔 72 :黏合劑 90 :周邊絕緣層 <較佳具體實施例之詳細描述> 實施例1 如第3圖所示之一種球形網格陣列包裝1〇〇,根據第i 實施例’其包含:一積體電路晶片40,一互連基板50及一 散熱板35。尤其特別係,井區36係於兩個具有相同大小之 互連基板50與散熱板35中央形成及垂直穿透。井區%較積 體電路晶片40大。該互連基板50與散熱板35係利用黏合劑 38附著,積體電路晶片40係以附著組合置於井區3 6正中央 位置。接合襯墊41係置於積體電路晶片4〇底部。 為了方便說明,如第3圖所示’積體電路晶片4〇之底 面’互連基板50及散熱板35視為第一表面,各上層因此視 為第二表面。一參考標誌“a”係指第一表面,而二參考標 誌“b”係指第二表面。因此,互連基板5〇之第二♦面5〇匕 及散熱板35之第一表面35a係附著一起,以及接合概塾心 本紙伕尺度適用中國國家標準(CNS丨A扣見格(210X297公釐) 裝 . 訂 線 .(讀先聞婧背4之注意f項苒填寫孝λ) - 經濟部中夬標準局貝工消費合作社印製 經濟部中央梯準局更工消費合作社印-*'1冬 4 4984 4 at ____ ___ B7 五、發明説明(7 ) 係置於積體電路b曰片40之第一表面4〇a。尤其係,積體電路 晶片40之第一表面40b係置於與散熱板π之第二表面35b相 同平面上。比較先前技藝第2圖’得知先前技藝與本散熱板 有不同之處。傳統散熱板丨丨係直接置於積體電路晶片4〇 上,而本發明之散熱板35係置於積體電路晶片4〇側邊’因 此,可縮小整體包裝厚度。同時,可選擇銅、鋁或銀作為 散熱板35。 互連基板50於%緣層32之兩側上組成第一及第二導電 性追蹤層31a,31b。其中,形成於底部位置之第一導電性追 蹤層31a作為傳輸信號及形成於上層位置之第二導電性追 蹤層31b則作為接地》其係沒有必要於第一及第導 縱層31a,3關電氣接合。 由於第一導電性追蹤層31a係直向底部配置,第二導電 性追蹤層31 b係利用黏合劑38附著於散熱板扔之第—表面 35a。第一導電性追蹤層31以系以金屬導線電氣接合至接合 親墊41。第-導電性追縱層31a係部份曝露於一絕緣焊接^ 33三導線接合料與耗36似材㈣湘。因此除 了第一表面4Gb與金屬導線39,其利用封时料將整體積體 電路晶片4G封固。-軟焊球34係、於部份曝露之第—導電性 追蹤層31a形成。 同時井區36於互連基板5〇形成,如第4圖所示,散 熱板35具有-正方形剖面,同時亦錢形、菱形及星形。 此外’井H 36角落為圓形、菱形或星形邊緣。 一種具有以上所述組成物之包裝1〇〇的組裝方法如 本紙铁尺度通用*f困囷象橾準(CNS ) A4規格(2!〇><297公釐 (請先^讀背1之注意*-.項再填寫为乂) 裝. 線 A7 B7 9844 五、發明説明(含) 下。如第5圖所示,互連基板50及散熱板35係安裝於一塊狀 加熱器61上’其中井區36各自形成;。此時,散熱板35之第 二表面35b面向塊狀加熱器61其中一表面。 參照第5圖,塊狀加熱器61形成一真空之真空孔62。真 空孔62透過互連基板50之各井區36與井區36而曝露於外 部。此情況下,積體電路晶片40係置於井區36内,以便積 體電路晶片40之第二表面40b面向塊狀加熱器61表面,由此 阻擋著真空孔62。積體電路晶片40透過真空孔62以真空壓 力將塊狀加熱器61穩固固定於塊狀加熱器6〗上。因此,以 上所述之包裝過程完成後,積體電路晶片40之各別第二表 面40b,35b及散熱板35則係位於同一平面上。 藉由這些包裝條件,根據導線接合步驟,積體電路晶 片41之接合襯墊41及第一導電性追蹤層31a係用金屬導線 39來電氣上連接。接著,整體井區36及導線接合部份則以 封固材料42封固。最後’軟焊球34係於第一導電性追蹤層 31a之一部份形成,其係曝露於絕緣焊接罩33。 根據本發明之第1實施例組裝此包裝與第2圖之傳統包 裝比較,有以下優點。 首先’本發明之包裝的散熱板35置於積體電路晶片40 之一側,而第2圖所示之先前技藝包裝,其散熱板11係安置 於積體電路晶片10之上方。包裝之厚度及重量有顯著的降 低。同時,本發明之包裝顯示包裝散熱特性的模擬評估試 驗結果為在氣流2m/sec時的熱阻為15.8°C/W。結果顯示, 並沒有太大差別。即是,本發明之包裝提供類似先前技藝 π .ml tru 1 - ^^3 HI . I —^ϋ ^—ί I- » I 1. - 一OJ· I - 111 HI . ...... (請先閏讀?面之注意.^項再填寫岑7<) 經濟部中央標準局負工消背合作社印裝 本纸乐尺度適用中國國家樣準(CMS ) 格(210X297公釐) 449844 五、發明説明(7 ) 包裝散熱特性的包裝’不過其具有厚度及重量有顯著降低 之優點。 (請先65讀背氐之注意•事項再填寫才菩;) 實施例2 第6圖為本發明之球形網格陣列包裝第2實施例之剖面 圖。第2實施例包裝200之組成物與第1實施例相同,另外不 同之處,將於以下說明。為了改善散熱特性,提供一第二 散熱板70於包裝200<^類似第1實施例所述之其他組成物, 第一散熱板70亦具有一第一表面70a及一第二表面7〇b。第 二散熱板70之第一表面70a置於其底部,其係附著於所述之 第一散熱板35之第二表面35b,40b及積體電路晶片4〇。第 二散熱板70與第一散熱板35為相同大小,其不具有第一散 熱板35之井區36。 根據第2實施例之包裝200,其較第1實施例之包裝100 有更佳地散熱特性。根據模擬試驗結果,包裝2〇〇顯示於空 氣流速為2m/sec時的熱阻為6. 3°C/W,優於第1實施例之包 裝 100。 經濟部中央標準局負工消費合作社印裝 由於如第6圖所示之包裝2〇〇的第二散熱板7〇係於釗固 材料42形成後才附著,其可用較第2圖先前技藝包裝更薄之 材料。因此,包裝200提供較薄之第二散熱板7〇,其重量為 第2圖所示之先前技藝包裝重量的65%。 實施例3 第7圖為本發明之球形網格陣列包裝第3實施例之剖面 圖。第2及第3實施例之差別在於,積體電路晶片4〇沒有藉 由黏合劑附著於第二散熱板70,此外,於第二散熱板7〇中 本纸張尺度適用中國國家標準(CNS ) A4洗格(210X297公釐) 經濟部中央標進.局貝工消費合作社印製 9 844 五、發明説明(ί17) 央形成開口 7 4。 其係由製造過程而造成之差別‘。第2實施例之包裝200 的第二散熱板70係於封固材料42形成後形成,以及第二散 熱板7 0係附著於積體電路晶片4 0上。而第3實施例之散熱板 70係於封固材料未形成前附著於積體電路晶片40上。因 此,根據第3實施例之包裝300,第一散熱板35係利用黏合 劑72附著於第二散熱板70,且積體電路晶片40並沒有附 著,而只是放置於第二散熱板70之第一表面70a上。 此情況下,如第5圖所示,整體合成體係置於塊狀加熱 器61上,接著,透過真空孔62而將真空壓力施於整體合成 體。此時,由於真空壓力必須施於積體電路晶片40上,以 便積體電路晶片40能於第二散熱板70上穩固固定。開口74 將積體電路晶片40之第二表面40b曝露形成於第二散熱板 70。 根據模擬試驗結杲,相似於第1實施例之包裝100,包 裝300顯示於空氣流速2m/sec時的熱阻為7. 8°C/W。因而證 明包裝30ΰ較第1實施例之包裝100,具有更佳之散熱特性。 同時,第7圖所示之包裝300之重量,為第2圖包裝200重量 之 85%。 實施例4 第8圖為本發明之球形網格陣列包裝之第4實施例的剖 面圖。第2與第4實施例之差別在於第4實施例之包裝400不 具有第一散熱板,以及第4實施例之第二散熱板80小於第2 實施例之第二散熱板70。 13 本纸張尺度適用中國國家標準(CNTS ) A4規格(2!〇x 297公釐〉 —--------^1----,—ΐτ--t —--^ (势.户€讀背£-~之注意事項再填£,卢,1) 經濟初I中央標準局員工消費合作社印製 A; E" 五、發明説明(I I ) 即是,第二散熱板80之第一表面8〇a係以黏合劑72直接 附著於互連基板5〇與積體電路晶,片4〇之第二表面5〇b, 40b。同時’由於第二散熱板8〇小於第2實施例之包裝2〇〇 的第一散熱板70,因而互連基板50之第二表面5〇b兩端具有 空間。該空間係由周邊絕緣層9〇填充。該周邊絕緣層作 為防止濕氣滲入第二散熱板8〇及黏合劑72。 第9圖表示就本發明之第一至第三施例中之包裝對其 散熱特性之評估所做模擬試驗結果的曲線圖。在第g圖中縱 座標為以°C/W表示的熱阻,而橫座標表示氣流速度⑴/北^。 在第9圖中’曲線A為本發明第一實施例中包裝的試驗結 果’曲線B為本發明第二實施例争包裝的試驗結果,曲線c 為本發明第三實施例中包裝的試驗結果,及曲線D為本發明 第四實施例中包裝的試驗結果。 如第9圖所示’第一實施例的包裝表示優異的熱阻15 8 °C/W於氣流速度2m/sec下,雖然它並無附著於積體電路晶 體後側的散熱板,但只這樣本發明第一實施例的包裝熱.阻 就能充分發散積體電路晶片所產生的熱。又第二實施例的 包裝表現最優異的熱阻,即大約6. 3°C/W於氣流速度2m/sec 下。又第三實施例的包裝表現的熱阻約為7. 8。〇 / w於氣流速 度2m/sec下。最後,第四實施例的包裝表現的熱阻為約6. 5 °C/W於氣流速度2m/sec下。 第10圖所示者為第9圖的熱阻值轉換為功率散失值的 曲線圖。在第9圖中,縱座標表示功率散失值,以w表示, 而横座標表示氣流速度,單位為m/sec。在第1〇圖中曲線e 本紙伕尺度適用中國國家標準(CNS ) A4規格(2!0Χ297公釐) ----------裝------、玎------M (請先閎讀背氣之注意事項再填寫方,^.} 鯉濟部中夫標準局員工消費合作杜印裝 4 今 844 at _________ 五、發明説明(/Λ ) ' 表不本發明第一實施例中包裝的功率散失特性,曲線F表示 士發明第二實施例中包裝的該特性,曲線6表示本發明第三 只k例中包裝的該特性,而曲線^1表示本發明第四實施例中 包裝的該特性。由第10圖可知,本發明的包裝表現優異的 功率散失特性3. 2W或更多於氣流速度2[η/ sec 下。 第11A至11C圖表示本發明之包裝在第一實施例中接合 =導,特性的曲線圖。於此第11A圖表示接合性拉力試驗結 果。第11B圖表示球的剪斷試驗結果。第uc圖表示環路高 度測定結果。在實施這些試驗之前,為了要在第5圖所示塊 狀加熱器上施行導線接合步驟,韓國K&s公司製造之K&s 1488 1'11]:13〇接合用導線,韓國旧1^6〇叩%,製造的1.3[^15 厚金線,及以商品名Micro Swiss 6 mil Tip販賣的毛管線 乃被使用。對於第一條線與第二條線,導線接合溫度各為 18.0 C,時間各為25msec,所用功率對於第一條線為6〇· ’ 對於第二條線為12_,及所用力量對於第一條線為45g,對 於第二條線為ll〇g〇 第11A圖的曲線I指示在接合性拉力試驗,所有21樣品 值均高於參考值的5g (如曲線J中所示)。因此,可見所完 成之導線接合強度甚大。第11B圖的曲線^指示’在球的剪 斷試驗,所有21樣品值均高於應大於3〇g的參考值。由第ye 圖的曲線N可知,所有22條導線樣品均通過應小於1 丄s 的參考值的標準。 如上揭描述’從第11A至11C所示結果,可以確定將積 體電路晶片以真空力附著於第5圖的塊狀加熱器的狀態下 15 本紙疚尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -----------丨^------1T------^ (請先闔讀背&.之注意事項再填寫方1) 449844 經濟部中央標準局負工消费合作社印裝 五、發明説明(/3 ) 施行導線接合作業可保證獲得成功的導線接合結果而不致 於對包裝的導線接合特性有任何壞影響。 第12A至12C圖表示本發明之包裝第一實施例中封裝特 性的曲線圖。第12A圖表示封裝高度的測定結果。第12B圖 表示導線旋刮的測定結果。第12C圖為空隙的測定結果□在 施行這些試驗之前,為了封裝已接合好導線的包裝,在第5 圖的塊狀加熱器上使用一種調配系統,亦即以商品名 CAMAL05000市售者,及一種堰止/填充材料,亦即以商品 名Hysol 4451/4450市售者曾被使用。封裝溫度為3〇它,而 封裝壓力為1.4bar。如從第12A圖之曲線〇可知,22個樣品 通過了應小於16mils (如曲線P所示)之參考值,如第 圖之曲線Q可知’ 22樣品在導線旋到的測定令均通過應小於 5. 0 %的參考值(如曲線R指示者)。從第12C圖之曲線§可 知’在封裝空隙比試驗中22樣品均通過封裝空隙比應為5 〇 %以下的參考值(如曲線Τ指示者)。 從以上的封裝特性測定結果,可球定將積體電路曰.片 以真空壓力附著於第5圖的塊狀加熱器的狀態下施行封f 作業時可成功的完成封裝而不致於對封裝特性有彳壬彳^ 影響。 .& 第13A至13C圖表示本發明之包裝在第二實施例中接合 用導線特性的曲線圖。第13A圖表示接合拉力試驗的結果。 第13B圖表示球的剪斷試驗結果。第13C圖表示環路高度試 驗結果。 在施行這些性能試驗之前,為了在第5圖所示之塊狀加 16 本紙伎尺度適用中國國家標準(CNS ) A4規格< 2丨公釐) (諳先閏讀背面之注意事項再填寫本異) 裝 訂 線 經濟部中央標準局員工消費合作社印製 4498心 :: 五、發明説明(j ) 熱器上實施導線接合作業,使用了韓國K&s公司出品之K&s 1488 Turbo接合用導線,韓國Mikyeong Sa出品之1. 3mi Is 直徑之金線,及以商品名STP市售之毛管線。第—導線的接 合溫度為220 C,時間為25msec,而對第二導線的接合溫度 仍為22 C,時間則為30msec ,功率對第一與第二導線均各 為60mw,所用之力對第一導線為45g,對第二導線為55g。 如第13A圖之曲線u指示,在接合拉力試驗中21樣品均 具有高於參考值應高於5g以上(如曲線V所示)之值。因此, 可確疋獲得了咼強度導線接合特性。如第13B圖之曲線w所 示,在球的剪斷試驗中,所有21樣品均通過了應大於3〇g 之參考值(如曲線X所示)。如第13C圖之曲線γ所示,22 導線樣品均通過了應小於10mns之參考值(如曲線冗所 示)°從以上的結果,可以確定將積體電路晶片以真空壓 力附著於第5圖的塊狀加熱器的狀態下施行導線接合作業 可保證有成功的導線接合結果。 第14A至14C圖表示本發明之包裝在第二實施例中封裝 特性的曲線圖。第14八圖表示封裝高度的測定結果,第丄仙 圖表示導線旋刮的測定結果,而第14C圖表示封裝空陳的測 定結果。 ' 在施行這些性能試驗以前,為了封裝已經做好導線接 合的包裝,使用一種以商品名CAMAL05000市售的調配系統 及以商品名Hysol 4451/4450市售的堰止/填充材料。封事 溫度為80°C,而封裝壓力為1. 5bar。如第14A圖中曲線W的 指示’ 22樣品均通過了封裝高度應在I6mils以下的參考值 17 本紙弦尺度適用中國國家標芈(CNS ) A4規格(210X297公釐) -------和衣------------—線 ·' (锜先聞讀背面之注意事項再填寫本) A7 449844 五、發明説明(/ί ) (如曲線B1所示)。如第14β圖中曲線^指示,22樣品均通 過了導線旋刮試驗值的應在5· 〇%以下的參考值(如曲線⑴ 所示)。如第14C圖中曲線^的指示,22樣品在封裝空隙比 試驗中其封裝空隙比均通過了應在5, 〇%以下的參考值(如 曲線F1所示)。從以上第丨4八至14(:所示之封裝特性,可以 確定將積體電路晶片以真空壓力附著於第5圖的塊狀加熱 器的狀態下施行封裝作業時可成功的完成封裝而不致於對 封裝特性有任何不良影響。
第15Α至15C圖為表示本發明之包裝在第二實施例中球 的裝著特性的曲線圖,其中第15Α圖表示包裝翹起度的測定 結果’第15Β圖表示軟焊球剪斷試驗測定結果,及第15C圖 表示平坦性的測定結果。在施行這些試驗以前,為了安裝 複數的軟焊球於已封固的包裝内,使用了 一種以sHIBUYA SBM-230的商品名市售的裝球器,一種以商品名CHRONICS SMD-522N市售的火爐,一種以商品名ACCEL MICROCEL 2市 售的焊劑清除器,及一種以商品名SENJU 635Sn/37Pb市售 的軟焊球。於此,在作業過程中火爐最高溫度保持225τ/ 5t: ’而洗滌時焊劑清除時間為i20sec,沖洗時間亦為 120sec而乾燥時間為i60sec。第15A圖中如曲線G1所示,12 樣品全部通過包裝纽曲試驗參考值的5· Omi 1 s (如曲線hi 之指示)。再者,第15B圖中如曲線J1所示,22軟焊球樣品 通過了小於剪斷力試驗參考值的lkg (如曲線K1之指示)。 第15C圖中如曲線L1與L2所示,48樣品用於二個平坦面試 驗’ 24樣品用於一個平坦面試驗,全部通過應小於6mils 18 本紙伕尺度適用中國國家榡準(CNS ) A4g ( 2丨OX2?7公釐} ---------裝------訂------線 /·· (請先閏讀背^之注意事碩再填寫名夷〕 經"部中央標準局負工消費合作社印製 4 4 9 844 五、發明説明(丨b ) -- 之平坦試驗參考值(如曲線Ml所示)。從第l5A至15C圖所 不,可以確定在本發明的第二實施例中軟焊球已成功 裝於包裝内。 關於本發明第三與第四實施例的包裝,其導線接合特 性的試驗,封裝特性與軟焊球安裝特性並未施行。然而雖 然=些試驗並未施行,但是本發明各發明人預期第三與第 四實施例的包裝將與本發明的第二實施例一樣,其導線接 合特性’封裝特性與軟焊球安裝特性均有同樣的結果,此 乃由於第三與第四實施例中的包裝較之本發明第二實施例 中的包裝具有結構上的相同性,各實施例中的包裝均有一 附著於積體電路晶片第二表面上的散熱板。 如上揭描述,本發明的球形網格陣列包裝具有積體電 路晶片像露於包裝之外部或具有淺針或箔片附著於曝露的 積體電路晶片的表面。因此本發明的包裝具有優異的散熱 特性’輕量’厚度薄及製造成本低廉的優點。 經":部中央標準局員工消費合作社印製 本發明的數項詳細實施例與其製造方法業已提供如 上。本發明係依據這些特定的實施例與製造方法加以描 述’上揭描述乃僅屬於關於本發明的說明而並非用來對本 發明做任何限制者。熟習於此方面技術人士或可對本發明 做各種變更或修飾,但如未能脫離本發明之精神範疇時, 概應認為被涵蓋於本發明之申請專利範圍内,特此聲明。 ___ 19 本紙用中SS 家標準(〔NS ) ( 21GX297公釐)

Claims (1)

  1. AS 4 49 84 4 cb 六、申請專利範圍 1. 一種球形網格陣列包裝,包括: 一互連基板之第一導電性追蹤層'與第二導電性追蹤層係 形成於絕緣層兩側,部份第一導電性追蹤層係曝露於一 絕緣焊接罩及一井區係形成於互連基板中央; 一散熱板具有互面對之第一及第二表面,其中,第一表 面係附著於互連基板之第二導電性追蹤層,一具有與互 連基板相同大小之井區,形成於散熱板中央; 一積體電路晶片具有互對立之第一及第二表面,以及其 係置於散熱板與互連基板之各別井區,其t,接合襯墊 係置於第一表面上,而第二表面係置於與散熱板之第二 表面於相同平面; 複數的金屬導線用以電氣上連接積體電路晶片之各別接 合襯墊、第一導電性追蹤層或第二導電性追蹤層; 一封固材料作為封固整體金屬導線,用以填補各別井 區,及 一軟焊球安裝於曝露於絕緣焊接罩之第一導電性追蹤 層。 經濟部中央標华局員工消費合作社印製 (請先-「讀^£之注^事項再填穷"頁) 2. 如申請專利範圍第1項所述之球形網格陣列包裝,其中, 第二散熱板係附著於積體電路晶片與散熱板之各別第二 表面。 3. 如申請專利範圍第1項所述之球形網格陣列包裝,其中, 第二散熱板係附著於散熱板之第二表面,及用作提供真 空壓力至積體電路晶片之第二表面的開口,其係形成第 二散熱板之中央。 20 本紙張尺度適用中國国家標準(CNS ) A4^格(210X297公釐) /1 4 9 844 | DS ^、申請專到園 4. 如申請專利範圍第1項至第3.項所述之球形網格陣列包 裝,其中,散熱板係由選自一群包含銅'鉋及銀金屬所 製成。 5. 如申請專利範圍第1項或第3項所述之球形網格陣列包 裝,其中’該導電性追蹤層係由銅金屬製成。 6. —種球形網格陣列包裝,其包含: 一互連基板之第一導電性追蹤層與第二導電性追縱層係 形成於絕緣層兩側,部份第一導電性追蹤層係曝露於一 絕緣焊接罩’及一井區係形成於互連基板中央; 一積體電路晶片具有互對立之第一及第二表面,以及其 係置於散熱板與互連基板之各別井區,其中,接合觀墊 係置於第一表面上; 小於互連基板之一散熱板係附著於積體電路晶片之第二 表面及互連基板上; 一封固材料作為封固整體金屬導線,用以填補各別丼 區; 經濟部中央標準局貝工消費合作社印策 複數的金屬導線用以電氣上連接積體電路晶片之各別接 合襯墊、第一導電性追蹤層或第二導電性追蹤層; 一周邊絕緣層係形成於積體電路晶片之第二表面兩端的 空間,其中,避免散熱板與互連基板之接點區域有濕氣 滲入現象;及 一軟焊球安裝於曝露於絕緣焊接罩之第〜導電性追縱 層。 7. 如肀請專利範圍第6項所述之球形網格陣列包裝,其令, 21 本纸铁尺度適用中國园家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印製 449844 会! CS __PS.___ 六、申請專利範園 散熱板係由選自一群包含銅、I呂及銀金屬所製成。 8.如申請專利範圍第6項所述之球形網格陣列包裝,其中 該導電性追蹤層係由銅金屬製成。 2 2 ΤΗ±·衣 i .*τ. (辞先:s-ttt,面之注,意事項'再^窝本頁} 線 本纸伕尺度速用中國闺家標準(CNS ) A4現格(2丨0X297公釐)
TW087103626A 1997-05-17 1998-03-12 Ball grid array package having an integrated circuit chip TW449844B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970019144A KR100220249B1 (ko) 1997-05-17 1997-05-17 열방출 능력이 향상된 박막 볼 그리드 어레이 패키지
KR1019970019145A KR19980083734A (ko) 1997-05-17 1997-05-17 열방출 능력이 향상된 박막 볼 그리드 어레이 패키지

Publications (1)

Publication Number Publication Date
TW449844B true TW449844B (en) 2001-08-11

Family

ID=26632739

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087103626A TW449844B (en) 1997-05-17 1998-03-12 Ball grid array package having an integrated circuit chip

Country Status (6)

Country Link
US (1) US6060778A (zh)
JP (1) JP3407184B2 (zh)
CN (1) CN100365804C (zh)
DE (1) DE19821715B4 (zh)
GB (2) GB2325340B (zh)
TW (1) TW449844B (zh)

Families Citing this family (142)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150730A (ja) * 1998-11-17 2000-05-30 Fujitsu Ltd 半導体装置及びその製造方法
US6433360B1 (en) * 1999-01-15 2002-08-13 Xilinx, Inc. Structure and method of testing failed or returned die to determine failure location and type
US6982478B2 (en) * 1999-03-26 2006-01-03 Oki Electric Industry Co., Ltd. Semiconductor device and method of fabricating the same
JP3575001B2 (ja) 1999-05-07 2004-10-06 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6384471B1 (en) * 1999-05-10 2002-05-07 Bull S.A. Pbga package with integrated ball grid
JP3416737B2 (ja) * 1999-05-20 2003-06-16 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージの製造方法
JP3398721B2 (ja) * 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6365967B1 (en) * 1999-05-25 2002-04-02 Micron Technology, Inc. Interconnect structure
US6196002B1 (en) * 1999-06-24 2001-03-06 Advanced Micro Devices, Inc. Ball grid array package having thermoelectric cooler
JP3427352B2 (ja) 1999-08-24 2003-07-14 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ用回路基板
JP2001077301A (ja) 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
US6534861B1 (en) * 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6399415B1 (en) 2000-03-20 2002-06-04 National Semiconductor Corporation Electrical isolation in panels of leadless IC packages
US6372539B1 (en) 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
US6686652B1 (en) 2000-03-20 2004-02-03 National Semiconductor Locking lead tips and die attach pad for a leadless package apparatus and method
US6576494B1 (en) 2000-06-28 2003-06-10 Micron Technology, Inc. Recessed encapsulated microelectronic devices and methods for formation
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
DE10042839B4 (de) * 2000-08-30 2009-01-29 Infineon Technologies Ag Elektronisches Bauteil mit Wärmesenke und Verfahren zu seiner Herstellung
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
TW466723B (en) * 2000-12-01 2001-12-01 Siliconware Precision Industries Co Ltd Super thin package having high heat-dissipation property
US6564454B1 (en) 2000-12-28 2003-05-20 Amkor Technology, Inc. Method of making and stacking a semiconductor package
US6486537B1 (en) * 2001-03-19 2002-11-26 Amkor Technology, Inc. Semiconductor package with warpage resistant substrate
AU2007203504B2 (en) * 2001-03-21 2010-05-27 United Test Center Inc Semi Conductor Device and Method for Fabricating The Same
TW579581B (en) * 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
KR100411811B1 (ko) * 2001-04-02 2003-12-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
US6475327B2 (en) * 2001-04-05 2002-11-05 Phoenix Precision Technology Corporation Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier
US7334326B1 (en) 2001-06-19 2008-02-26 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded passive components
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6967124B1 (en) 2001-06-19 2005-11-22 Amkor Technology, Inc. Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate
SG111919A1 (en) * 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
US6651869B2 (en) * 2001-09-21 2003-11-25 Intel Corporation Methods and electronic board products utilizing endothermic material for filling vias to absorb heat during wave soldering
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
SG102640A1 (en) * 2001-10-11 2004-03-26 Ultratera Corp Semiconductor device and method for fabricating the same
US6762489B2 (en) 2001-11-20 2004-07-13 International Business Machines Corporation Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules
US6784534B1 (en) 2002-02-06 2004-08-31 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
US6982485B1 (en) 2002-02-13 2006-01-03 Amkor Technology, Inc. Stacking structure for semiconductor chips and a semiconductor package using it
US6576998B1 (en) 2002-02-28 2003-06-10 Amkor Technology, Inc. Thin semiconductor package with semiconductor chip and electronic discrete device
US6683795B1 (en) 2002-04-10 2004-01-27 Amkor Technology, Inc. Shield cap and semiconductor package including shield cap
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US6930257B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laminated laser-embedded circuit layers
US7399661B2 (en) * 2002-05-01 2008-07-15 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded back-side access conductors and vias
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US20080043447A1 (en) * 2002-05-01 2008-02-21 Amkor Technology, Inc. Semiconductor package having laser-embedded terminals
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2003347741A (ja) 2002-05-30 2003-12-05 Taiyo Yuden Co Ltd 複合多層基板およびそれを用いたモジュール
KR100475079B1 (ko) * 2002-06-12 2005-03-10 삼성전자주식회사 고전압용 bga 패키지와 그에 사용되는 히트 스프레더및 제조방법
US7042072B1 (en) 2002-08-02 2006-05-09 Amkor Technology, Inc. Semiconductor package and method of manufacturing the same which reduces warpage
SG120879A1 (en) * 2002-08-08 2006-04-26 Micron Technology Inc Packaged microelectronic components
US6747352B1 (en) 2002-08-19 2004-06-08 Amkor Technology, Inc. Integrated circuit having multiple power/ground connections to a single external terminal
US7323772B2 (en) * 2002-08-28 2008-01-29 Micron Technology, Inc. Ball grid array structures and tape-based method of manufacturing same
JP4085788B2 (ja) * 2002-08-30 2008-05-14 日本電気株式会社 半導体装置及びその製造方法、回路基板、電子機器
US7033664B2 (en) 2002-10-22 2006-04-25 Tessera Technologies Hungary Kft Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
SG114585A1 (en) * 2002-11-22 2005-09-28 Micron Technology Inc Packaged microelectronic component assemblies
TW563895U (en) * 2003-03-06 2003-11-21 Advanced Semiconductor Eng Thin type ball grid array package
US6833619B1 (en) * 2003-04-28 2004-12-21 Amkor Technology, Inc. Thin profile semiconductor package which reduces warpage and damage during laser markings
US8574961B2 (en) * 2003-04-29 2013-11-05 Semiconductor Components Industries, Llc Method of marking a low profile packaged semiconductor device
CN100369243C (zh) * 2003-08-22 2008-02-13 矽品精密工业股份有限公司 具有散热结构的半导体封装件
US7368810B2 (en) 2003-08-29 2008-05-06 Micron Technology, Inc. Invertible microfeature device packages
US20050051893A1 (en) * 2003-09-05 2005-03-10 Taiwan Semiconductor Manufacturing Co. SBGA design for low-k integrated circuits (IC)
TWI239603B (en) * 2003-09-12 2005-09-11 Advanced Semiconductor Eng Cavity down type semiconductor package
US6936922B1 (en) 2003-09-26 2005-08-30 Amkor Technology, Inc. Semiconductor package structure reducing warpage and manufacturing method thereof
CN1327514C (zh) * 2003-10-01 2007-07-18 松下电器产业株式会社 配线衬底及其制造方法
TWI232561B (en) * 2003-10-17 2005-05-11 Advanced Semiconductor Eng Substrate having bond pads for bonding redundant solder beads
US20070145548A1 (en) * 2003-12-22 2007-06-28 Amkor Technology, Inc. Stack-type semiconductor package and manufacturing method thereof
US7009296B1 (en) 2004-01-15 2006-03-07 Amkor Technology, Inc. Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US7145238B1 (en) 2004-05-05 2006-12-05 Amkor Technology, Inc. Semiconductor package and substrate having multi-level vias
WO2006025084A1 (ja) * 2004-08-30 2006-03-09 Spansion Llc 積層型半導体装置用キャリア構成、この製造方法及び積層型半導体装置の製造方法
CN100433278C (zh) * 2004-10-29 2008-11-12 矽品精密工业股份有限公司 散热型封装结构及其制造方法
CN1319139C (zh) * 2004-12-01 2007-05-30 中国电子科技集团公司第二十四研究所 硅基传感器可动件局部真空密封保护结构的制作方法
CN100446200C (zh) * 2005-02-28 2008-12-24 矽品精密工业股份有限公司 散热型封装结构及其制法
US8826531B1 (en) 2005-04-05 2014-09-09 Amkor Technology, Inc. Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
US7429799B1 (en) 2005-07-27 2008-09-30 Amkor Technology, Inc. Land patterns for a semiconductor stacking structure and method therefor
US8624129B2 (en) * 2006-01-12 2014-01-07 Samsung Electronics Co., Ltd. Method of attaching a high power surface mount transistor to a printed circuit board
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US20080083981A1 (en) * 2006-06-07 2008-04-10 Romig Matthew D Thermally Enhanced BGA Packages and Methods
US7589398B1 (en) 2006-10-04 2009-09-15 Amkor Technology, Inc. Embedded metal features structure
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
WO2008073084A1 (en) * 2006-12-12 2008-06-19 Agere Systems, Inc. An integrated circuit package and a method for dissipating heat in an integrated circuit package
US7750250B1 (en) 2006-12-22 2010-07-06 Amkor Technology, Inc. Blind via capture pad structure
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
US20100006332A1 (en) * 2007-02-09 2010-01-14 Panasonic Corporation Circuit board, laminating circuit board and electronic apparatus
KR100802393B1 (ko) * 2007-02-15 2008-02-13 삼성전기주식회사 패키지 기판 및 그 제조방법
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
JP2008251608A (ja) * 2007-03-29 2008-10-16 Casio Comput Co Ltd 半導体装置およびその製造方法
US8323771B1 (en) 2007-08-15 2012-12-04 Amkor Technology, Inc. Straight conductor blind via capture pad structure and fabrication method
US20090096076A1 (en) * 2007-10-16 2009-04-16 Jung Young Hy Stacked semiconductor package without reduction in stata storage capacity and method for manufacturing the same
CN101494205B (zh) * 2008-01-23 2011-02-02 瑞鼎科技股份有限公司 集成电路封装体及其制造方法
US20090306811A1 (en) * 2008-06-06 2009-12-10 Raytheon Company Ball grid array cleaning system
KR101481405B1 (ko) * 2008-06-12 2015-01-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8872329B1 (en) 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method
CN103904041A (zh) * 2009-02-19 2014-07-02 日本电气株式会社 真空密封封装
US8097956B2 (en) * 2009-03-12 2012-01-17 Apple Inc. Flexible packaging for chip-on-chip and package-on-package technologies
US7960827B1 (en) 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8623753B1 (en) 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
US8222538B1 (en) 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
US8471154B1 (en) 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8536462B1 (en) 2010-01-22 2013-09-17 Amkor Technology, Inc. Flex circuit package and method
KR101630394B1 (ko) * 2010-03-08 2016-06-24 삼성전자주식회사 패키지 기판, 이를 구비한 반도체 패키지 및 반도체 패키지의 제조방법
US8654538B2 (en) * 2010-03-30 2014-02-18 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US8300423B1 (en) 2010-05-25 2012-10-30 Amkor Technology, Inc. Stackable treated via package and method
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8338229B1 (en) 2010-07-30 2012-12-25 Amkor Technology, Inc. Stackable plasma cleaned via package and method
US8717775B1 (en) 2010-08-02 2014-05-06 Amkor Technology, Inc. Fingerprint sensor package and method
US8337657B1 (en) 2010-10-27 2012-12-25 Amkor Technology, Inc. Mechanical tape separation package and method
US8482134B1 (en) 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
US9748154B1 (en) 2010-11-04 2017-08-29 Amkor Technology, Inc. Wafer level fan out semiconductor device and manufacturing method thereof
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8557629B1 (en) 2010-12-03 2013-10-15 Amkor Technology, Inc. Semiconductor device having overlapped via apertures
US8535961B1 (en) 2010-12-09 2013-09-17 Amkor Technology, Inc. Light emitting diode (LED) package and method
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9013011B1 (en) 2011-03-11 2015-04-21 Amkor Technology, Inc. Stacked and staggered die MEMS package and method
KR101140113B1 (ko) 2011-04-26 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
CN102867814A (zh) * 2011-07-06 2013-01-09 鸿富锦精密工业(深圳)有限公司 芯片封装体
US8653674B1 (en) 2011-09-15 2014-02-18 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8633598B1 (en) 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
TWI440228B (zh) * 2011-09-29 2014-06-01 Viking Tech Corp Light emitting diode package structure and manufacturing method thereof
US9029962B1 (en) 2011-10-12 2015-05-12 Amkor Technology, Inc. Molded cavity substrate MEMS package fabrication method and structure
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9543197B2 (en) 2012-12-19 2017-01-10 Intel Corporation Package with dielectric or anisotropic conductive (ACF) buildup layer
KR101488590B1 (ko) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9508635B2 (en) * 2013-06-27 2016-11-29 STATS ChipPAC Pte. Ltd. Methods of forming conductive jumper traces
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
CN104701190A (zh) * 2013-12-06 2015-06-10 毅宝力科技有限公司 制造腔向下制作载体的系统和方法
SG10201400390YA (en) * 2014-03-05 2015-10-29 Delta Electronics Int L Singapore Pte Ltd Package structure
CN105070694A (zh) * 2015-08-24 2015-11-18 中国科学院国家空间科学中心 一种暴露芯片衬底面的封装方法
CN106971993B (zh) * 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
KR102595276B1 (ko) 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
CN106298696B (zh) * 2016-08-22 2018-10-09 陶乐敏 一种悬架式的集成电路封装机构
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10832991B1 (en) 2019-05-07 2020-11-10 Texas Instruments Incorporated Leadless packaged device with metal die attach
FR3098646B1 (fr) * 2019-07-11 2022-03-25 Thales Sa Composant electronique resistant a l'humidite et procede de realisation d'un tel composant
CN112307710B (zh) * 2020-12-21 2021-04-02 北京智芯仿真科技有限公司 一种系统级集成电路的直流压降分析方法及系统

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630172A (en) * 1983-03-09 1986-12-16 Printed Circuits International Semiconductor chip carrier package with a heat sink
US4835598A (en) * 1985-06-13 1989-05-30 Matsushita Electric Works, Ltd. Wiring board
GB2189084B (en) * 1986-04-10 1989-11-22 Stc Plc Integrated circuit package
US4897508A (en) * 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH04119653A (ja) * 1990-09-11 1992-04-21 Toppan Printing Co Ltd 集積回路素子
US5147821A (en) * 1990-09-28 1992-09-15 Motorola, Inc. Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suction in a molding operation
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
JPH05102212A (ja) * 1991-10-04 1993-04-23 Seiko Epson Corp 配線基板
JPH05283553A (ja) * 1992-03-30 1993-10-29 Nec Corp 混成集積回路装置
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
JPH06275677A (ja) * 1993-03-23 1994-09-30 Shinko Electric Ind Co Ltd 半導体装置用パッケージおよび半導体装置
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5672909A (en) * 1995-02-07 1997-09-30 Amkor Electronics, Inc. Interdigitated wirebond programmable fixed voltage planes
US5572405A (en) * 1995-06-07 1996-11-05 International Business Machines Corporation (Ibm) Thermally enhanced ball grid array package
US5844168A (en) * 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
KR100244090B1 (ko) * 1995-08-07 2000-02-01 김규현 패키지형 집적회로장치와 그 제조방법
JP2814966B2 (ja) * 1995-09-29 1998-10-27 日本電気株式会社 半導体装置
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置
JPH09129784A (ja) * 1995-10-27 1997-05-16 Fuji Xerox Co Ltd 半導体装置およびその製造方法
KR100201380B1 (ko) * 1995-11-15 1999-06-15 김규현 Bga 반도체 패키지의 열방출 구조
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure

Also Published As

Publication number Publication date
GB0212903D0 (en) 2002-07-17
DE19821715B4 (de) 2005-12-29
GB9806078D0 (en) 1998-05-20
US6060778A (en) 2000-05-09
CN100365804C (zh) 2008-01-30
GB2325340A (en) 1998-11-18
JPH1145956A (ja) 1999-02-16
JP3407184B2 (ja) 2003-05-19
GB2325340B (en) 2002-09-11
CN1199927A (zh) 1998-11-25
DE19821715A1 (de) 1999-01-28

Similar Documents

Publication Publication Date Title
TW449844B (en) Ball grid array package having an integrated circuit chip
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
TW415056B (en) Multi-chip packaging structure
JP2819285B2 (ja) 積層型ボトムリード半導体パッケージ
US6326696B1 (en) Electronic package with interconnected chips
JP4332567B2 (ja) 半導体装置の製造方法及び実装方法
JP2002076250A (ja) 半導体装置
JP2006093189A5 (zh)
TW557556B (en) Window-type multi-chip semiconductor package
TW201108360A (en) Package structure and package process
TW200411872A (en) Semiconductor device with improved heat sink structure
US20120223442A1 (en) Method for Manufacturing an Electronic Device
TW497235B (en) Circuit board having center-directional package lands and ball grid array package using the circuit board
JPH0445981B2 (zh)
JP4033968B2 (ja) 複数チップ混載型半導体装置
TW200410380A (en) Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture
JPH0777258B2 (ja) 半導体装置
US7235870B2 (en) Microelectronic multi-chip module
TWI249231B (en) Flip-chip package structure with embedded chip in substrate
TWI229394B (en) Ball grid array semiconductor package with resin coated metal core
JPH1187574A (ja) 垂直実装形半導体チップパッケージ及びそれを含むパッケージモジュール
JPH10284544A (ja) 半導体装置およびその製造方法
JPS6253000A (ja) 半導体の実装構造
JPS59207646A (ja) 半導体装置およびリ−ドフレ−ム
TW479337B (en) High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees