CN104701190A - 制造腔向下制作载体的系统和方法 - Google Patents

制造腔向下制作载体的系统和方法 Download PDF

Info

Publication number
CN104701190A
CN104701190A CN201410858126.2A CN201410858126A CN104701190A CN 104701190 A CN104701190 A CN 104701190A CN 201410858126 A CN201410858126 A CN 201410858126A CN 104701190 A CN104701190 A CN 104701190A
Authority
CN
China
Prior art keywords
top surface
methods according
agent
carrier
apply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410858126.2A
Other languages
English (en)
Inventor
张家骅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Enablink Technologies Ltd
Original Assignee
Enablink Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Enablink Technologies Ltd filed Critical Enablink Technologies Ltd
Publication of CN104701190A publication Critical patent/CN104701190A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Manufacturing Of Electrical Connectors (AREA)

Abstract

本发明涉及制造腔向下制作载体的系统和方法。一种制作具有顶表面和底表面的容腔向下的BGA载体的方法，该方法包括组合导电部分和模制的介电部分，所述介电部分具有相交于所述顶表面的内表面，所述内表面形成用于接收管芯的腔；选择性刻蚀所述导电部分的一部分；以及施加抗焊剂至所述导电部分的顶表面的一部分。

Description

制造腔向下制作载体的系统和方法
相关申请
本申请要求2014年12月06日提交的美国专利申请61/912,745的优先权。要求此较早提交的申请的优先权，该较早提交的申请的内容的全部通过援引包含于此。
发明领域
本发明一般涉及集成电路封装，更具体地涉及用于制作球栅阵列载体的系统和方法。
背景技术
存在各种方法用于形成制造载体。例如，可通过以下的方式来制作：借助于粘合剂层制作在其上层叠金属箔的聚酰亚胺载体，接着图案化该金属和选择性电镀金属部分，随后通过将聚酰亚胺载体层叠到一个厚金属片上以形成管芯容腔(receptacle)，其中厚金属片上有部分蚀刻腔与聚酰亚胺载体的开口对准。制造这样的载体不是一个经济有效的方法，因为该聚酰亚胺是相对昂贵的。此外，聚酰亚胺是相对薄的，并且为了建立足够深的容腔(receptacle)以接收半导体器件，具有部分蚀刻腔的相对厚的金属片是必要的，因此，附加的蚀刻步骤是必要的。
发明内容
本发明的目的的一方面是提供一种新颖的制作球栅阵列载体的系统和方法，其消除和减轻至少一种现有技术的上述确定的缺点。
这些连同其它方面和优点随后将是显而易见的，存在于更全面地在下文中描述并要求保护的结构和操作上的细节中，参照的附图构成本发明的一部分，其中相似的标号通篇指代相似的部件。
附图说明
图1，包括图1(a)-(c)，示出根据一个实施方式的球栅阵列载体的示图；
图2示出了根据一个实施方式的球栅载体制作方法的流程图；
图3，包括图3(a)-(d)，示出了根据一个实施方式的球栅载体制作的截面图；
图4，包括图4(a)-(c)，示出了根据一个实施方式的球栅载体制作的剖视图；
图5，包括图5(a)-(d)，示出了根据一个实施方式的被组装到半导体管芯的球栅载体的剖视图；
图6，包括图6(a)-(g)，示出了根据另一个实施方式的被制作和组装到半导体管芯的球栅载体的剖视图；
图7，包括图7(a)和(b)，示出了根据可替代实施方式的组装的球栅载体的剖视图。
具体实施方式
图1(a)示出根据一个实施方式的一个球栅阵列(BGA)载体125的立体图的俯视图。图1(b)示出俯视图，图1(c)是载体125沿图1(b)中线A-A的剖面图。
现在参看图2，一种制作腔向下(cavity down)的BGA载体的方法一般表示为200。应当理解的是，方法200可以被改变，并且不必如本文所讨论的一样精确地执行，并且这样的变化在本发明的范围内。
在210，介电部分与导电部分结合，示于图3(a)，其中一个导电部分105，它可以由金属例如铜制得，直接与介电部分120结合。介电部分120可以由聚合模制化合物模制而成，聚合模制化合物基于，例如，诸如环氧树脂的粘合材料并填充如二氧化硅或碳化硅的无机填料，或者它可以是成型成适合于制作BGA载体的预定形状的任何合适的塑料化合物。介电部分120可形成为任何预定的厚度。例如介电部分120的示例厚度为大约为0.1毫米。如图3(a)所示，介电部分可以成形以便在中间形成一个腔或容腔110，以使导电部分105在腔110处从载体125的顶表面135和底表面140露出。
用于容纳管芯的腔110可通过介电部分120的内表面111形成，内表面111与形成了顶部入口112和底部入口113的底表面140和顶表面135相交。在一些实施方式中，诸如图3中所示的那个，内表面111可以基本上垂直于顶表面和底表面。在其他实施方式中，内表面111可以以不同于正交，即非正交的方式成角度，使得顶部入口112和底部入口113可以具有不同的周向尺寸。例如，内表面111相对于底表面135的角度可以大于90度，使底部入口113相对于该顶部入口112具有较小的圆周尺寸。在这样的示例中，内表面111将以一小于90度的角度相交于顶表面135。内表面111可以以任何预定的方式布置，以允许内表面111与顶表面和/或底表面的相交处限定形成任何预定圆周形状的入口。圆周的形状的例子可以包括正方形，长方形，三角形，圆形或不规则形状。此外，顶部入口112与底部入口113可以是不同的圆周形状，通过允许该形状不同的方式形成内表面111。在一些实施方式中，腔110可仅在所述内表面相交于顶表面135或底表面140中的一个的地方具有一个入口，而不是两个。
在一些实施方式中，如图3(a)，导电部分105可以是金属箔，如铜箔。箔的厚度可变化，例如18微米，10微米或更薄。在进一步的实施方式中，介电部分120由模制化合物组成，可以通过暴露于高温被模制，以降低粘度，从而允许模制化合物通过模制工具模制。在进一步的实施方式中，介电部分120可以直接与箔相结合，如模制部分120可以直接接合到箔，而不需更借助于介电部分120和箔之间的附加粘合剂层。例如，在一些变形中，包含在模制材料中的接合材料可以有助于介电部分120和箔的直接接合。在其他实施方式中，如图3(b)所示，导电部分可以通过金属化介电部分120的顶表面形成。金属化可以通过在介电部分120上溅射金属籽晶层115(例如铜或铬或钛)或者使用金属(如铜)的浸渍金属电镀的方式实现。随后籽晶层115或者浸渍镀层可以通过进一步电解电镀铜或类似金属以达到所需的厚度。
在220，导电部分105暴露的顶表面，即载体125的顶表面135，如图3(c)所示可以选择性地电镀，其中，所述选择性电镀示于155。金属电镀155可以选择性地沉积在导电部分105的至少一部分，导电部分105在所示实施例中是一个金属箔。在一些实施方式中，电镀155可以被成形以形成接合指和BGA焊盘。在一些变形中，为了能够进行选择性电镀，光可成像电镀阻抗剂被施加到载体125的顶表面。然后顶表面135曝光成预先确定的或选择的图像图案。接着，将电镀阻抗剂显影并且指定的金属图案被电镀在155指示处。可以使用Ag，Ni/Au，Pd或其他本领域技术人员公知的金属。最后，将电镀阻抗剂剥离。
在230，至少一些导电部分105被选择性地蚀刻，如图3(d)145所示。在一些实施方式中，为了按照预定图案进行选择性地蚀刻导电部105，可光成像的抗蚀剂被施加到所述顶表面135，并且所选图像的图案被曝光。然后，抗蚀剂被显影并且被抗蚀剂限定的金属图案被暴露。最后，将顶表面135的抗蚀剂剥离。
在240，抗焊剂可以使用传统方法按照预定的形状或图案选择性地施加至顶表面135。图4(a)示出抗焊剂施加于载体部分125的顶表面135，在160标示处。在一些实施方式中，抗焊剂施加被成形，以使形成BGA焊盘163和接合指166的导电部分区域在载体125的顶表面135处保持露出。
在方法200的250，如图4(b)所示的标示170处，粘合层如热固性环氧树脂或膜被施加至介电部分120的暴露底表面140。在260，散热器175，例如铜或具有高的热导率和低的与所附接的半导体装置的热膨胀系数(CTE)失配的材料，随后施加到粘合剂层的底表面140，如图4(c)所示，完成如图1所示的一个载体125的形成。
如图1所示的载体125，可如图5所示组装。首先，将管芯附接粘合剂或者环氧树脂180放置在腔的顶表面135上，管芯185可与管芯附接粘合剂或者环氧树脂180附接，如图5(a)所示。接着，接合线190可以被施加到管芯和接合指166以将管芯上的接合焊盘(bond pad)与载体125上的接合迹线连接，如图5(b)。接合线例如可以由Au，Cu或Ag组成。然后，作为示例，，使用二次模制(over molding)或分配液体型密封剂，随后进行温度固化，密封剂195可以封装或钝化管芯185、接合线190和接合指166的至少一部分，如图5(c)所示。焊球197也可以使用焊剂通过随后的回流(using flux followed byreflow)，附接到BGA焊盘163，例如如图5(d)所示。所用的焊料金属可包括SnAg，Cu，SnCu以及其他本领域技术人员已知的金属。
在变形中，在如图4(a)所示以及图6(a)重复的抗蚀剂的应用之后，例如，在一侧具有粘合剂的临时带198，可以层压到载体部分125的底表面140，如图6(b)所示。管芯185可以用粘合剂或环氧树脂附接到临时带198的顶表面，如图6(c)所示。接着，接合线190可以被施加到管芯和接合指166以将管芯上的焊盘(bond pad)与载体部分125上的接合迹线连接，如图6(d)所示。
随后，作为示例，，使用二次模制或分配液体型密封剂，随后进行温度固化，密封剂195可以封装或钝化管芯185、接合线190和接合指166至少一部分，如图6(e)所示。焊球197也可以使用焊剂通过回流，附接到BGA焊盘163，例如如图6(f)所示。此时，临时带198可以使用已知的方法被除去，如在图6(g)所示。
最后，参考图7，可以附接热沉(heat sink)199。散热器199可以被附接，使用或不使用散热器(heatspreader)175，分别如图(7)和7(b)所示。在一些实施方式中，热沉199可以通过使用热界面材料191(诸如热化合物)施加。
以上描述的实施方式旨在是实施例，可以由本领域技术人员对其进行变形和改形，均不偏离由所附权利要求书单独所限定的范围。例如，可以变化和组合所讨论的方法、系统和实施例的全部或一部分。

Claims (25)

1.一种制作容腔向下的BGA载体的方法，该载体具有顶表面和底表面，该方法包括：
组合导电部分和模制的介电部分，所述介电部分具有相交于所述顶表面的内表面，所述内表面形成用于接收管芯的腔；
选择性蚀刻所述导电部分的一部分；以及
施加抗焊剂至所述导电部分的顶表面的一部分。
2.根据权利要求1的方法，其中所述介电部分由聚合模制化合物模制。
3.根据权利要求2的方法，其中所述聚合模制化合物包括接合材料。
4.根据权利要求2的方法，其中所述接合材料包含填充有无机填料的环氧树脂。
5.根据权利要求4的方法，其中所述无机填料包括二氧化硅或碳化硅中的至少一个或塑料化合物。
6.根据权利要求1的方法，其中所述内表面与所述顶表面正交相交。
7.根据权利要求1的方法，其中所述内表面与所述顶表面非正交相交。
8.根据权利要求1的方法，其中所述腔的形状是正方形，长方形，三角形，圆形或不规则形状之一。
9.根据权利要求1的方法，还包括：选择性地电镀所述顶表面处的所述导电部分。
10.根据权利要求9的方法，其中所述选择性地电镀被成形以形成接合指和BGA焊盘。
11.根据权利要求9的方法，其中所述选择性地电镀包括：施加光成像电镀阻抗剂至所述顶表面，将所述光成像电镀阻抗剂曝光成图像图案，显影所述阻抗剂，在所述电镀阻抗剂未被曝光的部分沉积金属，以及剥离所述电镀阻抗剂。
12.根据权利要求11的方法，其中所述金属是Ag，Ni/Au或Pd中的一个。
13.根据权利要求9的方法，其中选择性地蚀刻包括：施加光成像抗蚀剂至所述顶表面，将光成像抗蚀剂曝光成图像图案，显影所述抗蚀剂，以及剥离所述抗蚀剂。
14.根据权利要求1的方法，其中根据预定形状选择性地执行施加抗焊剂至所述顶表面。
15.根据权利要求14的方法，其中所述预定形状使得形成BGA焊盘和接合指的所述导电部分的区域在所述顶表面处保持暴露。
16.根据权利要求15所述的方法，还包括施加粘合层至所述底表面的暴露部分。
17.根据权利要求16所述的方法，其中所述粘合层包括热固性环氧树脂或膜之一。
18.根据权利要求16所述的方法，进一步包括施加散热器至所述粘合层的底表面。
19.根据权利要求16所述的方法，其中在施加抗焊剂之后，将一侧具有粘合剂的临时带层压至所述底表面上。
20.根据权利要求19所述的方法，进一步包括利用粘合剂或环氧树脂之一将半导体管芯附接到所述临时带的顶表面。
21.根据权利要求20所述的方法，进一步包括引线接合，以通过接合线将管芯上的接合焊盘连接至所述接合指。
22.根据权利要求21所述的方法，进一步包括使用密封剂封装所述管芯、所述接合线以及接合指的至少一部分。
23.根据权利要求22所述的方法，进一步包括使用焊剂将焊球附接到所述BGA焊盘随后回流，并剥离所述临时带。
24.根据权利要求23所述的方法，进一步包括使用热界面材料将热沉附接到所述顶表面。
25.一种根据权利要求1的方法制作的容腔向下的BGA载体。
CN201410858126.2A 2013-12-06 2014-12-05 制造腔向下制作载体的系统和方法 Pending CN104701190A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361912745P 2013-12-06 2013-12-06
US61/912,745 2013-12-06

Publications (1)

Publication Number Publication Date
CN104701190A true CN104701190A (zh) 2015-06-10

Family

ID=52011069

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410858126.2A Pending CN104701190A (zh) 2013-12-06 2014-12-05 制造腔向下制作载体的系统和方法

Country Status (4)

Country Link
US (2) US9786518B2 (zh)
EP (1) EP2881986A3 (zh)
CN (1) CN104701190A (zh)
HK (1) HK1211385A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113286421A (zh) * 2021-04-16 2021-08-20 珠海杰赛科技有限公司 密集bga的导线结构、印制电路板及制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10206288B2 (en) 2015-08-13 2019-02-12 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate
US10165677B2 (en) * 2015-12-10 2018-12-25 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate without laser cut
US10847384B2 (en) 2017-05-31 2020-11-24 Palo Alto Research Center Incorporated Method and fixture for chip attachment to physical objects

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796038A (en) * 1997-06-16 1998-08-18 Vlsi Technology, Inc. Technique to produce cavity-up HBGA packages
JP2000183247A (ja) * 1998-12-18 2000-06-30 Nec Corp 半導体装置
JP2001274276A (ja) * 2000-03-27 2001-10-05 Sumitomo Metal Electronics Devices Inc 放熱型ｂｇａパッケージ及びその製造方法
CN1359150A (zh) * 2002-01-15 2002-07-17 威盛电子股份有限公司 球脚阵列封装基板及其制造方法
US20030001285A1 (en) * 1999-05-20 2003-01-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
CN100365804C (zh) * 1997-05-17 2008-01-30 现代电子产业株式会社 封装集成电路元件及其制造方法
CN103250244A (zh) * 2010-12-03 2013-08-14 英特尔公司 低轮廓微电子封装及其制造方法以及包含该低轮廓微电子封装的电子组件

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422313A (en) * 1994-05-03 1995-06-06 Texas Instruments Incorporated Integrated circuit device and manufacturing method using photoresist lead covering
JP3752949B2 (ja) 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
US6528869B1 (en) * 2001-04-06 2003-03-04 Amkor Technology, Inc. Semiconductor package with molded substrate and recessed input/output terminals
US20040175582A1 (en) 2002-12-05 2004-09-09 Olin Corporation, A Corporation Of The Commonwealth Of Virginia Laser ablation resistant copper foil
US7157791B1 (en) 2004-06-11 2007-01-02 Bridge Semiconductor Corporation Semiconductor chip assembly with press-fit ground plane
US7550319B2 (en) * 2005-09-01 2009-06-23 E. I. Du Pont De Nemours And Company Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
JPWO2007126090A1 (ja) 2006-04-27 2009-09-17 日本電気株式会社 回路基板、電子デバイス装置及び回路基板の製造方法
US20090102050A1 (en) * 2007-10-17 2009-04-23 Phoenix Precision Technology Corporation Solder ball disposing surface structure of package substrate
TW201041105A (en) 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8642897B2 (en) 2010-10-12 2014-02-04 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9049791B2 (en) * 2013-06-07 2015-06-02 Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd. Terminations and couplings between chips and substrates

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100365804C (zh) * 1997-05-17 2008-01-30 现代电子产业株式会社 封装集成电路元件及其制造方法
US5796038A (en) * 1997-06-16 1998-08-18 Vlsi Technology, Inc. Technique to produce cavity-up HBGA packages
JP2000183247A (ja) * 1998-12-18 2000-06-30 Nec Corp 半導体装置
US20030001285A1 (en) * 1999-05-20 2003-01-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
JP2001274276A (ja) * 2000-03-27 2001-10-05 Sumitomo Metal Electronics Devices Inc 放熱型ｂｇａパッケージ及びその製造方法
CN1359150A (zh) * 2002-01-15 2002-07-17 威盛电子股份有限公司 球脚阵列封装基板及其制造方法
CN103250244A (zh) * 2010-12-03 2013-08-14 英特尔公司 低轮廓微电子封装及其制造方法以及包含该低轮廓微电子封装的电子组件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113286421A (zh) * 2021-04-16 2021-08-20 珠海杰赛科技有限公司 密集bga的导线结构、印制电路板及制造方法

Also Published As

Publication number Publication date
EP2881986A3 (en) 2015-08-12
US9786518B2 (en) 2017-10-10
US20170365489A1 (en) 2017-12-21
US20150162218A1 (en) 2015-06-11
HK1211385A1 (zh) 2016-05-20
EP2881986A2 (en) 2015-06-10

Similar Documents

Publication Publication Date Title
CN102629561B (zh) 叠层式半导体组件制备方法
US8314499B2 (en) Flexible and stackable semiconductor die packages having thin patterned conductive layers
KR100484696B1 (ko) 회로 장치 및 그 제조 방법
US7119432B2 (en) Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
CN100547778C (zh) 柔性电路衬底及形成方法以及包括柔性电路衬底的组件
US20100059785A1 (en) Light emitting device and method of fabricating the same
KR100400629B1 (ko) 회로 장치 및 그 제조 방법
JP6669586B2 (ja) 半導体装置、半導体装置の製造方法
KR101713643B1 (ko) 칩 패키지
CN204792778U (zh) 半导体衬底结构及半导体封装
JP2002064226A (ja) 光 源
TWI435666B (zh) 輻散熱電路板及其製造方法
CN104701190A (zh) 制造腔向下制作载体的系统和方法
TW201804575A (zh) 整合扇出型封裝
US20100276797A1 (en) Semiconductor device
KR20020020170A (ko) 반도체 장치 및 그 제조 방법
US20160056094A1 (en) Ball grid array package with more signal routing structures
US20080135939A1 (en) Fabrication method of semiconductor package and structure thereof
CN106298692B (zh) 芯片封装结构的制作方法
JP6111284B2 (ja) 中空パッケージの製造方法、固体撮像素子の製造方法、中空パッケージおよび固体撮像素子
CN210575899U (zh) 嵌入式多芯片及元件sip扇出型封装结构
CN104766805A (zh) 制造装配载体的系统和方法
CN109526139B (zh) 印刷电路板结构及其形成方法
JP3668090B2 (ja) 実装基板およびそれを用いた回路モジュール
US9735032B2 (en) System and method for manufacturing a fabricated carrier

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1211385

Country of ref document: HK

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150610

REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1211385

Country of ref document: HK