TW374173B - Bitline load and precharge structure for an SRAM memory - Google Patents

Bitline load and precharge structure for an SRAM memory

Info

Publication number
TW374173B
TW374173B TW087100838A TW87100838A TW374173B TW 374173 B TW374173 B TW 374173B TW 087100838 A TW087100838 A TW 087100838A TW 87100838 A TW87100838 A TW 87100838A TW 374173 B TW374173 B TW 374173B
Authority
TW
Taiwan
Prior art keywords
sram
read
pmos transistor
mode
write
Prior art date
Application number
TW087100838A
Other languages
English (en)
Inventor
Saroj Pathak
James E Payne
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of TW374173B publication Critical patent/TW374173B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
TW087100838A 1997-01-24 1998-01-22 Bitline load and precharge structure for an SRAM memory TW374173B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/788,523 US5781469A (en) 1997-01-24 1997-01-24 Bitline load and precharge structure for an SRAM memory

Publications (1)

Publication Number Publication Date
TW374173B true TW374173B (en) 1999-11-11

Family

ID=25144750

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087100838A TW374173B (en) 1997-01-24 1998-01-22 Bitline load and precharge structure for an SRAM memory

Country Status (8)

Country Link
US (1) US5781469A (zh)
EP (1) EP0960421B1 (zh)
JP (1) JP2001509299A (zh)
KR (1) KR100483759B1 (zh)
CN (1) CN100390896C (zh)
DE (1) DE69822800T2 (zh)
TW (1) TW374173B (zh)
WO (1) WO1998033183A1 (zh)

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US7342832B2 (en) * 2005-11-16 2008-03-11 Actel Corporation Bit line pre-settlement circuit and method for flash memory sensing scheme
US7414904B2 (en) * 2006-12-12 2008-08-19 International Business Machines Corporation Method for evaluating storage cell design using a wordline timing and cell access detection circuit
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US7545176B2 (en) * 2007-10-25 2009-06-09 International Business Machines Corporation Energy-saving circuit and method using charge equalization across complementary nodes
WO2010042820A1 (en) * 2008-10-10 2010-04-15 Arizona Board Of Regents, For And On Behalf Of Arizona State University Differential threshold voltage non-volatile memory and related methods
JP5429383B2 (ja) * 2010-08-11 2014-02-26 富士通株式会社 半導体記憶装置
US8817562B2 (en) * 2012-07-31 2014-08-26 Freescale Semiconductor, Inc. Devices and methods for controlling memory cell pre-charge operations
US8929120B2 (en) 2012-08-29 2015-01-06 Micron Technology, Inc. Diode segmentation in memory
US9030893B2 (en) * 2013-02-06 2015-05-12 Qualcomm Incorporated Write driver for write assistance in memory device
CN103187093B (zh) * 2013-03-18 2016-03-23 西安华芯半导体有限公司 静态随机存储器及其存取控制方法及其位线预充电电路
US9508405B2 (en) * 2013-10-03 2016-11-29 Stmicroelectronics International N.V. Method and circuit to enable wide supply voltage difference in multi-supply memory
CN105632544B (zh) * 2014-10-27 2018-05-04 华为技术有限公司 一种磁性存储器
US9384826B2 (en) 2014-12-05 2016-07-05 Texas Instruments Incorporated Circuits and methods for performance optimization of SRAM memory
CN107851453B (zh) * 2015-07-27 2021-10-15 电力荡半导体有限公司 采用谐振驱动电路的低功耗sram位单元
US10607692B2 (en) * 2017-06-29 2020-03-31 SK Hynix Inc. Serializer and memory device including the same
US10878892B2 (en) 2018-04-23 2020-12-29 Arm Limited Integrated circuit using discharging circuitries for bit lines
TWI802703B (zh) 2019-05-31 2023-05-21 聯華電子股份有限公司 靜態隨機存取記憶體裝置
US11676656B2 (en) * 2021-02-05 2023-06-13 Arm Limited Memory architecture with DC biasing
US11784648B2 (en) 2021-06-02 2023-10-10 Power Down Semiconductor, Inc. Low power interconnect using resonant drive circuitry

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Also Published As

Publication number Publication date
CN1244281A (zh) 2000-02-09
EP0960421A4 (en) 2003-07-09
KR20000070411A (ko) 2000-11-25
DE69822800D1 (de) 2004-05-06
CN100390896C (zh) 2008-05-28
US5781469A (en) 1998-07-14
DE69822800T2 (de) 2004-12-30
KR100483759B1 (ko) 2005-04-19
EP0960421B1 (en) 2004-03-31
WO1998033183A1 (en) 1998-07-30
EP0960421A1 (en) 1999-12-01
JP2001509299A (ja) 2001-07-10

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MM4A Annulment or lapse of patent due to non-payment of fees