TW201737767A - 多層電路基板 - Google Patents
多層電路基板 Download PDFInfo
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Abstract
本發明係一種多層電路基板,多層電路基板(1)係藉由絕緣層而加以層積複數之配線層所成之多層電路基板,其中,具備被覆形成於表面側絕緣層(28)之表面配線層(30)之抗焊劑層(32),而表面配線層(30)係包含加以接合連接器(10)的腳端子(18)之腳端子用墊片(24),而抗焊劑層(32)係具有使腳端子用墊片(24)的一部分露出之腳端子用開口部(46),於跨越在腳端子用墊片(24)的下部之腳端子用開口部(46)之輪廓線的特定範圍,加以設置有腳端子用貫孔(48),而腳端子用貫孔(48)係連接第1內部配線層(54)與腳端子用墊片(24)。
Description
本發明係有關多層電路基板,詳細係有關加以安裝連接器之多層電路基板。
對於電子機器係含有各種的多層電路基板。對於如此之多層電路基板係有加以安裝使用於與其他電子機器等之連接的連接器之構成。連接器係具有:接受對方側的電子機器之管套的器殼,和加以設置於器殼內之連接銷,和加以連接於連接銷,自器殼之特定位置突出之信號端子。此信號端子係附上焊錫於加以設置於電路基板上之信號端子用墊片。並且,信號端子用墊片係加以連接於特定之電路圖案。因此,經由加以插入管套於器殼之時,加以電性連接一方的電子機器與另一方之電子機器。
但對於連接器之器殼而言,以比較大的力而進行管套的拔插,或者在將管套加以連接於器殼之狀態,扭轉於與拔插的方向不同之方向時,加上應力於連接器係自電路基板揭下之方向。如此,當加上應力於自電路基板揭下連接器之方向時,應力集中於信號端子與信號端子用
墊片之接合部,如此之接合部則產生剝離,而有引起接合不良之情況。
為了抑制如此之接合不良的產生,作為呈即使加上應力,器殼則對於電路基板而言未被揭下地,為了迴避應力集中於接合部之情況的對策則做種種檢討。作為如此的對策之一,知道有使用如專利文獻1所示之補強片而固定器殼者。如根據此專利文獻1的補強片,即使加上來自外部之大的應力,亦可抑制連接器之器殼則對於電路基板而言加以剝落情況,而抑制接合不良的產生。
但近年,加以要求有電子機器的小型化,而在搭載於多層電路基板之連接器中,小型化則亦進展著。作為加以進展如此小型化之連接器(以下,稱為小型連接器),係加以開發有USB連接器或微USB連接器之構成。
在如此之小型連接器中,亦有必要抑制伴隨著如上述之外部應力的附加之接合不良的產生。
但,由專利文獻1所代表之補強片係需要大的安裝空間之故,而阻礙電子模組的小型化。因而,對於小型連接器之補強係不傾向如此之補強片。
通常,在小型連接器中,自器殼延伸的固定用的腳端子,則經由附上焊錫於設置在電路基板上之腳端子用墊片之時而加以固定。因此,為了提高接合部的強度,加以採用增加焊錫的量之對策。
[專利文獻1]日本特開2006-048971號公報
當增加焊錫的量而提高焊錫接合部的強度時,腳端子與腳端子用墊片係成為不易分離。但,當自外部加上應力於連接器時,腳端子與腳端子用墊片係雖分離,但腳端子用墊片則有自電路基板脫離之情況,而伴隨於此,信號端子用墊片亦自電路基板剝離,而產生有接合不良。
於腳端子用墊片及信號端子用墊片之周緣部,使抗焊劑層交疊,進行防止此等墊片的剝離之情況。
但,對於小型連接器而言,自操作者遍佈複數次加以加上強的應力至不規則方向時,僅猶如上述之抗焊劑的被覆,充分地防止墊片的剝離者為困難。因此,一般而言,在電路基板上採用呈被覆焊錫接合部地塗佈補強用樹脂,進行補強而防止接合部的剝離之對策。
但如上述之補強用樹脂的塗佈係附設焊錫結束之後,必須對於特定範圍進行,而作業工數則增加。另外,對於細微部分塗佈補強用樹脂之情況係成為煩雜之作業,而花上時間勞力。更且,補強用樹脂的材料成本亦增加因此,塗佈補強用樹脂之補強對策係招致多層電路基板
之製造效率的下降,及製造成本增加之故,而省略為佳。
本發明係依據上述情事所作為之構成,其目的為提供:即使未塗佈補強樹脂,亦可防止墊片產生剝離之情況,因而可謀求製造成本之削減的多層電路基板。
為了達成上述目的,如根據本發明,加以提供藉由絕緣層而加以層積複數之配線層所成之多層電路基板,其中,具備被覆位於前述複數之配線層之中最表面側的表面配線層之抗焊劑層,而前述表面配線層係包含加以接合安裝於前述多層電路基板之表面的連接器的端子之墊片,而前述抗焊劑層係具有使前述墊片的一部分露出之開口部,於跨越在前述墊片的下部之前述開口部之輪廓線的特定範圍,加以設置有貫孔,而前述貫孔係連接前述配線層之中位於前述多層電路基板之內部的內部配線層與前述墊片的多層電路基板。
在此,前述貫孔係作為沿著前述輪廓線而加以複數設置之形態者為佳。
另外,前述內部配線層之中,位於相同階層之內部配線層係作為複數之前述貫孔之中,與2個以上的貫孔加以連接之形態者為佳。
更理想係前述開口部係平面視形狀為構成矩形狀,而前述貫孔係作為各加以設置於在前述矩形狀之角的部分及邊的部分之形態。
更且,前述貫孔係作為延伸至位於前述配線
層之中最為背面側之背面配線層,連接前述墊片,前述內部配線層及前述背面配線層之形態者為佳。
當將連接器的端子附上焊錫於墊片時,對於墊片係加以形成有焊錫接合部,於在抗焊劑層之開口部的輪廓線之部分,加以定位焊錫接合部的前端。並且,當對於連接器而言,自外部加上應力時,於焊錫接合部的前端,即在抗焊劑層之開口部的輪廓線之部分,容易集中應力。本發明之多層電路基板係於跨越在前述墊片下部前述開口部的輪廓線的特定範圍,加以設置貫孔,而前述貫孔係連接前述墊片與前述內部配線層。因此,因於容易集中應力的部分,存在有與內部配線層加以連接之貫孔之故,如此之貫孔則發揮定準效果,而即使未進行補強樹脂的塗佈,亦可充分地防止墊片的剝離者。
因而,如根據本發明,可提供:即使未塗佈補強樹脂,亦可防止墊片產生剝離情況,因而可謀求製造成本之削減的多層電路基板者。
1‧‧‧多層電路基板
3‧‧‧多層電路基板
10‧‧‧連接器
18‧‧‧腳端子
22‧‧‧信號端子
24‧‧‧腳端子用墊片
26‧‧‧信號端子用墊片
28‧‧‧表面側絕緣層
30‧‧‧表面配線層
32‧‧‧抗焊劑層
46‧‧‧腳端子用開口部
48‧‧‧腳端子用貫孔
54‧‧‧第1內部配線層
60‧‧‧信號端子用開口部
62‧‧‧信號端子用貫孔
圖1係概略地顯示自連接器的插入口側而視之形態及自連接器之後壁側而視之形態的斜視圖。
圖2係顯示第1實施形態之多層電路基板之一部分的
平面圖。
圖3係沿著圖2之III-III線的剖面圖。
圖4係沿著圖2之IV-IV線的剖面圖。
圖5係對應於在第2實施形態之多層電路基板的之圖3的剖面圖。
圖6係對應於在第2實施形態之多層電路基板的之圖4的剖面圖。
對於有關本發明之多層電路基板1,參照圖面同時,於以下加以說明。
多層電路基板1係藉由絕緣層而加以重疊多數之配線層所成的多層電路基板。對於此多層電路基板之特定位置係加以安裝各種電子構件及連接器。
連接器10係如圖1之(1)及(2)所示地,包含有:具有插入有其他電子構件之管套(未圖示)的插入口12之器殼14,和加以配置於器殼14之兩側壁16的腳端子18,和自位於與插入口12相反側之器殼14的後壁20突出之信號端子22。
此連接器10係經由加以附上焊錫於多層電路基板1之表面的特定位置而安裝腳端子18及信號端子22。
在安裝在多層電路基板1表面之連接器10的部分中,如圖2所示,加以設置有接合連接器10之腳端子18的腳端子用墊片24,和接合連接器10之信號端子22的信號端子用墊片26。
此等腳端子用墊片24及信號端子用墊片26係加以設置於位置在多層電路基板1之最表面側的表面側絕緣層28上的表面配線層30之特定處,則加以成特定形狀而加以形成。然而,表面配線層30係其他亦形成特定形狀的配線圖案34。
在此,在表面側絕緣層28及表面配線層30中,於無法避免與焊錫之接觸的部分,加以設置抗焊劑層32。上述之腳端子用墊片24及信號端子用墊片26的部分係因相反地必須與焊錫接觸而形成焊錫接合部之故,對於腳端子用墊片24及信號端子用墊片26上係未設置抗焊劑層32,而此等墊片係加以部分地露出。
腳端子用墊片24係如從圖2了解到,將連接器10加以安裝於安裝預定處36時,配設於器殼14之兩側壁16的腳端子18則加以設置於各加以定位的特定位置。腳端子用墊片24係平面視形狀則構成矩形狀,自外周緣38,僅特定長度進入至內側的範圍(以下,稱作外周緣部40)則經由抗焊劑層32而加以被覆。並且,腳端子用墊片24係除了外周緣部40以外的部分,即未由抗焊劑層32所被覆的部分則露出。
在此,在抗焊劑層32中,將與腳端子用墊片
24之外周緣部40重疊之部分,作為重疊部44,而使腳端子用墊片24露出之部分係作為開口部(以下,稱為腳端子用開口部46)。此腳端子用開口部46係構成呈縮小腳端子用墊片24之輪廓的形成之矩形狀的輪廓。
在本實施形態中,係於跨越在腳端子用墊片24之下部的上述之抗焊劑層32的腳端子用開口部46之輪廓線的特定範圍,加以設置貫孔(以下,稱為腳端子用貫孔48)。詳細係呈在圖2中,以假想圓所描繪地,沿著腳端子用開口部46之矩形的輪廓線,加以設置腳端子用貫孔48。更詳細係每1個之腳端子用墊片24,於矩形的輪廓線之4個角的部分,加以設置各1個,而於矩形的輪廓線之長邊50的部分,加以設置各2個,於矩形的輪廓線之短邊52的部分,加以設置各1個之合計10個的腳端子用貫孔48。
此腳端子用貫孔48係如圖3所示,將表面配線層30作為第1層之配線層時,到達至第2層之配線層的第1內部配線層54,而連接如此之第1內部配線層54與腳端子用墊片24。
在此,在圖3中,各參照符號80係顯示中央絕緣層,參照符號82係顯示第3層之配線層的第2內部配線層,參照符號84係顯示背面側絕緣層,參照符號86係顯示背面配線層,參照符號88係顯示背面側抗焊劑層。然而,關於後述之圖4~圖6亦為同樣。
另一方面,信號端子用墊片26係如從圖2了
解到,將連接器10加以安裝於安裝預定處36時,自器殼14之後壁20突出的信號端子22則加以設置於各加以定位的特定位置。
信號端子用墊片26係表面配線層30之配線圖案34之一部分則加工為寬幅而加以形成,平面視形狀則構成矩形狀。在此信號端子用墊片26中,較配線圖案34的寬度加以擴張之部分(以下,稱為拓寬部56)則由抗焊劑層32所被覆,而與配線圖案34相同寬度之部分係加以露出。也就是,在存在有各信號端子用墊片26之部分的抗焊劑層32中,如從圖2了解到地,加以設置矩形狀之開口部(以下,稱為信號端子用開口部60)。
在本實施形態中,係於跨越在信號端子用墊片26之下部的抗焊劑層32的信號端子用開口部60之輪廓線的特定範圍,加以設置貫孔(以下,稱為信號端子用貫孔62)。詳細係呈在圖2中,以假想圓所描繪地,於信號端子用開口部60之矩形的輪廓線之短邊64的部分,加以設置信號端子用貫孔62。更詳細係每1個之信號端子用墊片26,於矩形之輪廓線的短邊64部分,加以設置各1個,合計2個之信號端子用貫孔62。然而,對於各信號端子間如有餘量,作成擴大信號端子的圖案寬度,於信號端子用開口部60之長邊的部分設置信號端子用貫孔62,而於信號端子長邊側亦被覆抗焊劑之形態亦可。
此信號端子用貫孔62係如圖4所示,將表面配線層30作為第1層之配線層時,到達至第2層之配線
層的第1內部配線層54,而連接如此之第1內部配線層54與信號端子用墊片26。
如以上之多層電路基板1係可經由製造自組成法等之以往所使用之多層電路基板之製造方法而製造者。此時,呈成為如上述之位置關係地,設置表面配線層30,第1內部配線層54,抗焊劑層30,各絕緣層,腳端子用墊片24,信號端子用墊片26,腳端子用貫孔48及信號端子用貫孔62等。另外,作為腳端子用貫孔48及信號端子用貫孔62之形成方法係並非特別加以限制,而經由使用於一般之方法而加以形成。此時,各貫孔的內部係作為以銅電鍍加以填滿之填充貫孔者為佳。
對於具備如以上之腳端子用貫孔48及信號端子用貫孔62的多層電路基板1,係經由附上焊錫而加以實裝各種電子構件及連接器10。
加以附上焊錫之連接器10係如圖3及圖4所示,腳端子18則藉由焊錫接合部70而加以接合於腳端子用墊片24上,而信號端子22則藉由焊錫接合部72而加以接合於信號端子用墊片26上。
在此,例如,使用者則對於連接器10而言複數次進行管套的插拔,對於連接器10而言,反覆施加大的應力於圖3所示之箭頭A方向及箭頭B方向,以及如圖4的箭頭C方向,施加大的應力於與正常的插拔方向不同之方向之情況,於焊錫接合部70,72之前端部分,即焊錫圓角的前端部分,容易集中應力。通常,焊錫圓角的
前端部分係因延伸至抗焊劑層32之開口部(腳端子用開口部46,信號端子用開口部60)之輪廓線的部分之故,於輪廓線的附近,加以定位焊錫圓角的前端部分。隨之,在墊片(腳端子用墊片24,信號端子用墊片26)之抗焊劑層32之開口部的輪廓線附近係容易受到應力,而如此的部分容易成起點剝落。對於如此之情況而言,在本實施形態之多層電路基板1中,於抗焊劑層32之開口部的輪廓線下部,存在有腳端子用貫孔48及信號端子用貫孔62,而此等貫孔則連接墊片(腳端子用墊片24,信號端子用墊片26)與第1內部配線層54。此等貫孔係發揮定準效果之故,即使作為施加應力於墊片的部分,亦可有效地防止墊片被剝落之情況者。因而,可省略經由補強樹脂的補強。
以下,作為另外的實施形態,對於第2實施形態加以說明。對於有關的說明,僅說明與第1實施形態不同的部分,對於與第1實施形態相同的部分,由使用相同參照符號而省略詳細之說明。
在第2實施形態之多層電路基板3中,如圖5及圖6所示,作為腳端子用貫孔90及信號端子用貫孔92,除了使用自表面配線層30,延伸至第1內部配線層54,第2內部配線層82及背面配線層86為止之貫通貫孔之外,係與第1實施形態同樣。
此貫通貫孔的形成係並非特別加以限定,而可經由一般的形成方法而形成者。在本實施形態中,貫通貫孔之內部係由樹脂94而加以充填。也就是,腳端子用貫孔90及信號端子用貫孔92係埋孔貫通貫孔。
如根據第2實施形態之多層電路基板3,位於腳端子用墊片24及信號端子用墊片26下部的貫孔則不僅第1內部配線層54,而到達至第2內部配線層82及背面側的背面配線層86,與此等的層加以連接之故,得到較第1實施形態為強之定準效果。因此,在加以施加應力於連接器10之情況,可更抑制墊片被剝落之不良的發生者。
在此,如圖6所示,在信號端子用墊片26下部中,第1內部配線層54及第2內部配線層82係在圖6中右側的信號端子用貫孔92R與圖6中左側之信號端子用貫孔92L之間而加以分斷。另一方面,如圖5所示,在腳端子用墊片24下部中,第1內部配線層54及第2內部配線層82係在圖5中右側的腳端子用貫孔90R與圖6中左側之腳端子用貫孔90L之間而加以連接。如此,相同階層之內部配線層則比較於在貫孔與貫孔之間加以分斷的形態(以下,稱為分斷形態),在2個以上的貫孔之間加以連接之形態(以下,稱為連接形態)者則可增大與在和貫孔連接之內部配線層的接觸層接觸之面積。因此,與貫孔連接之內部配線層係比較於分斷形態,連接形態者則對於加上於剝離墊片之方向,也就是拔出貫孔之方向的應力而
言,有更強的阻抗,更發揮定準效果之故而為理想。然而,採用上述之連接形態的情況,以最短距離而配設內部配線層於2個以上的貫孔之間者則更佳。如此,如以最短距離而連結貫孔彼此,貫孔彼此之一體性則增加,更加以增強定準效果之故。
然而,如上述,對於比較於分斷形態,連接形態則得到更優越之定準效果之情況,係並非加以限定於貫通貫孔者,而未加以貫通至背面配線層,而僅延伸至途中之內部配線層的貫孔則亦為同樣。
然而,本發明係並不限定於上述之實施形態者,而可做種種的變形。例如,貫孔的形成位置,個數係可任意地設定。另外,與貫孔連接之配線層亦可作任意的選擇。另外,墊片的形狀係並非限定於矩形,而可任意地選擇多角形,圓形,橢圓形等。
1‧‧‧多層電路基板
10‧‧‧連接器
14‧‧‧器殼
16‧‧‧兩側壁
18‧‧‧腳端子
20‧‧‧後壁
22‧‧‧信號端子
24‧‧‧腳端子用墊片
28‧‧‧表面側絕緣層
30‧‧‧表面配線層
32‧‧‧抗焊劑層
46‧‧‧腳端子用開口部
48‧‧‧腳端子用貫孔
54‧‧‧第1內部配線層
70、72‧‧‧焊錫接合部
80‧‧‧中央絕緣層
82‧‧‧第2內部配線層
84‧‧‧背面側絕緣層
86‧‧‧背面配線層
88‧‧‧背面側抗焊劑層
Claims (5)
- 一種多層電路基板,係藉由絕緣層而加以層積複數之配線層所成之多層電路基板,其特徵為具備:被覆位於前述複數之配線層之中最表面側的表面配線層之抗焊劑層,前述表面配線層係包含加以接合安裝於前述多層電路基板之表面的連接器的端子之墊片,前述抗焊劑層係具有使前述墊片的一部分露出之開口部,於跨越在前述墊片的下部之前述開口部之輪廓線的特定範圍,加以設置有貫孔,前述貫孔係連接前述配線層之中位於前述多層電路基板之內部的內部配線層與前述墊片。
- 如申請專利範圍第1項記載之多層電路基板,其中,前述貫孔係沿著前述輪廓線而加以複數設置。
- 如申請專利範圍第2項記載之多層電路基板,其中,前述內部配線層之中,位於相同階層之內部配線層係與複數之前述貫孔之中,2個以上的貫孔加以連接者。
- 如申請專利範圍第1項至第3項任一項記載之多層電路基板,其中,前述開口部係平面視形狀則構成矩形狀,前述貫孔係各加以設置於在前述矩形狀之角的部分及邊的部分。
- 如申請專利範圍第1項至第4項任一項記載之多層電路基板,其中,前述貫孔係延伸至位於前述配線層之中 最背面側之背面配線層,連接前述墊片,前述內部配線層及前述背面配線層者。
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JP4416616B2 (ja) * | 2004-09-29 | 2010-02-17 | 株式会社リコー | 電子部品実装体及び電子機器 |
JP2006210515A (ja) * | 2005-01-26 | 2006-08-10 | Aisin Seiki Co Ltd | プリント基板 |
CN101507373A (zh) * | 2006-06-30 | 2009-08-12 | 日本电气株式会社 | 布线板、使用布线板的半导体器件、及其制造方法 |
JP2008218489A (ja) * | 2007-02-28 | 2008-09-18 | Sharp Corp | 多層プリント配線板の製造方法 |
JP2009021510A (ja) * | 2007-07-13 | 2009-01-29 | Sony Corp | プリント基板及びその製造方法 |
KR100867505B1 (ko) * | 2007-09-19 | 2008-11-07 | 삼성전기주식회사 | 적층형 칩 커패시터 실장용 회로기판 및 적층형 칩커패시터를 구비한 회로기판 장치 |
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JP5280309B2 (ja) * | 2009-07-17 | 2013-09-04 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
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CN101888741B (zh) * | 2010-07-02 | 2012-05-02 | 深圳市顶星数码网络技术有限公司 | 印刷电路板及笔记本电脑 |
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JP2012243488A (ja) * | 2011-05-18 | 2012-12-10 | Alps Electric Co Ltd | 電子部品用ソケット |
US10056323B2 (en) * | 2014-04-24 | 2018-08-21 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same |
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JP6480798B2 (ja) * | 2015-04-23 | 2019-03-13 | 株式会社ヨコオ | ソケット |
WO2018216646A1 (ja) * | 2017-05-26 | 2018-11-29 | 三菱電機株式会社 | 半導体装置 |
-
2016
- 2016-03-31 JP JP2016071038A patent/JP6741456B2/ja active Active
-
2017
- 2017-03-15 TW TW106108571A patent/TWI637667B/zh active
- 2017-03-16 US US16/089,033 patent/US20190132952A1/en not_active Abandoned
- 2017-03-16 WO PCT/JP2017/010751 patent/WO2017169858A1/ja active Application Filing
- 2017-03-16 KR KR1020187031613A patent/KR20180128048A/ko not_active Application Discontinuation
- 2017-03-16 CN CN201780021638.5A patent/CN108886873A/zh active Pending
Also Published As
Publication number | Publication date |
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KR20180128048A (ko) | 2018-11-30 |
CN108886873A (zh) | 2018-11-23 |
WO2017169858A1 (ja) | 2017-10-05 |
JP2017183599A (ja) | 2017-10-05 |
TWI637667B (zh) | 2018-10-01 |
US20190132952A1 (en) | 2019-05-02 |
JP6741456B2 (ja) | 2020-08-19 |
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