TW201523632A - 可獨立定址的記憶體陣列位址空間 - Google Patents
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Abstract
本發明之實例提供用於存取一記憶體陣列位址空間之器件及方法。一種例示性記憶體陣列包括:一第一位址空間,其包括耦合至一第一數目個選擇線及若干感測線之記憶體胞;及一第二位址空間,其包括耦合至一第二數目個選擇線及該若干感測線之記憶體胞。該第一位址空間相對於該第二位址空間可獨立定址。
Description
本發明大體上係關於半導體記憶體裝置及方法,且更特定言之係關於與獨立可定址的記憶體陣列位址空間有關的裝置及方法。
記憶體器件通常提供為電腦或其他電子系統中之內部半導體積體電路。存在許多不同類型的記憶體,包含揮發性記憶體及非揮發性記憶體。揮發性記憶體可需要電力以維持其資料(例如,主機資料、錯誤資料等)且尤其可包含隨機存取記憶體(RAM)、動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、同步動態隨機存取記憶體(SDRAM)及閘流體隨機存取記憶體(TRAM)。非揮發性記憶體可藉由在未供電時保持所儲存之資料而提供永久性資料,且尤其可包含NAND快閃記憶體、NOR快閃記憶體及電阻可變記憶體(諸如相變隨機存取記憶體(PCRAM)、電阻式隨機存取記憶體(RRAM)及磁阻式隨機存取記憶體(MRAM),諸如自旋力矩轉移隨機存取記憶體(STT RAM))。
電子系統通常包含若干處理資源(例如,一或多個處理器),該若干處理資源可擷取及執行指令且將所執行指令之結果儲存至一適合位置。一處理器可包括若干功能單元,諸如像是算術邏輯單元(ALU)電路、浮點單元(FPU)電路及/或一組合邏輯區塊,該等功能單元可用以
藉由對資料(例如,一或多個運算元)執行諸如AND、OR、NOT、NAND、NOR及XOR邏輯運算之邏輯運算而執行指令。例如,功能單元電路(FUC)可用以對運算元執行諸如加法、減法、乘法及/或除法之算術運算。
在將指令提供至FUC以供執行時可涉及一電子系統中之若干組件。指令可由例如像是一控制器及/或主機處理器之一處理資源產生。資料(例如,將對其執行指令之運算元)可儲存於可由FUC存取之一記憶體陣列中。可自該記憶體陣列擷取指令及/或資料且可在FUC開始對資料執行指令之前定序及/或緩衝指令及/或資料。此外,因為可透過FUC以一或多個時脈週期執行不同類型的運算,所以亦可定序及/或緩衝指令及/或資料之中間結果。
在許多例項中,處理資源(例如,處理器及/或相關聯FUC)可在記憶體陣列外部,且可經由處理資源與記憶體陣列之間的一匯流排存取資料(例如,以執行指令)。資料可經由一匯流排自記憶體陣列移動至記憶體陣列外部之暫存器。
100‧‧‧計算系統
110‧‧‧主機
120‧‧‧記憶體器件
130‧‧‧記憶體陣列
131‧‧‧位址空間
132‧‧‧位址空間
140‧‧‧控制電路
142‧‧‧位址電路
144‧‧‧輸入/輸出(I/O)電路
146‧‧‧列解碼器
148‧‧‧寫入電路
150‧‧‧感測電路
153‧‧‧行解碼器
154‧‧‧控制匯流排
156‧‧‧輸入/輸出(I/O)匯流排
202‧‧‧存取器件/電晶體
203‧‧‧儲存元件/電容器
204-0至204-N‧‧‧選擇線
205-1‧‧‧感測線D
205-2‧‧‧感測線D_
206‧‧‧感測放大器
230‧‧‧記憶體陣列
231‧‧‧位址空間
232‧‧‧位址空間
242‧‧‧位址電路
246‧‧‧選擇解碼器/列解碼器
270-0至270-N‧‧‧記憶體胞
303‧‧‧電容器
304-0至304-N‧‧‧選擇線
305-1‧‧‧感測線
305-2‧‧‧感測線
306‧‧‧感測放大器
307-1‧‧‧傳遞電晶體
307-2‧‧‧傳遞電晶體
308-1‧‧‧交叉耦合NMOS電晶體
308-2‧‧‧交叉耦合NMOS電晶體
309-1‧‧‧交叉耦合PMOS電晶體
309-2‧‧‧交叉耦合PMOS電晶體
311-1‧‧‧信號(Passd)
311-2‧‧‧信號(Passdb)
312-1‧‧‧負控制信號(Accumb)
312-2‧‧‧正控制信號(Accum)
313‧‧‧信號(InvD)
314-1‧‧‧反相電晶體
314-2‧‧‧反相電晶體
316-1‧‧‧電晶體
316-2‧‧‧電晶體
317-1‧‧‧共同節點
317-2‧‧‧共同節點
330‧‧‧記憶體陣列
331‧‧‧位址空間
332‧‧‧位址空間
333‧‧‧計算組件
342‧‧‧位址電路
346‧‧‧列解碼器
370-0至370-N‧‧‧記憶體胞
圖1係根據本發明之若干實施例之呈包含一記憶體器件之一計算系統之形式之一裝置之一方塊圖。
圖2圖解說明根據本發明之若干實施例之一記憶體陣列之一部分之一示意圖。
圖3圖解說明根據本發明之若干實施例之耦合至感測電路之一記憶體陣列之一部分之一示意圖。
本發明包含與存取一記憶體陣列位址空間有關的裝置及方法。一例示性記憶體陣列包括:一第一位址空間,其包括耦合至一第一數目個選擇線及若干感測線之記憶體胞;及一第二位址空間,其包括耦
合至一第二數目個選擇線及該若干感測線之記憶體胞。該第一位址空間相對於該第二位址空間可獨立定址。
本發明之若干實施例可減少在一記憶體陣列外部之在執行一邏輯運算期間用以儲存中間結果之暫存器的數目。與由諸如先前PIM系統及具有一外部處理器(例如,定位於一記憶體陣列外部,諸如在一單獨積體電路晶片上之一處理資源)之系統的處理資源存取的暫存器相比,當一處理資源與記憶體陣列胞耦合(例如,整合)時,可改良與存取暫存器相關聯之並行度及/或減低的電力消耗。例如,若干實施例可提供使用來自若干暫存器之資料執行全面完整的計算功能,諸如整數相加、整數相減、整數相乘、整數相除及CAM(內容可定址記憶體)功能,而不經由一匯流排(例如,資料匯流排、位址匯流排、控制匯流排)將資料傳送出記憶體陣列及感測電路。此等計算功能可涉及執行若干邏輯運算(例如,AND、NOT、NOR、NAND、XOR等)。然而,實施例不限於此等實例。在若干實施例中,陣列內之記憶體胞列可用作與執行計算功能相關聯之暫存器。用作暫存器之記憶體胞列可為一位址空間之部分,該位址空間相對於例如包含其他記憶體胞列之一位址空間可獨立定址。
在先前方法中,可(例如,經由包括輸入/輸出(I/O)線之一匯流排)將資料自陣列及感測電路傳送至可供一處理資源(諸如一處理器、微處理器及/或計算引擎)使用之若干暫存器,該處理資源可包括經組態以執行適當邏輯運算之ALU電路及/或其他功能單元電路。然而,經由一匯流排將資料自記憶體傳送至暫存器或自暫存器傳送至記憶體可涉及大量電力消耗及時間需求。即使處理資源與記憶體陣列定位於一相同晶片上,在將資料移出陣列而至計算電路(此可涉及例如執行一感測線位址存取(例如,一行解碼信號之觸發(firing))以將資料自感測線傳送至I/O線上;將該資料移動至陣列周邊;及將該資料提供至
與一計算功能相關聯之一暫存器)時仍可消耗大量電力。
在本發明之以下實施方式中,參考形成本發明之一部分之附圖,且在附圖中以圖解方式展示可如何實踐本發明之一或多項實施例。足夠詳細地描述此等實施例以使一般技術者能夠實踐本發明之實施例,且應瞭解,在不脫離本發明之範疇之情況下,可利用其他實施例且可進行程序、電氣及/或結構改變。如本文中所使用,指定符「N」(尤其關於圖式中之參考符號)指示:可包含如此指定之若干特定特徵。如本文中所使用,「若干」特定事物可指此等事物之一或多者(例如,若干記憶體陣列可指一或多個記憶體陣列)。
本文中之圖遵循一編號慣例,其中首位或前幾位數字對應於圖式圖號且剩餘數字識別圖式中之一元件或組件。可藉由使用類似數字識別不同圖之間的類似元件或組件。例如,130可指圖1中的元件「30」,且一類似元件在圖2中可稱為230。如將明白,可添加、交換及/或消除在本文中之各項實施例中所示之元件以提供本發明之若干額外實施例。此外,如將明白,圖中提供之元件之比例及相對尺度意欲圖解說明本發明之某些實施例,且不應被視為限制意義。
圖1係根據本發明之若干實施例之呈包含一記憶體器件120之一計算系統100之形式之一裝置之一方塊圖。如本文中所使用,一記憶體器件120、一記憶體陣列130及/或感測電路150亦可被單獨視為一「裝置」。
系統100包含耦合至記憶體器件120之一主機110,該記憶體器件120包含一記憶體陣列130。主機110可為一主機系統,諸如一個人膝上型電腦、一桌上型電腦、一數位相機、一行動電話或一記憶卡讀取器,以及各種其他類型的主機。主機110可包含一系統主機板及/或背板且可包含若干處理資源(例如,一或多個處理器、微處理器或某一其他類型的控制電路)。系統100可包含單獨積體電路,或主機110及
記憶體器件120兩者可在相同積體電路上。系統100可為例如一伺服器系統及/或一高效能計算(HPC)系統及/或該高效能計算(HPC)系統之一部分。儘管圖1中所示的實例圖解說明具有一范紐曼(Von Neumann)架構之一系統,然可以非范紐曼架構(例如,一杜林(Turing)機)實施本發明之實施例,該等非范紐曼架構可不包含通常與一范紐曼架構相關聯之一或多個組件(例如,CPU、ALU等)。
為明確起見,已簡化系統100以集中在與本發明特定相關之特徵。記憶體陣列130可為例如DRAM陣列、SRAM陣列、STT RAM陣列、PCRAM陣列、TRAM陣列、RRAM陣列、NAND快閃陣列及/或NOR快閃陣列。陣列130可包括配置成藉由選擇線(在本文中可稱為字線或存取線)耦合之列及藉由感測線(在本文中可稱為數位線或資料線)耦合之行之記憶體胞。儘管圖1中展示一單一陣列130,然實施例並不如此受限。例如,記憶體器件120可包含若干陣列130(例如,若干DRAM胞庫)。結合圖2描述一例示性DRAM陣列。
記憶體器件120包含用以鎖存經由一I/O匯流排156(例如,一資料匯流排)透過I/O電路144提供之位址信號之位址電路142。藉由一列解碼器146及一行解碼器153接收並解碼位址信號以存取記憶體陣列130。在若干實例中,可由更多個或更少個列解碼器解碼位址信號。例如,記憶體器件可包含三個列解碼器。如本文中所使用,一列解碼器可稱為一選擇解碼器。在若干實例中,一列解碼器146可用以解碼對應於記憶體陣列130中之記憶體胞之一位址空間131。在圖1中,位址空間132相對於位址空間131可獨立定址。可藉由使用感測電路150感測感測線上之電壓及/或電流改變而自記憶體陣列130讀取資料。感測電路150可自記憶體陣列130讀取一資料頁(例如,列)並鎖存該資料頁。I/O電路144可用於經由I/O匯流排156與主機110之雙向資料通信。寫入電路148用以將資料寫入至記憶體陣列130。
在若干實施例中,列解碼器146可透過一第一數目個線自位址電路142接收一第一數目個位元。該第一數目個位元可經預解碼以觸發列解碼器146內之一第二數目個線(例如,經預解碼線)。該第二數目個線可耦合至列解碼器146內之若干最終解碼器。該等最終解碼器之各者可連接至該等經預解碼線之一獨有組合。該等最終解碼器之各者可用以啟動位址空間131之列。因而,經由共用位址線解碼位址空間131之列。例如,在列解碼器146處,可透過八個線自位址電路142接收一個八位元位址。該八個位元可經預解碼以啟動二十個經預解碼線。該等最終解碼器之各者可連接至該二十個經預解碼線之一獨有組合以啟動256個列之任一者(例如,第28個列)。執行於在列解碼器146處接收若干位元與啟動若干個列之間的解碼之數目可多於或少於上文實例中所示之數目。例如,可存在比與列解碼器146相關聯之一預解碼及一最終解碼更多及/或更少之預解碼及最終解碼。
在若干實例中,術語解碼可包含在列解碼器146及/或行解碼器153中實行之一預解碼、最終解碼及/或任何其他類型的解碼。在若干實例中,術語預解碼包含:電路實施預解碼程序使得不離散地定址位址。術語預解碼及解碼在本文中可用以區分術語可離散定址的線及/或可個別定址的線。
在若干實例中,與位址空間132相關聯之列係獨立於記憶體陣列130之其他列個別定址及/或解碼。如本文中所使用,一離散位址可為無需解碼以啟動一特定選擇線之一位址。例如,位址電路142可接收與位址空間132相關聯之一位址且可啟動一選擇線而不解碼該位址。在若干實例中,個別定址之列及/或離散定址之列可稱為全解碼列。與位址空間131相關聯之記憶體胞及與位址空間132相關聯之記憶體胞可包括例如以其他方式用於DRAM陣列、SRAM陣列、STT RAM陣列、PCRAM陣列、TRAM陣列、RRAM陣列、NAND快閃陣列及/或
NOR快閃陣列以及其他記憶體組態中之記憶體胞。將結合圖2及圖3詳細敘述位址空間131與位址空間132之間的其他差異。
控制電路140解碼由控制匯流排154自主機110提供之信號。此等信號可包含用以控制對記憶體陣列130執行之操作(包含資料讀取、資料寫入及資料擦除操作)之晶片啟用信號、寫入啟用信號及位址鎖存信號。在各項實施例中,控制電路140負責執行來自主機110之指令。控制電路140可為一狀態機、一定序器或某一其他類型的控制器。
下文結合圖3進一步描述感測電路150之一實例。例如,在若干實施例中,感測電路150可包括若干感測放大器及若干計算組件,該若干計算組件可包括一累加器(例如,圖3中所示之計算組件333)且可用以(例如,對與互補感測線相關聯之資料)執行邏輯運算。在若干實施例中,感測電路(例如,150)可用以使用儲存於陣列130中之資料作為輸入來執行邏輯運算,且可將該等邏輯運算之結果儲存回至陣列130而未經由一感測線位址存取傳送(例如,未觸發一行解碼信號)。對應於位址空間132之列在執行邏輯運算及/或計算功能期間可用作暫時儲存裝置(例如,暫存器)。因而,可使用感測電路150執行而非藉由感測電路外部之處理資源(例如,藉由與主機110相關聯之一處理器及/或定位於器件120上(例如,在控制電路140上或別處)之其他處理電路,諸如ALU電路)執行各種計算功能,及/或除藉由感測電路外部之處理資源執行各種計算功能之外可使用感測電路150執行各種計算功能。
在各種先前方法中,例如與一運算元相關聯之資料將經由感測電路自記憶體讀取並提供至一外部ALU。該外部ALU電路將使用運算元執行計算功能且結果可經由本機I/O線傳送回至陣列。相比之下,在本發明之若干實施例中,感測電路(例如,150)經組態以對儲存於與位址空間131相關聯之記憶體胞及與位址空間132相關聯之記憶體胞
中之資料執行邏輯運算,且將結果儲存回至陣列130而不啟用耦合至該感測電路之一本機I/O線。
因而,在若干實施例中,執行計算功能可不需要陣列130及感測電路150外部之暫存器,此係因為感測電路150可使用陣列130之位址空間131及132執行適當邏輯運算。此外,可在未使用一外部處理資源之情況下執行此等計算功能。因此,位址空間132可用以至少在某種程度上互補及/或取代若干此等外部暫存器。然而,在若干實施例中,可結合陣列130外部及/或記憶體器件120外部之若干暫存器使用陣列130之位址空間132。
圖2圖解說明根據本發明之若干實施例之一記憶體陣列230之一部分之一示意圖。在此實例中,記憶體陣列230係1T1C(一電晶體一電容器)記憶體胞270-0、270-1、270-2、270-3、...、270-N(例如,統稱為記憶體胞270)之一DRAM陣列,各記憶體胞由一存取器件202(例如,電晶體)及一儲存元件203(例如,一電容器)組成。
在若干實施例中,記憶體胞270係破壞性讀取記憶體胞(例如,讀取儲存於胞中之資料會破壞該資料使得最初儲存於該胞中之資料在被讀取之後經再新)。記憶體胞270配置成藉由選擇線204-0(列0)、204-1(列1)、204-2(列2)、204-3(列3)、...、204-N(列N)耦合之列及藉由感測線(例如,數位線)205-1(D)及205-2(D_)耦合之行。在若干實施例中,陣列230可包含耦合至單獨電路之位址空間。例如,如圖2中所示,位址空間231之選擇線204-2、204-3、...、204-N耦合至選擇解碼器246且位址空間232之選擇線204-0及204-1耦合至位址電路242。在若干實例中,位址空間232之選擇線204-0及204-1之至少一者可耦合至獨立於選擇解碼器246之一選擇解碼器。
在此實例中,各胞行與一對互補感測線205-1(D)及205-2(D_)相關聯。儘管圖2中圖解說明僅一單一行之記憶體胞270,然實施例並不
如此受限。例如,一特定陣列可具有若干行之胞及/或感測線(例如,4,096個、8,192個、16,384個等)。在圖2中,記憶體胞270耦合至感測線205-1。一特定胞電晶體202之一閘極耦合至其對應選擇線204-0至204-N(例如,統稱為選擇線204),一第一源極/汲極區域耦合至其對應感測線205-1,且一特定胞電晶體之一第二源極/汲極區域耦合至其對應電容器203。儘管圖2中未圖解說明,然感測線205-2亦可具有耦合至其之記憶體胞。
在圖2中,經由若干共用位址線解碼位址空間231之選擇線204-2至204-N。因而,經由與列解碼器電路(例如,列解碼器246)相關聯之預解碼啟動選擇線204-2至204-N。在若干實施例中,歸因於預解碼程序,在任何給定時間僅可啟動選擇線204-2至204-N之一者(歸因於預解碼約束)。位址空間232之選擇線204-0及204-1直接耦合至位址電路242且可(例如,在未解碼一位址之情況下)由位址電路242離散地啟動。因而,選擇線204-0及204-1可同時啟動且可連同經預解碼選擇線204-2至204-N之一者同時啟動。
在若干實施例中,選擇線204-2至204-N相對於選擇線204-0及204-1可獨立定址,此係因為選擇線204-2至204-N耦合至列解碼器246且選擇線204-0及204-1直接耦合至位址電路242,及/或此係因為選擇線204-2至204-N經由列解碼器246耦合至若干共用位址線且選擇線204-0及204-1可離散定址。在若干實施例中,一第一位址空間(例如,對應於選擇線204-0及204-1之一位址空間)相對於一第二位址空間(例如,對應於選擇線204-2至204-N之一位址空間)可獨立定址,此係因為對應於第一位址空間之若干選擇線耦合至一第一解碼器且對應於第二位址空間之若干選擇線耦合至一第二解碼器。
在若干實施例中,因為第一位址空間及第二位址空間可獨立定址,所以可同時啟動第一位址空間及第二位址空間之選擇線。在其中
一位址空間耦合至共用位址線之若干實施例中,在一給定時間僅可啟動該等選擇線之一者。然而,在此等實施例中,耦合至共用位址線之位址空間之一選擇線可與對應於另一位址空間之一或多個選擇線同時啟動。
在若干實例中,耦合至對應於位址空間232之選擇線之記憶體胞可用作暫存器。即,耦合至位址空間232之各自列之記憶體胞可用作例如與執行邏輯運算相關聯之暫時儲存裝置。作為一實例,記憶體胞270-0及270-1可用作可由一計算組件啟動之暫時儲存裝置,該計算組件耦合至感測放大器206以執行邏輯運算。結合圖3進一步描述使用記憶體胞作為暫存器之實例。
解碼器246可接收對應於解碼器246之一特定選擇線之一位址(例如,來自位址電路242)而作為輸入。解碼器246可經由一預解碼程序解碼該位址並啟動適當的共用位址線以啟動位址空間231之特定選擇線(例如,選擇線204-2至204-N)。在此實例中,解碼器246解碼選擇線204-2至204-N之位址。在若干實例中,可使用更多個或更少個解碼器來解碼與位址空間231相關聯之位址。
在若干實例中,解碼器246可獨立於用以啟動位址空間232之選擇線之一解碼器。在若干實施例中,一主機可對位址空間231進行存取且無法對位址空間232進行存取。例如,一主機可能夠直接存取耦合至位址空間231之選擇線204-2至204-N之記憶體胞270-2至270-N,但可能無法存取耦合至位址空間232之選擇線204-0及204-1之記憶體胞270-0至270-1。
在若干實施例中,且如圖2中所圖解說明,位址空間232之記憶體胞定位於與位址空間231之記憶體胞一間距上。在圖2中,位址空間232之選擇線定位於記憶體陣列230之一邊緣部分處(例如,於凸緣上),然而實施例並不如此受限。在若干實施例中,對應於位址空間
232及/或位址空間231之選擇線可未集合為連續號碼之選擇線。例如,位址空間231之若干選擇線可包含定位於其等之間的位址空間232之若干選擇線。
在若干實施例中,位址空間231及位址空間232可分別與一第一位址區塊及一第二位址區塊相關聯。各位址區塊可包括例如若干位址。連續位址可指按一單一位址自一第一位址數值地增加至一最後位址之位址。一位址區塊可包含該位址區塊之一第一位址與一最後位址之間的全部位址。一位址區塊可分成若干位址子區塊。例如,記憶體陣列230可與一位址區塊相關聯,該位址區塊可包含與位址空間231相關聯之一第一位址子區塊及與位址空間232相關聯之一第二位址子區塊。
一主機可具有直接存取與位址空間232相關聯之位址之一有限能力(例如,位址空間232可無法由一使用者存取)。例如,可使用對一特定位址空間(或其部分)之有限存取以保留該特定位址空間之使用。例如,如結合圖3進一步描述,與位址空間232相關聯之一位址可經保留以用於計算操作。在若干實施例中,未知一位址之一主機可對該位址有限地存取。在若干實施例中,一主機可對位址空間231及位址空間232直接存取。在若干實施例中,一主機可對位址空間231及/或位址空間232之一部分直接存取。例如,一主機可對記憶體胞270-1及列204-1直接存取且無法對記憶體胞270-0及列204-0直接存取。在若干實例中,一主機可對位址空間231直接存取且無法對位址空間232直接存取。
圖3圖解說明根據本發明之若干實施例之耦合至感測電路之一記憶體陣列330之一部分之一示意圖。圖3包含類似於圖2中之記憶體陣列230之記憶體陣列330。
在此實例中,感測電路包括一感測放大器306及一計算組件
333。感測電路可係圖1中所示之感測電路150。感測放大器306耦合至對應於一特定行之記憶體胞之互補感測線D、D_。感測放大器306可經操作以判定儲存於一選定胞(例如,記憶體胞370)中之一狀態(例如,邏輯資料值)。實施例不受限於例示性感測放大器306。例如,根據本文中描述之若干實施例之感測電路可包含電流模式感測放大器及/或單端感測放大器(例如,耦合至一感測線之感測放大器)。
在若干實施例中,一計算組件(例如,333)可包括形成於與感測放大器(例如,306)及/或陣列(例如,330)之記憶體胞370之電晶體的間距上之若干電晶體,該間距可符合一特定特徵大小(例如,4F2、6F2等)。如下文進一步描述,計算組件333可結合感測放大器306一起操作以使用來自陣列330中之記憶體胞370之資料作為輸入來執行各種邏輯運算,並將結果儲存回至陣列330中之記憶體胞370而未經由一感測線位址存取傳送資料(例如,未觸發一行解碼信號,使得資料經由本機I/O線傳送至陣列及感測電路外部之電路)。因而,本發明之若干實施例可使能夠使用少於各種先前方法的電力執行邏輯運算及與邏輯運算相關聯的計算功能。此外,由於若干實施例消除跨本機I/O線傳送資料以執行計算功能之需要,故與先前方法相比,若干實施例可使用一計算組件(例如,333)及記憶體胞370實現增加的並行處理能力。
在圖3中所圖解說明之實例中,對應於計算組件333之電路包括耦合至感測線D及D_之各者之五個電晶體;然而,實施例不限於此實例。電晶體307-1及307-2具有分別耦合至感測線D及D_之一第一源極/汲極區域,及耦合至一交叉耦合鎖存器(例如,耦合至一對交叉耦合電晶體(諸如交叉耦合NMOS電晶體308-1及308-2以及交叉耦合PMOS電晶體309-1及309-2)之閘極)之一第二源極/汲極區域。如本文中進一步描述,包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器可稱為次要鎖存器(對應於感測放大器306之交叉耦合鎖存器在本文中
可稱為主要鎖存器)。
電晶體307-1及307-2可稱為傳遞電晶體,其等可經由各自信號311-1(Passd)及311-2(Passdb)啟用以將各自感測線D及D_上之電壓或電流傳遞至包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器之輸入端(例如,次要鎖存器之輸入端)。在此實例中,電晶體307-1之第二源極/汲極區域耦合至電晶體308-1及309-1之一第一源極/汲極區域以及電晶體308-2及309-2之閘極。類似地,電晶體307-2之第二源極/汲極區域耦合至電晶體308-2及309-2之一第一源極/汲極區域以及電晶體308-1及309-1之閘極。
電晶體308-1及308-2之一第二源極/汲極區域共同耦合至一負控制信號312-1(Accumb)。電晶體309-1及309-2之一第二源極/汲極區域共同耦合至一正控制信號312-2(Accum)。Accum信號312-2可係一供應電壓(例如,Vcc)且Accumb信號可係一參考電壓(例如,接地)。啟用信號312-1及312-2啟動對應於次要鎖存器之包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器。經啟動感測放大器對進行操作以放大共同節點317-1與共同節點317-2之間的一差動電壓,使得將節點317-1驅動至Accum信號電壓及Accumb信號電壓之一者(例如,至Vcc及接地之一者),且將節點317-2驅動至Accum信號電壓及Accumb信號電壓之另一者。如下文進一步描述,信號312-1及312-2標記為「Accum」及「Accumb」,此係因為次要鎖存器在用以執行一邏輯運算時可用作一累加器。在若干實施例中,一累加器包括形成次要鎖存器之交叉耦合電晶體308-1、308-2、309-1及309-2以及傳遞電晶體307-1及307-2。如本文中進一步描述,在若干實施例中,包括耦合至一感測放大器之一累加器之一計算組件可經組態以執行一邏輯運算,該邏輯運算包括對藉由一對互補感測線之至少一者上之一信號(例如,電壓或電流)表示之一資料值執行一累加運算。
計算組件333亦包含反相電晶體314-1及314-2,其等具有耦合至各自數位線D及D_之一第一源極/汲極區域。電晶體314-1及314-2之一第二源極/汲極區域分別耦合至電晶體316-1及316-2之一第一源極/汲極區域。電晶體314-1及314-2之閘極耦合至一信號313(InvD)。電晶體316-1之閘極耦合至共同節點317-1,電晶體308-2之閘極、電晶體309-2之閘極及電晶體308-1之第一源極/汲極區域亦耦合至該共同節點317-1。以一互補方式,電晶體316-2之閘極耦合至共同節點317-2,電晶體308-1之閘極、電晶體309-1之閘極及電晶體308-2之第一源極/汲極區域亦耦合至該共同節點317-2。因而,啟用信號InvD用以使儲存於次要鎖存器中之資料值反相並將該反相值驅動至感測線305-1及305-2上。
在圖3中,計算組件333經組態以執行一AND、NAND及/或一NOT(例如,反相)運算。以下實例將證實可如何使用儲存於陣列330中之資料(例如,與位址空間331及位址空間332相關聯之資料)作為輸入來執行一3輸入NAND運算及可如何經由感測電路(例如,感測放大器306及計算組件333)之操作將NAND運算之結果儲存於陣列中。該實例涉及將儲存於耦合至選擇線304-0至304-N且共同耦合至感測線305-1之記憶體胞370中之資料值(例如,邏輯1或邏輯0)使用為一NAND運算之各自輸入。NAND運算之結果可儲存於選擇線304-0至304-N之至少一者之記憶體胞中。
作為一實例,列304-1之記憶體胞(例如,胞370-1)可用作計算組件333之一暫存器。例如,計算組件333可使用儲存於位址空間331之一列中之資料作為輸入,且可將一計算功能之一中間結果保存在位址空間332之一列中。在此實例中,可將計算功能之一結果儲存回至位址空間331之一列及/或位址空間332之一列。在若干實施例中,可將一計算功能之結果同時儲存至位址空間332之一或多個列及位址空間
331之一列。
使用位址空間332之記憶體胞進行暫時儲存可防止使用位址空間331之記憶體胞進行暫時儲存之需要,此可增加可存取記憶體之量。例如,若一計算組件333使用位址空間331之記憶體胞作為暫時儲存裝置,則位址空間331之該等胞無法用於儲存其他資料,此可抑制位址空間331之使用(例如,藉由一主機)。例如,使用位址空間331作為暫時儲存裝置可限制可用於一主機之位址空間之一總量。相比之下,結合本文中描述之實施例,使用位址空間332作為暫時儲存裝置(例如)容許計算組件333執行若干邏輯運算而不限制一主機使用位址空間331之能力。
下文描述其中位址空間332可用作暫存器之一邏輯運算之一實例。例如,3輸入NAND運算之一第一運算階段可包含:使用感測放大器306對列0之記憶體胞(例如,胞370-0)執行一感測操作以判定所儲存之一資料值,該資料值可用作NAND運算之一第一輸入。該感測操作涉及啟動列0(例如,經由位址電路342)且導致對應於一邏輯1之一電壓(例如,Vcc)或對應於一邏輯0之一電壓(例如,接地)在感測線D上(且另一電壓在互補感測線D_上),使得將所感測之資料值儲存於對應於感測放大器306之主要鎖存器中。在感測列0記憶體胞370-0之後,啟用Passd信號311-1及Passdb信號311-2且啟用Accumb信號312-1及Accum信號312-2,此導致將儲存於列0記憶體胞370-0中之經感測資料值複製至對應於計算組件333之次要鎖存器。接著停用Passd信號及Passdb信號;然而,保持啟用Accum信號及Accumb信號(在第二、第三及第四運算階段期間,如下文描述)。接著停用列0且發生平衡。平衡可涉及在一平衡電壓(例如,其可係Vcc/2)使互補感測線D及D_一起短路。平衡可發生於例如一記憶體胞感測操作之前。
3輸入NAND運算之一第二階段包含:使用感測放大器306對列1
記憶體胞(例如,370-1)執行一感測操作以判定其儲存之資料值,該資料值用作NAND運算之一第二輸入。因而,由位址電路342啟用列1且將感測線D及D_各自驅動至Vcc及接地之一不同者。在此實例中,感測線D上之一Vcc電壓對應於儲存於記憶體胞370-1中之一邏輯1且感測線D_上之一接地電壓對應於一邏輯0;然而,實施例不限於此實例。在感測列1記憶體胞370-1之後,啟用Passd信號311-1而保持停用Passdb信號311-2(例如,僅啟用Passd)。撤回(recall)保持啟用Accumb信號312-1及Accum信號312-2。若儲存於列1記憶體胞370-1中之資料值係一邏輯0,則確證與次要鎖存器相關聯之累加值係低的,使得次要鎖存器儲存邏輯0。若儲存於列1記憶體胞370-1中之資料值並非一邏輯0,則次要鎖存器保持其儲存之列0資料值(例如,一邏輯1或一邏輯0)。因而,在此實例中,次要鎖存器用作零(0)累加器。接著停用Passd信號,停用列1,且發生平衡。
3輸入NAND運算之一第三階段包含:使用感測放大器306對列2記憶體胞(例如,370-2)執行一感測操作以判定其儲存之資料值,該資料值用作NAND運算之一第三輸入。因而,由列解碼器346啟用列2且將感測線D及D_各自驅動至Vcc及接地之一不同者。在感測列2記憶體胞370-2之後,啟用Passd信號311-1而保持停用Passdb信號311-2(例如,僅啟用Passd)。撤回保持啟用Accumb信號312-1及Accum信號312-2。若儲存於列2記憶體胞370-2中之資料值係一邏輯0,則確證與次要鎖存器相關聯之累加值係低的,使得次要鎖存器儲存邏輯0。若儲存於列2記憶體胞370-2中之資料值並非一邏輯0,則次要鎖存器保存其先前儲存之值(例如,其儲存之值)。因而,儲存於次要鎖存器中之值(例如,累加器之輸出)係儲存於各自的列0記憶體胞370-0、列1記憶體胞370-1及列2記憶體胞370-2中之資料值之AND。接著停用Passd信號,停用列2,且發生平衡。
3輸入NAND運算之第四階段包含:停用平衡使得感測線D及D_浮動。接著啟用InvD信號313,此導致儲存於次要鎖存器中之資料值之一反相(例如,使累加輸出反相)。因而,若記憶體胞370-0、370-1及370-2之任一者儲存一邏輯0(例如,若NAND運算之三個輸入之任一者係邏輯0),則感測線D_將載送對應於邏輯0之一電壓(例如,接地電壓)且感測線D將載送對應於邏輯1之一電壓(例如,Vcc)。若記憶體胞370-0、370-1及370-2之全部者儲存一邏輯1(例如,若NAND運算之三個輸入之全部者皆係邏輯1),則感測線D_將載送對應於邏輯1之一電壓且感測線D將載送對應於邏輯0之一電壓。接著啟用感測放大器306之主要鎖存器且感測線D現含有來自列0至列2記憶體胞370-0、370-1及370-2之各自輸入資料值之經反及(NANDed)結果。因而,若列0至列2記憶體胞之任一者儲存一邏輯0,則感測線D將處於Vcc,且若列0至列2記憶體胞之全部者儲存一邏輯1,則感測線D將處於接地。接著,可將NAND運算之結果儲存回至與位址空間332相關聯之一記憶體胞。在若干實例中,可將NAND運算之結果儲存回至與位址空間331(例如,經由共用位址線解碼之一位址空間)相關聯之一記憶體胞。在此實例中,可將NAND運算之結果儲存至列1記憶體胞370-1。將NAND運算之結果儲存至列1記憶體胞370-1涉及經由位址電路342啟動列1。列1記憶體胞370-1之電容器303將被驅動至對應於感測線D上之資料值(例如,邏輯1或邏輯0)之一電壓,此本質上覆寫先前儲存於列1記憶體胞370-1中之任何資料值。例如,當邏輯運算(例如,NAND)之結果係與一更複雜運算相關聯之中間結果時,將該邏輯運算之結果保存至一暫存器中可係有益的。例如,保存在列1記憶體胞370-1中之結果可用作一後續邏輯運算中之輸入。實施例並不如此受限。
在若干實施例中,可將一邏輯運算之結果寫入至與位址空間331
相關聯之一記憶體胞。例如,可將結果儲存回至列204-2至204-N之記憶體胞。在若干實施例中,邏輯運算之結果可未儲存回至陣列(例如,至位址空間331或位址空間332之胞)。例如,在執行邏輯運算之後,可將結果自一累加器(例如,計算組件333之累加器)傳送至一外部器件(例如,經由本機I/O線耦合至感測放大器之一外部主機)。
再者,一般技術者將明白,執行NAND邏輯運算之能力可使能夠執行更複雜計算功能,諸如加法、減法及乘法以及其他主要數學功能及/或圖案比較功能。例如,一系列NAND運算可經組合以執行一全加器功能。作為一實例,若一全加器需要12個NAND閘極以添加兩個資料值連同一進位輸入及進位輸出,則可執行總計384個NAND運算(12 x 32)以添加兩個32位元數字。本發明之實施例亦可用以執行可係非布林(boolean)(例如,複製、比較等)及/或與一NAND運算相比可更複雜或較不複雜之邏輯運算。
在若干實例中,可將儲存於對應於位址空間331之一列之一記憶體胞中之一資料值複製至對應於位址空間332之一列之一記憶體胞。例如,將儲存於記憶體胞370-3中之資料值複製至一記憶體胞370-1可包含將該資料值自記憶體胞370-3複製至感測放大器306。接著,可藉由啟動選擇線204-1而將該資料值自感測放大器306複製至記憶體胞370-1。
在未啟動一I/O電路之情況下,可執行將一資料值自感測放大器306複製至記憶體胞370-1。將資料值自感測放大器306複製至一記憶體胞而不啟動I/O電路可節省時間及資源,此係因為未啟動I/O電路,且與啟動I/O電路之條件下相比,可更快執行複製。
作為另一實例,可將一資料值自位址空間331之記憶體胞370-3同時複製至位址空間332之記憶體胞370-0及370-1。例如,可將資料值自記憶體胞370-3複製至感測放大器306,且將該資料值自感測放大器
306同時複製至記憶體胞370-0及記憶體胞370-1。位址電路342可同時啟動記憶體胞370-0及370-1,此係因為與位址空間332相關聯之記憶體胞係離散地定址。相比之下,由於經由共用位址線解碼對應於位址空間331之列,故一次可將資料自感測放大器306複製至列304-2至304-N之僅一者。
在若干實施例中,可將一資料值自位址空間331之一列複製至位址空間331之一不同列及位址空間332之一列。例如,可將一資料值自記憶體胞370-3複製至感測放大器306,且將該資料值自感測放大器306同時複製至記憶體胞370-1及370-2。可將資料自記憶體胞370-3同時複製至記憶體胞370-1及370-2,此係因為由列解碼器346解碼與記憶體胞370-2相關聯之位址(例如,經由預解碼)且因為與記憶體胞370-1相關聯之位址係離散地定址。即,列解碼器346可與位址電路342可啟動選擇線304-1同時啟動選擇線304-2。
在若干實施例中,可將一資料值自位址空間332之一列複製至位址空間331之一列。例如,可將一資料值自記憶體胞370-1複製至感測放大器306及自感測放大器306複製至記憶體胞370-3。作為另一實例,可將一資料值自位址空間332之一列複製至位址空間332之若干列。例如,可將資料值自記憶體胞370-0複製至感測放大器306及自感測放大器306複製至與位址空間332相關聯之至少兩個不同記憶體胞。在若干實例中,可將一資料值自位址空間332之一列複製至位址空間332之相同列及/或位址空間332之若干不同列。可將一資料值自位址空間332之一列同時複製至位址空間332之一不同列及位址空間331之一列。
在若干實施例中,可在一單一感測循環中執行上述之複製(例如,而無需額外陣列平衡、列啟動及/或位元線之重新感測)。例如,在一單一感測循環內將一資料值自位址空間331之一列複製至位址空
間332之一列可包含感測位址空間331之該列。與在自位址空間331之該列感測資料值時所執行相比,可執行複製而無需位址空間331之該列之額外感測且無需額外平衡。此外,可執行複製而無需額外列存取。例如,可藉由啟動(例如,觸發)位址空間332之選擇列而將自位址空間331之一列感測之資料值複製至位址空間332之一或多個列,但不重新感測對應於選定胞之位元線。具有以下能力可藉由減小執行複製所需之感測循環之數目而提供優於先前方法之一顯著效能:在一單一感測循環內將一資料值自位址空間331之一列複製至位址空間332之若干列;將一資料值自位址空間332之一列複製至位址空間331之一列;及/或將一資料值自位址空間332之一位址複製至位址空間331之若干位址。
本發明之實施例不限於圖3中所圖解說明之特定感測電路組態。例如,不同計算組件電路可用以執行根據本文中描述之若干實施例之邏輯運算。儘管圖3中未圖解說明,然在若干實施例中,控制電路可耦合至陣列330、感測放大器306及/或計算組件333。此控制電路可例如在與陣列及感測電路相同之一晶片上及/或一外部處理資源(諸如一外部處理器)上實施,且可控制對應於陣列及感測電路之各種信號之啟用/停用以執行如本文中描述之邏輯運算。
總結
本發明包含用於存取一記憶體陣列位址空間之器件及方法。一例示性記憶體陣列包括:一第一位址空間,其包括耦合至一第一數目個選擇線及若干感測線之記憶體胞;及一第二位址空間,其包括耦合至一第二數目個選擇線及該若干感測線之記憶體胞。經由若干共用選擇線解碼該第一數目個選擇線。該第一位址空間相對於該第二位址空間可獨立定址。
儘管本文中已圖解說明並描述特定實施例,然一般技術者將明
白,經計算以達成相同結果之一配置可替代所示之特定實施例。本發明意欲於涵蓋本發明之一或多項實施例之調適或變動。應瞭解,已以一闡釋性方式而非一限制性方式進行上文描述。熟習此項技術者在檢閱上文描述之後將明白上文實施例與本文中未具體描述之其他實施例之組合。本發明之一或多項實施例之範疇包含其中使用上文結構及方法之其他應用。因此,應參考隨附申請專利範圍以及此等申請專利範圍所授權之等效物之全部範圍來判定本發明之一或多項實施例之範疇。
在前述實施方式中,為簡化本發明之目的,將一些特徵集合於一單一實施例中。本發明之此方法不應被解釋為反映本發明所揭示之實施例必須使用比明確陳述於各技術方案中更多之特徵之一意圖。實情係,如以下申請專利範圍反映,本發明標的在於少於所揭示之一單一實施例之全部特徵。因此,特此將以下申請專利範圍併入實施方式中,其中各技術方案獨立地作為一單獨實施例。
303‧‧‧電容器
304-0‧‧‧選擇線
304-1至304-N‧‧‧選擇線
305-1‧‧‧感測線
305-2‧‧‧感測線
306‧‧‧感測放大器
307-1‧‧‧傳遞電晶體
307-2‧‧‧傳遞電晶體
308-1‧‧‧交叉耦合NMOS電晶體
308-2‧‧‧交叉耦合NMOS電晶體
309-1‧‧‧交叉耦合PMOS電晶體
309-2‧‧‧交叉耦合PMOS電晶體
311-1‧‧‧信號(Passd)
311-2‧‧‧信號(Passdb)
312-1‧‧‧負控制信號(Accumb)
312-2‧‧‧正控制信號(Accum)
313‧‧‧信號(InvD)
314-1‧‧‧反相電晶體
314-2‧‧‧反相電晶體
316-1‧‧‧電晶體
316-2‧‧‧電晶體
317-1‧‧‧共同節點
317-2‧‧‧共同節點
330‧‧‧記憶體陣列
331‧‧‧位址空間
332‧‧‧位址空間
333‧‧‧計算組件
370-0至370-N‧‧‧記憶體胞
Claims (24)
- 一種記憶體陣列,其包括:一第一位址空間,其包括耦合至一第一數目個選擇線及若干感測線之記憶體胞;及一第二位址空間,其包括耦合至一第二數目個選擇線及該若干感測線之記憶體胞;其中該第一位址空間相對於該第二位址空間可獨立定址。
- 如請求項1之記憶體陣列,其中在一給定時間僅啟動該第一數目個選擇線之一者且其中同時啟動該第二數目個選擇線。
- 如請求項2之記憶體陣列,其中同時啟動該第一數目個選擇線之一選擇線及該第二數目個選擇線之至少一者。
- 如請求項1至3中任一項之記憶體陣列,其中該第一位址空間相對於該第二位址空間可獨立定址包括:該第一數目個選擇線耦合至一解碼器及該第二數目個選擇線直接耦合至位址電路。
- 如請求項1至3中任一項之記憶體陣列,其中該第一位址空間相對於該第二位址空間可獨立定址包括:該第一數目個選擇線耦合至一第一解碼器及該第二數目個選擇線耦合至一第二解碼器。
- 如請求項5之記憶體陣列,其中該第一解碼器及該第二解碼器耦合至共用位址電路。
- 如請求項1至3中任一項之記憶體陣列,其中該第一位址空間相對於該第二位址空間可獨立定址包括:該第一數目個選擇線經由一解碼器耦合至若干共用位址線且該第二數目個選擇線可離散定址。
- 如請求項1之記憶體陣列,其中獨立定址該第二數目個選擇線之 各者。
- 如請求項1至3中任一項之記憶體陣列,其中包括該第一位址空間之該等記憶體胞透過該若干感測線耦合至包括該第二位址空間之該等記憶體胞。
- 如請求項1至3中任一項之記憶體陣列,其中獨立於該第二數目個選擇線解碼該第一數目個選擇線。
- 一種方法,其包括:啟動一記憶體陣列之一第一數目個選擇線的一選擇線;經由耦合至該記憶體陣列之感測線的感測電路來感測儲存於耦合至該選擇線之一第一數目個記憶體胞中之資料;及將儲存於該第一數目個記憶體胞中之該資料複製至一第二數目個記憶體胞,該第一數目個記憶體胞耦合至該第一數目個選擇線之該選擇線,該第二數目個記憶體胞耦合至該記憶體陣列之一第二數目個選擇線之一選擇線;其中該第一數目個選擇線相對於該第二數目個選擇線可獨立定址。
- 如請求項11之方法,其中複製儲存於該第一數目個記憶體胞中之該資料包括:將該資料自該感測電路複製至該第二數目個記憶體胞而不存取一輸入/輸出(I/O)線。
- 如請求項12之方法,其中將該資料自該感測電路複製至該第二數目個記憶體胞進一步包含將該資料自該感測電路複製至一第三數目個記憶體胞,該第三數目個記憶體胞耦合至該第一數目個選擇線之另一選擇線。
- 如請求項13之方法,其中同時發生將該資料自該感測電路複製至該第二數目個記憶體胞及將該資料自該感測電路複製至該第三數目個記憶體胞。
- 如請求項11至14中任一項之方法,其中啟動該第一數目個選擇線之該選擇線包含:經由解碼電路啟動該選擇線,該解碼電路獨立於與啟動該第二數目個選擇線之該選擇線相關聯之解碼電路。
- 一種方法,其包括:啟動一記憶體陣列之一第一數目個選擇線之一選擇線,其中耦合至該第一數目個選擇線之記憶體胞由一計算組件用作暫時儲存裝置;經由耦合至該記憶體陣列之感測線的感測電路來感測儲存於一第一數目個記憶體胞中之資料,該第一數目個記憶體胞耦合至該第一數目個選擇線之該選擇線;及將儲存於該第一數目個記憶體胞中之該資料複製至一第二數目個記憶體胞,該第二數目個記憶體胞耦合至該記憶體陣列之一第二數目個選擇線的一選擇線;其中該第一數目個選擇線相對於該第二數目個選擇線可獨立定址。
- 如請求項16之方法,其中複製儲存於該第一數目個記憶體胞中之該資料包含:將該資料自用作暫時儲存裝置之該第一數目個記憶體胞複製至該感測電路。
- 如請求項17之方法,其中複製儲存於該第一數目個記憶體胞中之該資料包含:將該資料自該感測電路複製至該第二數目個記憶體胞而不存取一輸入/輸出(I/O)線。
- 如請求項17之方法,其中複製儲存於該第一數目個記憶體胞中之該資料包含:將該資料自該感測電路同時複製至一第三數目個記憶體胞及該第一數目個記憶體胞,該第三數目個記憶體胞耦合至該第一數目個選擇線之另一選擇線,該第一數目個記憶 體胞耦合至該第一數目個選擇線之該選擇線。
- 如請求項16至19中任一項之方法,其中複製儲存於該第一數目個記憶體胞中之該資料包含:在一單一感測循環內進行複製。
- 一種裝置,其包括:一記憶體陣列之一第一位址空間,其包括耦合至一第一數目個選擇線及若干感測線之一第一數目個記憶體胞;該記憶體陣列之一第二位址空間,其包括耦合至一第二數目個選擇線及該若干感測線之一第二數目個記憶體胞,其中該第二位址空間相對於該第一位址空間可獨立定址;及感測電路,其經組態以:至少接收與該第一位址空間相關聯之一第一資料值及與該第二位址空間相關聯之一第二資料值;及使用該第一資料值作為一第一輸入且使用該第二資料值作為一第二輸入來執行一邏輯運算。
- 如請求項21之裝置,其中該第一位址空間與一第一位址區塊相關聯且一第二位址空間與一第二位址區塊相關聯,且其中該第一位址區塊與該第二位址區塊分離。
- 如請求項22之裝置,其進一步包括該感測電路外部之一處理資源,該處理資源對該第一位址空間及該第二位址空間之至少一部分進行存取。
- 如請求項21至23中任一項之裝置,其中該感測電路經組態以執行該邏輯運算而不經由一感測線位址存取來傳送資料。
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CN105612582B (zh) | 2018-08-28 |
EP3039685B1 (en) | 2019-06-05 |
US20150063052A1 (en) | 2015-03-05 |
EP3039685A1 (en) | 2016-07-06 |
EP3039685A4 (en) | 2017-05-31 |
US9530475B2 (en) | 2016-12-27 |
KR20160039687A (ko) | 2016-04-11 |
WO2015031051A1 (en) | 2015-03-05 |
JP5989281B1 (ja) | 2016-09-07 |
US20160005447A1 (en) | 2016-01-07 |
US9153305B2 (en) | 2015-10-06 |
TWI539469B (zh) | 2016-06-21 |
CN105612582A (zh) | 2016-05-25 |
JP2016535916A (ja) | 2016-11-17 |
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