TW201438167A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201438167A
TW201438167A TW103101421A TW103101421A TW201438167A TW 201438167 A TW201438167 A TW 201438167A TW 103101421 A TW103101421 A TW 103101421A TW 103101421 A TW103101421 A TW 103101421A TW 201438167 A TW201438167 A TW 201438167A
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metal
semiconductor device
film
bonding pad
plunger
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TW103101421A
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TWI604581B (zh
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Sukehiro Yamamoto
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Seiko Instr Inc
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Abstract

[課題]防止接合墊下的層間絕緣膜，產生衝擊所致之裂痕。[解決手段]在第一金屬膜(12)與最上層之第二金屬膜(15)之間，配置小徑金屬栓塞(14a)與大徑金屬栓塞(14b)，作為大徑金屬栓塞(14b)上方的第二金屬膜(15)表面設置凹部(17)的接合墊。

Description

半導體裝置
本發明係關於具有接合墊的半導體裝置。
針對具有接合墊之先前的半導體裝置進行說明。圖13係揭示先前的半導體裝置的剖面圖。
觀察接合墊附近的剖面時，第一金屬膜132係設置在層間絕緣膜131上，層間絕緣膜133以覆蓋第一金屬膜132之方式設置。藉由已知的光微影及蝕刻或CMP技術，金屬柱塞134係形成並配置於第一金屬膜132上。第二金屬膜135係透過金屬柱塞134而與第一金屬膜132連接，且設置在第一金屬膜132的上方。保護膜136係在第二金屬膜135上具有開口部。又，保護膜136係除了保護膜136的開口部之外，覆蓋第二金屬膜135。
在此，金屬柱塞134使用埋入鎢的柱塞，金屬柱塞的直徑係以接近處理原則上可形成之最小徑的尺寸來統一，第二金屬膜135的表面係為平坦。(例如參照專利文獻1)
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2004-221430號公報
然而，先前的技術中，因為用以形成探針200或焊球300的引線接合的衝擊所發生之應力，第二金屬膜135及第一金屬膜132產生歪曲時，應力集中於接合墊的下方向，有層間絕緣膜133會產生裂痕137的危險性。
本發明係有鑑於前述課題所發明者，目的為提供可有效防止接合墊下的絕緣膜產生裂痕的半導體裝置。
本發明為了解決前述課題，使用以下的手段。
首先，作為一種半導體裝置，係具有接合墊的半導體裝置，其特徵為：具備：第一層間絕緣膜上的第一金屬膜；前述第一金屬膜上的第二層間絕緣膜；金屬柱塞，係以貫通前述第二層間絕緣膜之方式形成；及第二金屬膜，係在前述第二層間絕緣膜上，隔著前述金屬柱塞電性連接所設置者；前述金屬插頭，係由大徑的第一金屬柱塞與小徑的第二金屬柱塞所成，並於前述第一金屬柱塞正上的前述第二金屬膜的表面，形成凹部。
又，作為一種半導體裝置，其特徵為：前述第一金屬柱塞，係由高熔點金屬膜與前述第二金屬膜所成；第二金屬柱塞，係僅由高熔點金屬膜所成；前述第二金屬柱塞正上的前述第二金屬膜的表面係為平坦。
又，作為一種半導體裝置，其特徵為：前述第二金屬柱塞被配置於前述接合墊區域外。
又，作為一種半導體裝置，其特徵為：前述第二金屬柱塞被配置於前述接合墊區域內。
又，作為一種半導體裝置，其特徵為：前述第一金屬柱塞與前述第二金屬柱塞，係在前述接合墊區域內交互配置。
又，作為一種半導體裝置，其特徵為：前述金屬柱塞，係被配置成同心圓狀。
又，作為一種半導體裝置，其特徵為：前述金屬柱塞，係除了接合墊的角部方向，被配置成同心圓狀。
又，作為一種半導體裝置，其特徵為：前述金屬柱塞，係被配置成螺旋狀。
又，作為一種半導體裝置，其特徵為：前述金屬柱塞，係以圓形配置於前述接合墊的中央部，進而，於其外側，被配置成螺旋狀。
然後，作為一種半導體裝置，其特徵為：前述金屬柱塞，係集合複數金屬柱塞且設為台形的區域者沿著接合墊的4邊，配置4個。
藉由使用前述手段，被施加於接合墊表面的應力因為往第二金屬膜的凹部之移動而被分散，藉此，可防止接合墊下的絕緣膜產生裂痕。
11‧‧‧第一層間絕緣膜
12‧‧‧第一金屬膜
13‧‧‧第二層間絕緣膜
14a‧‧‧大徑金屬栓塞
14b‧‧‧小徑金屬栓塞
15‧‧‧第二金屬膜
16‧‧‧保護膜
17‧‧‧凹部
18‧‧‧接合墊(開口區域)
131‧‧‧第一層間絕緣膜
133‧‧‧第二層間絕緣膜
132‧‧‧第一金屬膜
134‧‧‧小徑金屬栓塞
135‧‧‧第二金屬膜
136‧‧‧保護膜
137‧‧‧裂痕
200‧‧‧探針
300‧‧‧焊球
[圖1]揭示本發明之半導體裝置的俯視圖與剖面圖。
[圖2]本發明之半導體裝置的探針測試工程、引線接合工程的剖面圖。
[圖3]揭示本發明之半導體裝置的俯視圖。
[圖4]揭示本發明之半導體裝置的俯視圖。
[圖5]揭示本發明之半導體裝置的俯視圖。
[圖6]揭示本發明之半導體裝置的俯視圖。
[圖7]揭示本發明之半導體裝置的俯視圖。
[圖8]揭示本發明之半導體裝置的俯視圖。
[圖9]揭示本發明之半導體裝置的俯視圖。
[圖10]揭示本發明之半導體裝置的俯視圖。
[圖11]揭示本發明之半導體裝置的俯視圖。
[圖12]揭示本發明之半導體裝置的俯視圖。
[圖13]先前之半導體裝置的探針測試工程、引線接合工程的剖面圖。
以下，參照圖面來說明本發明的實施形態。
首先，針對具有接合墊之半導體裝置的基本構造，來進行說明。圖1係揭示本發明之半導體裝置的俯視圖與剖面圖。
圖1(a)係接合墊的俯視圖。於保護膜16開口的區域，露出矩形的第二金屬膜15，於其背面，小徑金屬栓塞14a與剖面直徑大於其之大徑金屬栓塞14b以交互佔據如圍棋棋盤的眼之正方格子的交點之方式配置。再者，小徑金屬栓塞14a的直徑係接近處理原則上可形成之最小徑的尺寸。再者，接合墊區域外係僅以小徑金屬栓塞14a，讓與第二金屬膜15同層的金屬配線和下層的金屬配線被電性連接。
圖1(b)係接合墊的剖面圖。在設置於半導體基板上的第一層間絕緣膜11上，設置有矩形的第一金屬膜12，並以覆蓋第一金屬膜12之方式設置第二層間絕緣膜13，於第一金屬膜12上的第二層間絕緣膜13，設置有到達第一金屬膜12的通孔。通孔混合存在有大徑通孔與小徑通孔的兩種類，於小徑通孔，形成填充由高熔點金屬所成之阻障金屬膜與鎢膜的小徑金屬栓塞14a，於大徑通孔，形成填充阻障金屬膜與鎢膜與第二金屬膜15的大徑金屬栓塞14b。於第一金屬膜12的上方，隔著第二層間絕緣膜13，設置有第二金屬膜15，第一金屬膜12與第二金屬膜15係透過大徑金屬栓塞14a與小徑金屬栓塞14b電性連接。
由圖可知，第二金屬膜15的下面並不平坦，以第二 金屬膜15進入大徑通孔的中心的陷落部之方式成膜，故第二金屬膜15表面也不平坦，成為大徑通孔的上方，亦即大徑金屬栓塞14b的上方具有凹部17的形狀。然後，以覆蓋第二金屬膜15的端面及側面之方式設置保護膜16，去除第二金屬膜15的端面以外的保護膜16，成為具有開口區域18的構造。
在此，針對第一金屬膜成膜之後的製造方法進行說明。於第二層間絕緣膜13，使用光微影技術與蝕刻技術來形成大徑通孔與小徑通孔之後，利用PVD法，成膜鈦系阻障金屬膜，接下來，利用CVD法來成膜鎢膜。此時，鎢膜係以完全填充小徑通孔，部分填充大徑通孔之程度的膜厚來成膜。利用使小徑通孔的直徑小於阻障金屬膜的膜厚與鎢膜的膜厚之和的兩倍，使大徑通孔的直徑大於阻障金屬膜的膜厚與鎢膜的膜厚之和的兩倍，可進行如前述之完全填充、部分填充的成膜。
接下來，利用回蝕法或CMP法來去除第二層間絕緣膜13上的鎢膜。利用回蝕法或CMP法，去除鎢膜之後，即便任一的方法，小徑通孔都會被阻障金屬膜與鎢膜完全填充，大徑通孔會被部分填充，於大徑通孔的中心部會存在空孔。在此種狀態下，利用PVD法來成膜第二金屬膜15的話，第二金屬膜15會進入至大徑通孔內，於其表面形成凹部。接下來，於第二金屬膜15與第二層間絕緣膜13的表面，形成由氮化矽等所成之保護膜16，讓第二金屬膜15的一部分開口，形成接合墊(開口區域)18。
又，圖1(b)係利用回蝕法時的形狀，於大徑通孔的內壁，形成鎢的側壁，於其側壁中填充第二金屬膜15。第二金屬膜15的底面係與第一金屬膜12的上面直接接觸的構造。CMP法之狀況係因為不去除大徑通孔內的鎢膜，第二金屬膜15與第一金屬膜12係隔著鎢膜與阻障金屬膜而電性連接的構造。利用設為此種接合墊構造，接合墊正下方的半導體元件可不受到損害。
接著，針對對於本發明的半導體裝置，進行探針測試或引線接合時之應力的分散來進行說明。
圖2(a)係圖示於本發明的半導體裝置，探針200接觸第二金屬膜15之狀態者。探針200係為了提升與接合墊的電性連接而施加某種程度的加重，雖然滑動於第二金屬膜15的表面，但在本發明的半導體裝置中，於表面有凹部，探針200的前端嵌入於此凹部而停止。施加於該區域的應力係傳導至正下方的大徑金屬栓塞14b，分散於第一金屬膜12。所以，可防止過度的應力施加於第二層間絕緣膜13，產生裂痕。
圖2(b)係圖示本發明的半導體裝置接合焊球300之狀態者。於引線接合工程中，形成於金屬線的前端之金屬焊球壓附於第二金屬膜15時，凸部的金屬膜係藉由往凹部移動，進行應力的緩和。亦即，對於第二金屬膜15的表面大略垂直所施加之應力及超音波振動所致之衝擊會往橫方向分散，進而，藉由透過大徑金屬栓塞14b，分散於第一金屬膜12，緩和對於第二層間絕緣膜13的衝擊， 達成防止裂痕。
從圖3至圖12揭示各種變形例。
[變形例1]圖3(a)係於接合墊僅配置大徑金屬栓塞14b之半導體裝置的俯視圖。在圖1(a)中，小徑金屬栓塞14a與剖面直徑大於其之大徑金屬栓塞14b以交互佔據正方格子的交點之方式配置，但是，在本變形例中，設為以大徑金屬栓塞14b佔據所有交點的配置。利用如此構造，接合墊區域內的凹部的數量變多，應力緩和力會增加，可更加減少對接合墊下方的衝擊。圖3(b)也是僅配置大徑金屬栓塞14b之半導體裝置的俯視圖。與圖3(a)的不同係奇數行的大徑金屬栓塞14b與偶數行的大徑金屬栓塞14b偏離配置之處。換句話說，大徑金屬栓塞14b係成為配置成鋸齒狀的形狀。如此，接合墊區域係僅配置大徑金屬栓塞14b，但是，接合墊區域外係與第二金屬膜15同層的金屬配線與下層的金屬配線僅利用小徑金屬栓塞14a來電性連接。
[變形例2]圖4係將大徑金屬栓塞14b與小徑金屬栓塞14a交互配置成同心圓狀亦可。又，如圖5所示，僅配置大徑金屬栓塞14b亦可。圖5所示之實施例相較於圖4所示之實施例，大徑金屬栓塞14b的數量較多，應力容易被緩和。
[變形例3]在圖4中，將金屬柱塞配置成同心圓狀，但是，如圖6所示，將金屬柱塞，除了接合墊的角部之外，分割成4個來配置成圓形亦可。於圖6揭示混合存在 大徑金屬栓塞14b與小徑金屬栓塞14a者，於圖7揭示僅配置大徑金屬栓塞14b者。
[變形例4]在圖4中，將金屬柱塞配置成同心圓狀，但是，如圖8所示，將金屬柱塞的配置佈局，配置成螺旋狀亦可。於圖8揭示混合存在大徑金屬栓塞14b與小徑金屬栓塞14a者，於圖9揭示僅配置大徑金屬栓塞14b者。再者，螺旋的方向係作為右旋亦可，左旋亦可。
[變形例5]如圖10所示，於接合墊的中央部，圓形配置大徑金屬栓塞14b，進而，於其外側配置成螺旋狀亦可。此狀況中也作為右旋、左旋任一方皆可。
[變形例6]在圖11及圖12中，將複數金屬柱塞集合而成為台形的區域者，沿著接合墊的4邊，配置4個台形的區域。在圖11中，將小徑金屬栓塞14a交互配置，在圖12中，僅配置大徑金屬栓塞14b。利用此種構造，接合的超音波振動發生方向的衝擊所致之第二金屬膜的變形移動的應力因凹部的影響，而容易被緩和，且探針的侵入方向的應力也容易被緩和。
11‧‧‧第一層間絕緣膜
12‧‧‧第一金屬膜
13‧‧‧第二層間絕緣膜
14a‧‧‧大徑金屬栓塞
14b‧‧‧小徑金屬栓塞
15‧‧‧第二金屬膜
16‧‧‧保護膜
17‧‧‧凹部
18‧‧‧接合墊

Claims (10)

  1. 一種半導體裝置，係具有接合墊的半導體裝置，其特徵為：具備：第一層間絕緣膜上的第一金屬膜；前述第一金屬膜上的第二層間絕緣膜；金屬柱塞，係以貫通前述第二層間絕緣膜之方式形成；及前述接合墊，係在前述第二層間絕緣膜上，隔著前述金屬柱塞電性連接所設置之第二金屬膜所成；前述金屬柱塞，係包含大徑的第一金屬柱塞，藉由前述第二金屬膜進入至前述第一金屬柱塞，並於前述第一金屬柱塞正上的前述接合墊的表面，形成凹部。
  2. 如申請專利範圍第1項所記載之半導體裝置，其中，前述金屬柱塞，係更包含直徑小於前述第一金屬柱塞之小徑的第二金屬柱塞。
  3. 如申請專利範圍第2項所記載之半導體裝置，其中，前述第一金屬柱塞，係由高熔點金屬膜與前述第二金屬膜所成；第二金屬柱塞，係僅由高熔點金屬膜所成；前述第二金屬柱塞正上的前述第二金屬膜的表面係為平坦。
  4. 如申請專利範圍第2項或第3項所記載之半導體裝置，其中， 前述第二金屬柱塞被配置於前述接合墊區域外。
  5. 如申請專利範圍第2項至第4項中任一項所記載之半導體裝置，其中，前述第一金屬柱塞與前述第二金屬柱塞，係在前述接合墊區域內交互配置。
  6. 如申請專利範圍第1項至第5項中任一項所記載之半導體裝置，其中，前述金屬柱塞，係在前述接合墊區域內，被配置成同心圓狀。
  7. 如申請專利範圍第1項至第5項中任一項所記載之半導體裝置，其中，前述金屬柱塞，係除了前述接合墊的角部方向，在前述接合墊區域內，被配置成同心圓狀。
  8. 如申請專利範圍第1項至第5項中任一項所記載之半導體裝置，其中，前述金屬柱塞，係在前述接合墊區域內，被配置成螺旋狀。
  9. 如申請專利範圍第1項至第5項中任一項所記載之半導體裝置，其中，前述金屬柱塞，係以圓形配置於前述接合墊的中央部，進而，於其外側，被配置成螺旋狀。
  10. 如申請專利範圍第1項至第5項中任一項所記載之半導體裝置，其中，前述金屬柱塞，係集合複數個前述金屬柱塞且設為台 形的區域者在前述接合墊區域內，沿著前述接合墊的4邊，配置4個。
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TWI604581B (zh) 2017-11-01
US20150357297A1 (en) 2015-12-10
CN104969334A (zh) 2015-10-07
WO2014119348A1 (ja) 2014-08-07
CN104969334B (zh) 2017-06-16
JP6027452B2 (ja) 2016-11-16
EP2953159A4 (en) 2016-11-09
US9412710B2 (en) 2016-08-09
JP2014150190A (ja) 2014-08-21
KR102145168B1 (ko) 2020-08-18
KR20150112990A (ko) 2015-10-07

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