TW201314854A - 用於半導體裝置的接墊結構 - Google Patents

用於半導體裝置的接墊結構 Download PDF

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TW201314854A
TW201314854A TW100138614A TW100138614A TW201314854A TW 201314854 A TW201314854 A TW 201314854A TW 100138614 A TW100138614 A TW 100138614A TW 100138614 A TW100138614 A TW 100138614A TW 201314854 A TW201314854 A TW 201314854A
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TWI443794B (zh
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Tse-Yao Huang
Yi-Nan Chen
Hsien-Wen Liu
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本發明揭露了一種接墊結構，其包含有：一半導體基材，其上具有複數個金屬間介電層，該些金屬間介電層包含有至少一最上層金屬間介電層；一可接合金屬墊層，設於一接墊形成區域範圍內的該最上層金屬間介電層的表面上；一保護性鈍化層，覆蓋住該可接合金屬墊層的週邊以及該最上層金屬間介電層的表面；以及複數個導孔插塞，設於該接墊形成區域的一環形區域範圍內的該最上層金屬間介電層中，其中該些導孔插塞不形成於該接墊形成區域的一中央區域範圍內。

Description

用於半導體裝置的接墊結構
本發明大體上與一種半導體裝置有關，更特定言之，其係關於一種積體電路的接墊結構。
現今技術已知，如要形成一晶片封裝結構，在組裝流程中必須將積體電路晶片接合在如導線架(leadframe)或封裝基板等晶片載體上。積體電路晶片接合在晶片載體上後會再進行一打線步驟。於此打線製程期間，接合導線會被逐一地接合在積體電路晶片的各個接墊或輸出入(I/O)接墊上，而接合導線的另一端則接合在晶片載體的引腳、接墊或指部結構上。
一般來說，打線製程含有下列步驟。首先，於打線機銲針的打線尖端形成一初始球體，該初始球體會被壓接在晶片的接墊上。其後，該銲針會向上移到離該受壓接球體一預定高度的位置，之後該銲針會再移至晶片載體的一接合位置處，藉此使打線電性與機械性地連接該晶片接墊與晶片載體。
目前業界中廣泛地將低介電值(low-k)與/或超低介電值介電材用在金屬間介電層(inter-metal dielectric,IMD)中，以減少RC延遲與寄生電容。然而隨著介電常數的減少，介電材的強度亦隨之降低。因此許多的低介電值介電材都很容易裂開，並缺少承受打線接合期間施加在接墊上的應力所需之強度。舉例言之，目前打線製程期間已觀察到了許多因接墊脫層以及該接墊下方的介電材強度不足等原因所導致的接墊偏移等現象。
故此，目前業界需要一種可承受打線接合製程時施加在其上應力的改良式接墊結構，以解決先前技術中存在的接墊脫層以及接墊偏移等問題。
本發明的目的之一即在於提供一種改良的接墊結構，以解決前述先前技術中存在的問題。
根據本發明實施例，接墊結構包含有一半導體基材，其上具有複數個金屬間介電層，該些金屬間介電層包含有至少一最上層金屬間介電層；一可接合金屬墊層，設於一接墊形成區域範圍內的該最上層金屬間介電層的表面上；一保護性鈍化層，覆蓋住該可接合金屬墊層的週邊以及該最上層金屬間介電層的表面；以及複數個導孔插塞，設於該接墊形成區域的一環形區域範圍內的該最上層金屬間介電層中，其中該些導孔插塞不形成於該接墊形成區域的一中央區域範圍內。
無疑地，本發明的這類目的與其他目的在閱者讀過下文以多種圖示與繪圖來描述的較佳實施例細節說明後將變得更為顯見。
在下文的細節描述中，元件符號會被用來標示在隨附的圖示中成為其中的一部份，並且以可實行該實施例之特例描述方式來表示。這類實施例會說明足夠的細節俾使該領域之一般技藝人士得以具以實施。閱者須瞭解到本發明中亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
現在請參照第1圖與第2圖。第1圖為一截面示意圖，其表示出根據本發明實施例一製作在接墊形成區域200中的接墊結構300。第2圖為根據本發明實施例該接墊結構300的頂視圖。如第1圖與第2圖所示，發明中提供有一半導體基材100，如矽基材。半導體基材100的主表面上係層疊有複數個金屬間介電層102～108。該些金屬間介電層102～108可包含氧化矽、氮化矽、氮氧化矽、碳化矽、磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate,BPSG)、或領域中習知的低介電值或超高介電值介電材。
如第一圖所示，接墊形成區域200範圍內的金屬間介電層108頂面上具有一可接合金屬墊層30(如鋁墊)，在某些例子中其可能為重佈層(re-distributed layer,RDL)的一部份。在形成可接合金屬墊層30之後，一保護性鈍化層110(如氮化矽、聚亞醯胺、或任何合適的鈍化材質)會被用來覆蓋在可接合金屬墊層30與金屬間介電層108的頂面上。之後，於保護性鈍化層110中形成一開口110a，以裸露出部分的可接合金屬墊層30。其後，打線40會經由該開口110a接在可接合金屬墊層30的裸露面上。
如先前所提到的，在打線接合製程期間，施加在可接合金屬墊層30上的應力可能會造成接墊偏移等問題。本案申請人已發現銅-碳化矽蓋層介面處的鋁離析現象可能在上述接墊偏移問題中扮演重要的角色。為了避免此問題，根據本發明實施例，位於接墊形成區域200的中央區域202範圍內的可接合金屬墊層30正下方的三維空間150中(圖中以虛線來表示)將不會形成有任何互連結構。
如第1圖與第2圖所示，接墊結構300包含一位在金屬間介電層108上的可接合金屬墊層30、複數個製作在該金屬間介電層108中的導孔插塞28，以將可接合金屬墊層30耦接至下層製作在金屬間介電層106中的第二層鑲嵌銅結構26a與26b。金屬間介電層106中可具有一碳化矽蓋層106a。根據本發明實施例，接墊形成區域200的中央區域202周圍的環形區域204範圍中係可製作有複數個導孔插塞28。根據本發明實施例，鑲嵌銅結構26b可為一環形銅質層，而鑲嵌銅結構26b可包含複數個銅質導孔插塞。金屬間介電層104中可形成類似的環形鑲嵌銅結構24。金屬間介電層102中可具有一接觸插塞層22。閱者應瞭解在某些實施例中，接觸插塞層22可以省去，亦應瞭解在某些實施例中，金屬間介電層104中的鑲嵌銅結構24可以省去。
使用本發明的好處在於因為接墊形成區域200的中央區域202範圍內的可接合金屬墊層30正下方的三維空間150中不會形成有互連結構(特別是鑲嵌銅結構)，因而可以避免接墊偏移等問題。本案申請人已發現到藉由不在接墊形成區域200的中央區域202範圍內的可接合金屬墊層30正下方的三維空間150中形成導孔插塞28與鑲嵌銅結構之作法將可避免銅-碳化矽蓋層介面的鋁離析現象，並大幅改善金屬間介電層之間的整合度以及其間的接合強度(特別是碳化矽蓋層106a與金屬間介電層106其他部位之間)。
本領域之技藝人士將可輕易瞭解到在維持本發明教示之前提下，本發明之元件與方法可加以修改或變形成多種態樣。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
22．．．接觸插塞層
24/26a/26b．．．鑲嵌銅結構
28．．．導孔插塞
30．．．可接合金屬墊層
40．．．打線
100．．．半導體基材
102/104/106/108．．．金屬間介電層
106a．．．碳化矽蓋層
110．．．保護性鈍化層
110a．．．開口
150．．．三維空間
200．．．接墊形成區域
202．．．中央區域
204．．．環形區域
300．．．接墊結構
本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：
第1圖為一截面示意圖，其表示出根據本發明實施例一製作在接墊形成區域中的接墊結構；以及
第2圖為根據本發明實施例接墊結構的頂視圖。
須注意本說明書中的所有圖示皆為圖例性質。為了清楚與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現。圖中相同的參考符號一般而言會用來標示修改後或不同實施例中對應或類似的特徵。
22．．．接觸插塞層
24/26a/26b．．．鑲嵌銅結構
28．．．導孔插塞
30．．．可接合金屬墊層
40．．．打線
100．．．半導體基材
102/104/106/108．．．金屬間介電層
106a．．．碳化矽蓋層
110．．．保護性鈍化層
110a．．．開口
150．．．三維空間
200．．．接墊形成區域
202．．．中央區域
204．．．環形區域
300．．．接墊結構

Claims (9)

  1. 一種接墊結構，包含有：一半導體基材，其上具有複數個金屬間介電層，該些金屬間介電層包含有至少一最上層金屬間介電層；一可接合金屬墊層，設於一接墊形成區域範圍內的該最上層金屬間介電層的表面上；一保護性鈍化層，覆蓋住該可接合金屬墊層的週邊以及該最上層金屬間介電層的表面；以及複數個導孔插塞，設於該接墊形成區域的一環形區域範圍內的該最上層金屬間介電層中，其中該些導孔插塞不形成於該接墊形成區域的一中央區域範圍內。
  2. 如申請專利範圍第1項所述之接墊結構，其中，位於該接墊形成區域的中央區域內的該可接合金屬墊層正下方的一三維立體空間內不會形成有任何的互連結構。
  3. 如申請專利範圍第2項所述之接墊結構，其中該互連結構係為鑲嵌銅結構。
  4. 如申請專利範圍第3項所述之接墊結構，其中該最上層金屬間介電層係直接層疊於一碳化矽蓋層上。
  5. 如申請專利範圍第4項所述之接墊結構，其中藉由不要在該接墊形成區域的中央區域內的該可接合金屬墊層正下方的三維立體空間內形成任何的互連結構之作法可避免銅-碳化矽介面的鋁離析問題。
  6. 如申請專利範圍第1項所述之接墊結構，其中該些金屬間介電層包含有氧化矽、氮化矽、氮氧化矽、碳化矽、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、或低介電值或超高介電值之介電材。
  7. 如申請專利範圍第1項所述之接墊結構，其中該可接合之金屬墊層包含有鋁。
  8. 如申請專利範圍第1項所述之接墊結構，其中該可接合金屬墊層亦為一重佈層(RDL)的一部份。
  9. 如申請專利範圍第1項所述之接墊結構，其中另包含有一環形的鑲嵌銅結構。
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