TWI779684B - 具有傾斜隔離層之半導體元件及其製備方法 - Google Patents
具有傾斜隔離層之半導體元件及其製備方法 Download PDFInfo
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- TWI779684B TWI779684B TW110123082A TW110123082A TWI779684B TW I779684 B TWI779684 B TW I779684B TW 110123082 A TW110123082 A TW 110123082A TW 110123082 A TW110123082 A TW 110123082A TW I779684 B TWI779684 B TW I779684B
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- Prior art keywords
- isolation layers
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- layer
- isolation
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 142
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims description 287
- 239000000463 material Substances 0.000 claims description 70
- 238000005530 etching Methods 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 26
- 229910052799 carbon Inorganic materials 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 239000002131 composite material Substances 0.000 claims description 13
- 229910052582 BN Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000003361 porogen Substances 0.000 claims description 8
- 238000010336 energy treatment Methods 0.000 claims description 5
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 4
- ZILJFRYKLPPLTO-UHFFFAOYSA-N [C].[B].[Si] Chemical compound [C].[B].[Si] ZILJFRYKLPPLTO-UHFFFAOYSA-N 0.000 claims description 4
- -1 silicon oxide nitride Chemical class 0.000 claims description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 2
- 239000007789 gas Substances 0.000 description 23
- 239000002243 precursor Substances 0.000 description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- 239000011521 glass Substances 0.000 description 16
- 239000001257 hydrogen Substances 0.000 description 13
- 229910052739 hydrogen Inorganic materials 0.000 description 13
- 239000000203 mixture Substances 0.000 description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000001154 acute effect Effects 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 230000015654 memory Effects 0.000 description 8
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 150000002430 hydrocarbons Chemical class 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 229940104869 fluorosilicate Drugs 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000003848 UV Light-Curing Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000008282 halocarbons Chemical class 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- WGGNJZRNHUJNEM-UHFFFAOYSA-N 2,2,4,4,6,6-hexamethyl-1,3,5,2,4,6-triazatrisilinane Chemical compound C[Si]1(C)N[Si](C)(C)N[Si](C)(C)N1 WGGNJZRNHUJNEM-UHFFFAOYSA-N 0.000 description 2
- 229910000951 Aluminide Inorganic materials 0.000 description 2
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- RQQRTMXCTVKCEK-UHFFFAOYSA-N [Ta].[Mg] Chemical compound [Ta].[Mg] RQQRTMXCTVKCEK-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- BGECDVWSWDRFSP-UHFFFAOYSA-N borazine Chemical compound B1NBNBN1 BGECDVWSWDRFSP-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000001273 butane Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 150000001247 metal acetylides Chemical class 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- IJDNQMDRQITEOD-UHFFFAOYSA-N n-butane Chemical compound CCCC IJDNQMDRQITEOD-UHFFFAOYSA-N 0.000 description 2
- OFBQJSOFQDEBGM-UHFFFAOYSA-N n-pentane Natural products CCCCC OFBQJSOFQDEBGM-UHFFFAOYSA-N 0.000 description 2
- 125000000962 organic group Chemical group 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000001294 propane Substances 0.000 description 2
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 2
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 2
- MWWATHDPGQKSAR-UHFFFAOYSA-N propyne Chemical compound CC#C MWWATHDPGQKSAR-UHFFFAOYSA-N 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NWHAUAZVLJCRBB-UHFFFAOYSA-N [Si](=O)=O.[B] Chemical compound [Si](=O)=O.[B] NWHAUAZVLJCRBB-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- VOSJXMPCFODQAR-UHFFFAOYSA-N ac1l3fa4 Chemical compound [SiH3]N([SiH3])[SiH3] VOSJXMPCFODQAR-UHFFFAOYSA-N 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000003610 charcoal Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013036 cure process Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- UPKIHOQVIBBESY-UHFFFAOYSA-N magnesium;carbanide Chemical compound [CH3-].[CH3-].[Mg+2] UPKIHOQVIBBESY-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 125000000383 tetramethylene group Chemical group [H]C([H])([*:1])C([H])([H])C([H])([H])C([H])([H])[*:2] 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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Abstract
本揭露提供一種具有多個傾斜隔離層之半導體元件及其製備方法。該半導體元件包括一基底、二導電栓柱、一第一組傾斜隔離層以及一第二組傾斜隔離層;該二導電栓柱位在該基底上,並沿一垂直軸延伸;該第一組傾斜隔離層係相互平行,且位在該二導電栓柱之間;該第二組傾斜隔離層相互平行,且位在該二導電栓柱之間。該第一組傾斜隔離層沿一第一方向延伸,該第一方向相對於該垂直軸傾斜;該第二組傾斜隔離層沿一第二方向延伸,該第二方向相對於該垂直軸傾斜;以及該第一方向與該第二方向係交叉。
Description
本申請案主張2020年9月24日申請之美國正式申請案第17/031,119號的優先權及益處,該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是有關於一種具有多個傾斜隔離層之半導體元件及其製備方法。
半導體元件係使用在不同的電子應用,例如個人電腦、手機、數位相機,或其他電子設備。半導體元件的尺寸係逐漸地變小,以符合計算能力所逐漸增加的需求。然而,在尺寸變小的製程期間,係增加不同的問題,且如此的問題在數量與複雜度上持續增加。因此,仍然持續著在達到改善品質、良率、效能與可靠度以及降低複雜度方面的挑戰。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件,包括一基底;二導電栓柱,位在該基底上,並沿一垂直軸延伸;一第一組傾斜隔離層,係相互平行,並位在該二導電栓柱之間;以及一第二組傾斜隔離層,係相互平行,並位在該二導電栓柱之間;其中,該第一組傾斜隔離層沿一第一方向延伸,該第一方向相對於該垂直軸傾斜;該第二組傾斜隔離層沿一第二方向延伸,該第二方向相對於該垂直軸傾斜;以及該第一方向與該第二方向係交叉。
在一些實施例中,該半導體元件還包括一第一隔離層,係位在該基底上,其中該二導電栓柱係沿該第一隔離層設置,該第一組傾斜隔離層與該第二組傾斜隔離層係位在該第一隔離層中,以及該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料係不同於該第一隔離層的材料。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層包含一材料,該材料具有一介電常數,係低於該第一隔離層之材料的介電常數。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層為多孔的。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層的各孔隙率,係介於大約10%到大約80%之間。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料具有一熱膨脹係數以及一楊氏模數(Young’s Modulus),該熱膨脹係數係小於大約20ppm/°C,該楊氏模數係小於大約15GPa。
在一些實施例中,該半導體元件還包括一墊層,位在該二導電栓柱、該第一組傾斜隔離層以及該第二組傾斜隔離層上。
在一些實施例中,該第一方向與該垂直軸之間的一角度,係介於大約10度到大約80度之間。
在一些實施例中,該第二方向與該垂直軸之間的一角度,係介於大約-10度到大約-80度之間。
在一些實施例中,該第一方向與該垂直軸之間的一角度,係不同於該第二方向與該垂直軸之間的一角度。
在一些實施例中,該第一方向與該垂直軸之間的一角度係與該第二方向與該垂直軸之間的一角度相反。
在一些實施例中,該第一組傾斜隔離層的各下表面與該第二組傾斜隔離層的各下表面,係大致與該第一隔離層的一下表面為共面。
在一些實施例中,該第一組傾斜隔離層的各最低點與該第二組傾斜隔離層的各最低點係位在一位面處,該位面係在該第一隔離層的一下表面上。
本揭露之另一實施例提供一種半導體元件的製備方法,包括提供一基底;形成一第一隔離層在該基底上;沿著該第一隔離層形成二導電栓柱;沿著該第一隔離層形成一第一組傾斜溝槽在該二導電栓柱之間;沿著該第一隔離層形成一第二組傾斜溝槽在該二導電栓柱之間;沿一第一方向形成一第一組傾斜隔離層在該第一組傾斜溝槽中;以及沿一第二方向形成一第二組傾斜隔離層在該第二組傾斜溝槽中;其中,該第一組傾斜隔離層與該第二組傾斜隔離層係同時形成,以及該第一方向與該第二方向係交叉。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料係不同於該第一隔離層的材料。
在一些實施例中,該第一組傾斜隔離層與該第二組傾斜隔離層包含一材料,該材料具有一介電常數,係低於該第一隔離層之材料的介電常數。
在一些實施例中,形成該第一組傾斜溝槽的該步驟係包括:形成一第一硬遮罩層在該第一隔離層上;沿著該第一硬遮罩層形成多個第一硬遮罩開孔;以及使用該第一硬遮罩層與該等第一硬遮罩開孔當作多個圖案引導件,以執行一第一傾斜蝕刻製程在該第一隔離層上,以形成該第一組傾斜溝槽。
在一些實施例中,該第一硬遮罩層包含下列材料:氧化矽、氮化矽、氮氧化矽、氧化氮化矽(silicon nitride oxide)、氮化硼、矽硼氮化物(silicon boron nitride)、磷硼氮化物(phosphorus boron nitride)、硼碳矽氮化物(boron carbon silicon nitride)或是一碳膜。
在一些實施例中,形成該第二組傾斜隔離層的該步驟,係包括:使用該第一硬遮罩層與該等第一硬遮罩開孔當作多個圖案引導件,以執行一第二傾斜蝕刻製程在該第一隔離層上,以形成該第二組傾斜溝槽,以及該第一傾斜蝕刻製程的一入射角係與該第二傾斜蝕刻製程的一入射角相反。
在一些實施例中,形成該第一組傾斜隔離層的該步驟以及形成該第二組傾斜隔離層的該步驟,係包括:形成一層能量可移除複合物在該第一組傾斜溝槽與該第二組傾斜溝槽中,且該層能量可移除複合物包括一基礎材料以及一可分解成孔劑材料;以及執行一能量處理以轉換該層能量可移除複合物成為該第一組傾斜隔離層與該第二組傾斜隔離層。
由於本揭露該半導體元件的設計,第一組傾斜隔離層以及第二組傾斜隔離層可用來調整該等導電栓柱之間的介電常數。因此,係可降低該等導電栓柱之間的寄生電容。因此,係可改善該半導體元件效能。此外,該第一組傾斜隔離層與該第二組隔離層可增加該第一隔離層的彈性,其係在一接合製程或一佈線製程(wiring process)期間,可改善該半導體元件之接合強度的電阻。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
以下描述了組件和配置的具體範例,以簡化本揭露之實施例。當然,這些實施例僅用以例示,並非意圖限制本揭露之範圍。舉例而言,在敘述中第一部件形成於第二部件之上,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不會直接接觸的實施例。另外,本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚,除非內文中特別說明,其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係 用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
應當理解,當形成一個部件在另一個部件之上(on)、與另一個部件相連(connected to)、及/或與另一個部件耦合(coupled to),其可能包含形成這些部件直接接觸的實施例,並且也可能包含形成額外的部件介於這些部件之間,使得這些部件不會直接接觸的實施例。
應當理解,儘管這裡可以使用術語第一,第二,第三等來描述各種元件、部件、區域、層或區段(sections),但是這些元件、部件、區域、層或區段不受這些術語的限制。相反,這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此,在不脫離本發明進步性構思的教導的情況下,下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。
除非內容中另有所指,否則當代表定向(orientation)、布局(layout)、位置(location)、形狀(shapes)、尺寸(sizes)、數量(amounts),或其他量測(measures)時,則如在本文中所使用的例如「同樣的(same)」、「相等的(equal)」、「平坦的(planar)」,或是「共面的(coplanar)」等術語(terms)並非必要意指一精確地完全相同的定向、布局、位置、形狀、尺寸、數量,或其他量測,但其意指在可接受的差異內,係包含差不多完全相同的定向、布局、位置、形狀、尺寸、數量,或其他量測,而舉例來說,所述可接受的差異係可因為製造流程(manufacturing processes)而發生。術語「大致地(substantially)」係可被使用在本文中,以表現出此意思。舉例來說,如大致地相同的(substantially the same)、大致地相等的(substantially equal),或是大致地平坦的(substantially planar),係為精確地相同的、相等的,或是平坦的,或者是其係可為在可接受的差異內的相同的、相等的,或是平坦的,而舉例來說,所述可接受的差異係可因為製造流程而發生。
在本揭露中,一半導體元件通常意指可藉由利用半導體特性(semiconductor characteristics)運行的一元件,而一光電元件(electro-optic device)、一發光顯示元件(light-emitting display device)、一半導體線路(semiconductor circuit)以及一電子元件(electronic device),係均包括在半導體元件的範疇中。
應當理解,在本揭露的描述中,上方(above)(或之上(up))係對應Z方向箭頭的該方向,而下方(below)(或之下(down))係對應Z方向箭頭的相對方向。
圖1例示本揭露一些實施例之一半導體元件1A的剖視示意圖。請參考圖1,在一些實施例中,基底101可為一塊狀(bulk)半導體基底,舉例來說,該塊狀半導體基底可包含一元素半導體、一化合物半導體;該元素半導體例如矽或鍺;該化合物半導體係例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦(indium phosphide)、砷化銦(indium arsenide)、銻化銦(indium antimonide)或其他III-V族化合物半導體或II-VI族化合物半導體。
在一些實施例中,基底101可包括絕緣體上覆半導體結構,其從下到上由一處置基底、一隔離層以及一最上面半導體層所組成。該處置基底與該最上面半導體層所包含的材料,係類似於前述塊狀半導體基底的材料。該隔離層可為一結晶或非結晶介電材料,例如一氧化物及/或一氮化物。 該隔離層可具有一厚度,係介於大約10nm到200nm之間。
基底101亦可包含介電質、隔離層或導電特徵,其係形成在該塊狀半導體基底或該絕緣體上覆半導體結構上。舉例來說,該等介電質或該等隔離層可包括一半導體氧化物、一半導體氮化物、半導體氮氧化物、半導體碳化物、四乙氧基矽烷氧化物(tetraethyl orthosilicate oxide)、磷矽酸鹽玻璃(phosphosilicate glass)、硼磷矽酸鹽玻璃(borophosphosilicate glass)、氟化矽玻璃(fluorinated silica glass)、摻碳氧化矽(carbon doped silicon oxide)、非結晶的氟化碳(amorphous fluorinated carbon)或其組合。該等導電特徵可為導電線、導電通孔、導電接觸點或類似物。該等介電質或該等隔離層可當作一絕緣體,其係支撐並電性絕緣該等導電特徵。
在一些實施例中,多個裝置元件(圖未示)可設置在基底101中。舉例來說,該等裝置元件可為雙極性接面電晶體(bipolar junction transistors)、金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor)、二極體、系統大型積體電路(system large-scale integration)、快閃記憶體(flash memories)、動態隨機存取記憶體(dynamic random-access memories)、靜態隨機存取記憶體(static random-access memories)、電可擦除可程式化唯讀記憶體(electrically erasable programmable read-only memory)、影像感測器、微機電系統、主動元件或被動元件。該等裝置元件可藉由多個隔離結構而與相鄰的多個裝置元件電性隔離,而該等隔離結構係例如淺溝隔離(shallow trench isolation)。
請參考圖1,下隔離層103可設置在基底101上。在一些實施例中,下隔離層103可包含以下材料:氮化矽、氧化矽、氮氧化矽、氧化氮化矽、流動氧化物(flowable oxide)、矽氮烷(tonen silazen)、未摻雜矽玻璃(undoped silica glass)、硼二氧化矽玻璃(borosilica glass)、磷矽酸鹽玻璃(phosphosilica glass)、硼磷矽酸鹽玻璃(boroPhosphoSilica glass)、電漿輔助四氧乙基矽(plasma-enhanced tetra-ethyl orthoSilicate)、氟矽酸鹽玻璃(fluoride silicate glass)、摻碳的氧化矽(carbon-doped silicon oxide)、有機矽酸鹽玻璃(organo silicate glass)、低介電常數介電材料或其組合。該低介電常數材料可具有一介電常數,係小於3.0或甚至小於2.5。
請參考圖1,下導電層105可設置在下隔離層103中。舉例來說,下導電層105包含銅、鋁、鈦、鎢、類似物或其組合。下導電層105可電性耦接到該等裝置元件。
請參考圖1,第一隔離層107可設置在下隔離層103上。在一些實施例中,第一隔離層107可包含下列材料:氮化矽、氧化矽、氮氧化矽、氧化氮化矽、流動氧化物、矽氮烷、未摻雜矽玻璃、硼二氧化矽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、電漿輔助四氧乙基矽、氟矽酸鹽玻璃、摻碳的氧化矽、有機矽酸鹽玻璃、低介電常數介電材料或其組合。
在一些實施例中,第一隔離層107可包含下列材料:氧化矽、氮化矽、氮氧化矽、氮化氧化矽(silicon oxide nitride)、聚醯亞胺(polyimide)、聚苯並噁唑(polybenzoxazole)、磷矽酸鹽玻璃、未摻雜矽玻璃或氟矽酸鹽玻璃。第一隔離層107可視為一鈍化層。
請參考圖1,導電栓柱201-1、201-3可沿第一隔離層107與下隔離層103垂直設置。意即,導電栓柱201-1、201-3可沿垂直軸Z延伸。導電栓柱201-1、201-3之各側壁的各下部可貼合到下導電層105。換言之,導電栓柱201-1、201-3以及下導電層105可電性連接。導電栓柱201-1、201-3的各上表面可大致與第一隔離層107的各上表面107TS為共面。舉例來說,導電栓柱201-1、201-3可包含鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭鎂(tantalum magnesium carbide))、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物或其組合。
請參考圖1,第一組傾斜隔離層301可設置在第一隔離層107中,以及在導電栓柱201-1、201-3之間。第一組傾斜隔離層301的各上表面301TS可大致與第一隔離層107的上表面107TS為共面。第一組傾斜隔離層301的各下表面301BS可大致與第一隔離層107的下表面107BS為共面。第一組傾斜隔離層301可相互平行。第一組傾斜隔離層301可沿一第一方向E1延伸。第一方向E1可相對於垂直軸Z傾斜。第一方向E1與垂直軸Z之間的一角度α,可介於大約10度與大約80度之間。
請參考圖1,第二組傾斜隔離層303可設置在第一隔離層107中,以及在導電栓柱201-1、201-3之間。第二組傾斜隔離層303的各上表面303TS可大致與第一隔離層107的上表面107TS為共面。第二組傾斜隔離層303的各下表面303BS可與第一隔離層107的下表面107BS為共面。第二組傾斜隔離層303可相互平行。第二組傾斜隔離層303可沿一第二方向E2延伸。第二方向E2可相對於垂直軸Z傾斜。第一方向E1與第二方向E2可交叉。第二方向E2與垂直軸Z之間的一角度β,係介於大約-10度到大約-80度之間。第一組傾斜隔離層301中的一些以及第二組傾斜隔離層303中的一些可交叉。第一組傾斜隔離層301中的另一些以及第二組傾斜隔離層303中的另一些可不交叉。
在一些實施例中,第一方向E1與第二方向E2之間的一角度,可介於大約20度到大約160度之間。
第一組傾斜隔離層301與第二組傾斜隔離層303可包含相同材料。在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303可包含不同於第一隔離層107的材料。在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303可包含下列材料:氮化矽、氧化矽、氮氧化矽、氧化氮化矽、流動氧化物、矽氮烷、未摻雜矽玻璃、硼二氧化矽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、電漿輔助四氧乙基矽、氟矽酸鹽玻璃、摻碳的氧化矽、有機矽酸鹽玻璃、低介電常數介電材料或其組合。
在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303可包含一材料,係具有一介電常數,該介電常數係低於第一隔離層107的介電常數。包含較低介電常數之材料的第一組傾斜隔離層301與第二組傾斜隔離層303,係可降低導電栓柱201-1、201-3之間的寄生電容。意即,包含較低介電常數之材料的第一組傾斜隔離層301與第二組傾斜隔離層303,係減緩導電栓柱201-1、201-3所產生的電子訊號之間或是施加到導電栓柱201-1、201-3之間的電子訊號之間的一干擾效應(interference effect)。
在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303可包含一材料,該材料係具有一熱膨脹係數以及一楊氏模數(Young’s Modulus),該熱膨脹係數小於大約20ppm/°C,楊氏模數係小於大約15GPa。在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303可包含一材料,該材料係包括聚醯亞胺或一環氧基(epoxy-based)材料。第一組傾斜隔離層301與第二組傾斜隔離層303可當成一減震墊(cushion),以降低一凸塊製程(bumping process)或一佈線製程(wiring process)的一應力;因此,可減少第一隔離層107的分層(delamination)。
請參考圖1,墊層109可設置在第一隔離層107上。墊層109可覆蓋導電栓柱201-1、201-3的各上表面、第一組傾斜隔離層301的各上表面301TS以及第二組傾斜隔離層303的各上表面301TS。舉例來說,墊層109可包含下列材料:鋁、銅、鈦、鎢、鋁-銅合金、鋁合金或銅合金。
圖2到圖9例示本揭露一些實施例之各半導體元件1B、1C、1D、1E、1F、1G、1H、1I的剖視示意圖。請參考圖2,半導體元件1B可具有類似於如圖1所例示的一結構。圖2中與圖1中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖2,導電栓柱201-1、201-3之各側壁的各下部可遠離下導電層105。第一組傾斜隔離層301與第二組傾斜隔離層303可設置在導電栓柱201-1、201-3之間。
請參考圖3,半導體元件1C可具有類似於如圖1所例示的一結構。圖3中與圖1中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。
請參考圖3,導電栓柱201-1、201-3可沿第一隔離層107設置,並設置在下導電層105上。第一組傾斜隔離層301與第二組傾斜隔離層303可設置在導電栓柱201-1、201-3之間。
請參考圖4,半導體元件1D可具有類似於如圖1所例示的一結構。圖4中與圖1中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖4,導電栓柱201-1可沿第一隔離層107設置,並設置在下導電層105上。導電栓柱201-3可沿第一隔離層107與下導電層105設置。導電栓柱201-3之側壁的下部可接合在下導電層105上。第一組傾斜隔離層301與第二組傾斜隔離層303可設置在導電栓柱201-1、201-3之間。
請參考圖5,半導體元件1E可具有類似於如圖4所例示的一結構。圖5中與圖4中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖5,導電栓柱201-3之側壁的下部可遠離下導電層105。在一些實施例中,導電栓柱201-3可電性隔離下導電層105。第一組傾斜隔離層301與第二組傾斜隔離層303可設置在導電栓柱201-1、201-3之間。導電栓柱201-3可改善半導體元件1E的機械強度(mechanical strength)。
請參考圖6,半導體元件1F可具有類似於如圖1所例示的一結構。圖6中與圖1中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖6,第一組傾斜隔離層301與第二組傾斜隔離層303可為多孔的(porous)。第一組傾斜隔離層301與第二組傾斜隔離層303的個孔隙率可介於大約10%到大約80%之間。第一組傾斜隔離層301與第二組傾斜隔離層303可包括一骨架以及複數個空的空間,該等空的空間係在骨架之間。複數個空的空間可相互連接,並可填滿空氣。舉例來說,骨架可包含氧化矽、低介電質材料(low-dielectric materials)或甲基矽倍半氧烷(methylsilsesquioxane)。第一組傾斜隔離層301與第二組傾斜隔離層303之複數個空的空間可填滿空氣。因此,舉例來說,第一組傾斜隔離層301與第二組傾斜隔離層303的一介電常數,可大大地低於包含氧化矽的一層。因此,第一組傾斜隔離層301與第二組傾斜隔離層303可大大地降低導電栓柱201-1、210-3之間的寄生電容。意即,第一組傾斜隔離層301與第二組傾斜隔離層303係可減緩導電栓柱201-1、201-3所產生的電子訊號之間或是施加到導電栓柱201-1、201-3之間的電子訊號之間的一干擾效應(interference effect)。
請參考圖7,半導體元件1G可具有類似於如圖1所例示的一結構。圖7中與圖1中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖7,更多的導電栓柱可設置在半導體元件1G中。舉例來說,導電栓柱201-1、201-3可沿第一隔離層107與下隔離層103設置。導電栓柱201-5、201-7可沿第一隔離層107設置,並可設置在下導電層105上。第一組傾斜隔離層301與第二組傾斜隔離層303可分別對應設置在相鄰對的導電栓柱201-1、201-3、201-5、201-7之間。
請參考圖8,半導體元件1H可具有類似於如圖7所例示的一結構。圖8中與圖7中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。請參考圖8,第一組傾斜隔離層301與第二組傾斜隔離層303可僅設置在相鄰對之導電栓柱201-1、201-3、201-5、201-7中的一些中。舉例來說,在本揭露中,第一組傾斜隔離層301與第二組傾斜隔離層303可僅設置在導電栓柱201-1、201-5之間,以及在導電栓柱201-7、201-3之間。
請參考圖9,半導體元件1I可具有類似於如圖7所例示的一結構。圖9中與圖7中相同或類似的元件係已以相似的元件編號進行標示,並已省略重複的描述。
請參考圖9,第一組傾斜隔離層301的各最低點301BP以及第二組傾斜隔離層303的各最低點303BP可位在一垂直位面,係位在第一隔離層107之下表面107BS之一垂直位面上。
圖10例示本揭露一些實施例之半導體元件1A之製備方法10的流程示意圖。圖11到圖19例示本揭露一些實施例之半導體元件1A之製備方法的流程的剖視示意圖。請參考圖10及圖11,在步驟S11,可提供一基底101,一下導電層104可形成在基底101上,以及一第一隔離層107可形成在下導電層105上。
請參考圖11,一下隔離層103可形成在基底101上。下隔離層103的製作技術可包含一沉積製程,例如化學氣相沉積、電漿加強化學氣相沉積、低壓化學氣相沉積或類似方法。下導電層105可藉由一鑲嵌製程(damascene process)而形成在下隔離層103中。第一隔離層107可以類似於下隔離層103形成的一程序而形成在下導電層105與下隔離層103上。
請參考圖10及圖12,在步驟S13,導電栓柱201-1、201-3可沿第一隔離層107形成,並電性連接到下導電層105,以及一第一硬遮罩層401可形成在第一隔離層107上。請參考圖12,可執行一微影製程以界定導電栓柱201-1、201-3的一所欲圖案。可繼續進行一接續的蝕刻製程,例如一非等向性該蝕刻製程,以沿著第一隔離層107與下隔離層103而垂直形成多個開孔。一導電材料可完全填滿該等開孔,而該導電材料係例如鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭鎂(tantalum magnesium carbide))、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物或其組合。接下來,可執行一平坦化製程,例如化學機械研磨,直到第一隔離層107的上表面暴露為止,以移除多餘材料,提供一大致平坦表面給接下來的處理步驟,並同時形成導電栓柱201-1、210-3。
在一些實施例中,第一硬遮罩層401可包含氧化矽、氮化矽、氮氧化矽、氧化氮化矽、類似物或其組合。第一硬遮罩層401的製作技術包含多個沉積製程,例如化學氣相沉積、電漿加強化學氣相沉積、低壓化學氣相沉積或類似方法。
應當理解,在本揭露的描述中,氮氧化矽表示一物質(substance),其係包含矽、氮以及氧,且在其中之氧的一比率係大於氮的一比率。氧化氮化矽係表示一物質,其係包含矽、氧以及氮,且在其中之氮的一比率係大於氧的一比率。
在一些實施例中,第一硬遮罩層401可包含氮化硼、矽硼氮化物、磷硼氮化物或硼碳矽氮化物。第一硬遮罩層401的製作技術可包含一膜形成製程以及一處理製程。在一些實施例中,在模形成製程中,可為硼基(boron-based)前驅物的第一前驅物可引入在第一隔離層107上,以形成一硼基層。接下來,在處理製程中,可為氮基前驅物的第二前驅物可引入,以與硼基層產生反應,並轉換硼基層成為第一硬遮罩層401。
在一些實施例中,該等第一前驅物可為二硼烷(diborane)、硼氮炔(borazine)或是硼氮炔的一烷基取代衍生物(alkyl-substituted derivative)。在一些實施例中,該等第一前驅物可以一流量引入,該流量係介於大約5 sccm(每分鐘標準立方公分(standard cubic centimeter per minute))到大約50 slm(每分鐘標準公升(standard liter per minute))之間;在一些實施例中,介於大約10 sccm到大約1 slm之間。在一些實施例中,該等第一前驅物可藉由稀釋氣體(dilution gas)而被引入,該稀釋氣體係例如氮(nitrogen)、氫(hydrogen)、氬(argon)或其組合。該稀釋氣體可以一流量被引入,該流量係介於大約5 sccm到大約50 slm之間;在一些實施例中,介於大約1 slm到大約10 slm之間。
在一些實施例中,膜形成製程無須電漿的輔助即可執行。在此狀況下,膜形成製程的一基底溫度可介於大約100℃到大約1000℃之間。舉例來說,膜形成製程的基底溫度可介於大約300℃到大約500℃之間。膜形成製程的一製程壓力可介於大約10 mTorr到大約760 Torr之間。舉例來說,膜形成製程的製程壓力可介於大約2 Torr到大約10 Torr之間。
在一些實施例中,膜形成製程可在電漿存在下進行。在此情況下,膜形成製程的一基底溫度可介於大約100℃到大約1000℃之間。舉例來說,膜形成製程的基底溫度可介於大約300℃到大約500℃之間。膜形成製程的一製程溫度可介於大約10 mTorr到大約760 Torr。舉例來說,膜形成製程的製程溫度可介於大約2 Torr到大約10 Torr。電漿可藉由介於2 W到5000 W之間的一射頻功率(RF power)所提供。舉例來說,電漿係藉由介於30 W到1000 W之間的一射頻功率(RF power)所提供。
在一些實施例中,該等第二前驅物可為氨水(ammonia)或聯氨(hydrazine)。在一些實施例中,該等第二前驅物可以一流量引入,該流量係介於大約5 sccm到大約50 slm之間;在一些實施例中,介於大約10 sccm到大約1 slm之間。
在一些實施例中,多個氧基前驅物可在處理製程中與該等第二前驅物一起引入。舉例來說,該等氧基前驅物可為氧、一氧化氮(nitric oxide)、一氧化二氮(nitrous oxide)、二氧化碳或水。
在一些實施例中,多個矽基前驅物可在處理製程中與該等第二前驅物一起引入。舉例來說,該等矽基前驅物可為矽烷(silane)、三甲矽烷基胺(trisilylamine)、三甲基矽烷(trimethylsilane)以及矽氮烷(silazanes)(例如六甲基環三矽氮烷(hexamethylcyclotrisilazane))。
在一些實施例中,多個磷基前驅物可在處理製程中與該等第二前驅物一起引入。舉例來說,該等磷基前驅物可為磷化氫(phosphine)。
在一些實施例中,該等氧基前驅物、該等矽基前驅物或該等磷基前驅物可在處理製程中與該等第二前驅物一起引入。
在一些實施例中,處理製程可用一電漿製程、一紫外線固化(UV cure)製程、一熱退火(thermal anneal)製程或其組合的一輔助所執行。
當該處理以電漿製程為輔助而執行時,電漿製程的電漿係可藉由射頻功率(RF power)所提供。在一些實施例中,在介於大約100 kHz直到大約1 MHz之間的一單一低頻率下,射頻功率可介於大約2W到大約5000 W。在一些實施例中,在大於約13.6 MHz的一單一高頻率下,射頻功率可介於大約30 W到大約1000 W。在此情況下,處理製程的一基底溫度可介於大約20℃到大約1000℃之間。處理製程的一製程壓力可介於大約10 mTorr到大約760 Torr之間。
當該處理以紫外線固化製程為輔助所執行時,在此情況下,處理製程的一基底溫度可介於大約20℃到大約1000℃之間。處理製程的一製程溫度可介於大約10 mTorr到大約760 Torr之間。紫外線固化可藉由任何紫外線源所提供,例如汞微波弧燈(mercury microwave arc)、脈衝式氙閃光燈(pulsed xenon flash lamps)或高效率UV發光二極體陣列(high-efficiency UV light emitting diode arrays)。紫外線源可具有一波長,係介於大約170 nm到大約400 nm之間。紫外線源可提供一光子能量(photon energy),係介於大約0.5 eV到大約10 eV之間;在一些實施例中,係介於大約1 eV到大約6 eV之間。紫外線固化製程的輔助可從第一硬遮罩層201移除氫。當氫可擴散進入半導體元件1A的其他區域以及可能降低半導體元件1A的可靠度時,氫藉由紫外線固化製程之輔助的移除係可改善半導體元件1A的可靠度。此外,紫外線固化製程可增加第一硬遮罩層401的密度。
當該處理以熱退火製程為輔助所執行時,在此狀況下,處理製程的一基底溫度可介於大約20℃到大約1000℃之間。處理製程的一製程壓力可介於大約10 mTorr到大約760 Torr之間。
在一些實施例中,第一硬遮罩層401可由一碳膜所製。在文中所使用的術語「碳膜(carbon film)」,其係主要由多個碳原子所界定,或者是其物理和化學性質係取決於其碳含量。術語「碳膜」係指排除作為簡單混合物或包含碳之化合物的材料,舉例來說,包含碳之化合物的材料為介電材料,例如摻雜碳的氮氧化矽、摻雜碳的氧化矽或摻雜碳的多晶矽。舉例來說,這些術語確實包括石墨(graphite)、炭(charcoal)以及鹵素碳化物(halocarbons)。
在一些實施例中,碳膜藉由一製程所沉積,該製程包括引入一製程氣體混合物進入一製程腔室,該製程氣體混合物係由一或多個烴化合物(hydrocarbon compounds)。烴化合物具有一化學式C
xH
y,其中x具有介於2到4之間的一範圍,y具有介於2到10之間的一範圍。舉例來說,烴化合物可為丙烯(propylene,C
3H
6)、丙炔(propyne,C
3H
4) 、丙烷(propane,C
3H
8) 、丁烷(butane,C
4H
10) 、丁烯(butylene,C
4H
8) 、丁二烯(butadiene,C
4H
6) 、乙炔(acetylene,C
2H
2)或其組合。在一些實施例中,可以使用烴化合物的部分或完全氟化的衍生物(fluorinated derivatives)。摻雜衍生物包括烴化合物的含硼衍生物(boron-containing derivatives)及其氟化衍生物(fluorinated derivatives)。
在一些實施例中,碳膜係藉由維持在一基底溫度以從處理氣體混合物所沉積,而該基底溫度係介於大約100℃到大約700℃之間;在一些實施例中,介於大約350℃到550℃之間。在一些實施例中,碳膜係藉由維持在一腔室壓力以從處理氣體混合物所沉積,而該腔室壓力係介於大約1 Torr到大約20 Torr之間。碳膜可以一流量分別藉由引入烴氣體(hydrocarbon gas)和任何惰性或反應性氣體而從處理氣體混合物進行沉積,而該流量係介於大約50 sccm到大約2000 sccm之間。
在一些實施例中,處理氣體混合物還可包括一非活性氣體(inert gas),例如氬。然而,其可使用其他非活性氣體,例如氮或其他惰性氣體,惰性氣體係例如氦。可使用該等非活化氣體以控制碳膜的密度以及沉積率。此外,可以將多種不同氣體添加到處理氣體混合物中以改變碳膜的特性。該等氣體係可為反應氣體,例如氫、氨、氫與氮的混合物或其組合。可使用氫或氨的添加以控制碳膜之氫的比率,進而控制層特性,例如蝕刻選擇性、化學機械研磨阻力特性以及反射率(reflectivity)。在一些實施例中,可添加該等反應氣體與該等非活化氣體的一混合物到處理氣體混合物,以沉積碳膜。
碳膜可包含碳與氫原子,其係可為一可調整的碳:氫比率,係介於大約10%的氫到大約60%的氫之間。控制碳膜的氫比例係可以調節相對應的蝕刻選擇性和化學機械研磨阻力特性。當氫含量降低時,碳膜的蝕刻阻力以及選擇性係增加。當執行蝕刻製程以將所欲的圖案轉移到下層上時,碳膜移除率的降低可以使碳膜適合作為一遮罩層。
請參考圖13,一第一遮罩層403可形成在第一硬遮罩層401上。第一遮罩層43可為一光阻層。第一遮罩層403可藉由一微影製程進行圖案化。請參考圖14,可執行一蝕刻製程,例如一非等向性乾蝕刻製程,以移除第一硬遮罩層401的一些部分,且同時形成多個第一硬遮罩開孔405。在一些實施例中,蝕刻製程之第一硬遮罩層401的蝕刻率,可快於蝕刻製程之第一隔離層107的蝕刻率。舉例來說,在蝕刻製程期間,第一硬遮罩層401對第一隔離層107的蝕刻率比率,係可介於大約100:1到大約1.05:1之間、介於大約100:1到大約10:1之間、介於大約50:1到大約10:1之間、介於大約30:1到大約10:1之間、介於大約20:1到大約10:1之間,或是介於大約15:1到大約10:1之間。在一些實施例中,該等第一硬遮罩開孔405之寬度W1對第一硬遮罩開孔405之高度H1的一比率,可介於大約5:1到大約1:15之間、介於大約3:1到大約1:13之間、介於大約1:1到大約1:11之間,以及介於大約5:1到大約1:8之間。
請參考圖10、圖15以及圖16,在步驟S17,一第一組傾斜溝槽407以及一第二組傾斜溝槽409可沿第一隔離層107以形成在導電栓柱201-1、201-3之間。請參考圖15,可執行一第一傾斜蝕刻製程501,以沿第一隔離層107形成第一組傾斜溝槽407。第一傾斜蝕刻製程501可使用第一硬遮罩層401與該等第一硬遮罩開孔405當成多個圖案引導件(pattern guides)。在一些實施例中,第一傾斜蝕刻製程501的一入射角γ可由該等第一硬遮罩開孔405的寬度W1與該等第一硬遮罩開孔405的高度H1所界定。在一些實施例中,第一傾斜蝕刻製程501的入射角γ可介於大約10度到大約80度之間。在一些實施例中,第一傾斜蝕刻製程501的入射角γ可介於大約20度到大約60度之間。在一些實施例中,第一傾斜蝕刻製程501的入射角γ可介於大約20度到大約40度之間。
在一些實施例中,第一傾斜蝕刻製程501可為一非等向性蝕刻製程,例如一反應性離子蝕刻製程(reactive ion etching process)。反應性離子蝕刻製程可包括多個蝕刻劑氣體(etchant gases)以及多個鈍化氣體(passivation gases),這可能會抑制等向性效應(isotropic effect),以限制材料在水平方向上的移除。該等蝕刻劑氣體可包括氯氣(chlorine gas)以及三氯化硼(boron trichloride)。該等鈍化氣體可包括氟仿(fluoroform)或其他適合的鹵烴(halocarbons)。在一些實施例中,由碳膜所製的該等第一硬遮罩層401可以作為反應性離子蝕刻製程的該等鈍化氣體的一鹵烴源。
在一些實施例中,第一傾斜蝕刻製程501之第一隔離層107的蝕刻率,可快於第一傾斜蝕刻製程501之第一硬遮罩層401的蝕刻率。舉例來說,在第一傾斜蝕刻製程501期間,第一隔離層107對第一硬遮罩層401的蝕刻率比率,係可介於大約100:1到大約1.05:1之間、介於大約100:1到大約10:1之間、介於大約50:1到大約10:1之間、介於大約30:1到大約10:1之間、介於大約20:1到大約10:1之間,或是介於大約15:1到大約10:1之間。在一些實施例中,在第一傾斜蝕刻製程501期間,第一隔離層107對導電栓柱201-1、201-3的一蝕刻率比率,可介於大約100:1到大約1.05:1之間、介於大約100:1到大約10:1之間、介於大約50:1到大約10:1之間、介於大約30:1到大約10:1之間、介於大約20:1到大約10:1之間,或是介於大約15:1到大約10:1之間。
第一組傾斜溝槽407可沿第一方向E1延伸,而第一方向E1相對於垂直軸Z傾斜。第一組傾斜溝槽407的各側壁407SW與第一組傾斜溝槽407的各下表面407BS之間的一銳角γ’,可介於大約10度到大約80度之間。第一組傾斜溝槽407的寬度W2可小於該等第一硬遮罩開孔405的寬度W1。
請參考圖16,可執行一第二傾斜蝕刻製程503,以沿第一隔離層107形成第二組傾斜溝槽409。第二傾斜蝕刻製程503可使用第一硬遮罩層401與該等第一硬遮罩開孔405當成多個圖案引導件。在一些實施例中,第二傾斜蝕刻製程503的入射角δ可與第一傾斜蝕刻製程501相對於垂直軸Z的入射角γ相反,並可由該等第一硬遮罩開孔405的寬度W1與該等第一硬遮罩開孔405的高度H1所界定。在一些實施例中,第二傾斜蝕刻製程503的入射角δ可不同於第一傾斜蝕刻製程501的入射角γ。在一些實施例中,第二傾斜蝕刻製程503的入射角δ可介於大約-10度到大約-80度之間。
在一些實施例中,第二傾斜蝕刻製程503可為一非等向性蝕刻製程,例如一反應性離子蝕刻製程。第二傾斜蝕刻製程503之第一隔離層107的蝕刻率,可快於第二傾斜蝕刻製程503之第一硬遮罩層401的蝕刻率。舉例來說,在第二傾斜蝕刻製程503期間,第一隔離層107對第一硬遮罩層401的一蝕刻率比率,可介於大約100:1到大約1.05:1之間、介於大約100:1到大約10:1之間、介於大約50:1到大約10:1之間、介於大約30:1到大約10:1之間、介於大約20:1到大約10:1之間,或是介於大約15:1到大約10:1之間。在一些實施例中,在第二傾斜蝕刻製程503期間,第一隔離層107對導電栓柱201-1、201-3的一蝕刻率比率,可介於大約100:1到大約1.05:1之間、介於大約100:1到大約10:1之間、介於大約50:1到大約10:1之間、介於大約30:1到大約10:1之間、介於大約20:1到大約10:1之間,或是介於大約15:1到大約10:1之間。
第二組傾斜溝槽409可沿一第二方向E2延伸,而第二方向E2相對於垂直軸Z傾斜。第二方向E2與第一方向E1可交叉。在一些實施例中,第二組傾斜溝槽409的各側壁409SW與第二組傾斜溝槽409的各下表面409BS間的一銳角δ’,可介於大約-10度到大約-80度之間。在一些實施例中,第一組傾斜溝槽407與第二組傾斜溝槽409的一些部分可重疊。換言之,一些第一組傾斜溝槽407與第二組傾斜溝槽409可交叉。第二組傾斜溝槽409的寬度W3可小於該等第一硬遮罩開孔405的寬度W1。在一些實施例中,第二組傾斜溝槽409的寬度W3可相同於第一組傾斜溝槽407的寬度W2,但並不以此為限。
請參考圖10、圖17及圖18,在步驟S19,一第一組傾斜隔離層301可形成在第一組傾斜溝槽407中,以及一第二組傾斜隔離層301可形成在第二組傾斜溝槽409中。請參考圖17,可形成一層第一隔離材料411以完全填滿第一組傾斜溝槽407、第二組傾斜溝槽409以及該等第一硬遮罩開孔405,並覆蓋第一硬遮罩層401。在一些實施例中,第一隔離材料411可為不同於第一隔離層107的材料。在一些實施例中,第一隔離材料411可為一材料,具有一介電常數,該介電常數係小於第一隔離層107的介電常數。在一些實施例中,第一隔離材料411可為氮化矽、氧化矽、氮氧化矽、氧化氮化矽、流動氧化物、矽氮烷、未摻雜矽玻璃、硼二氧化矽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、電漿輔助四氧乙基矽、氟矽酸鹽玻璃、摻碳的氧化矽、有機矽酸鹽玻璃或其組合。在一些實施例中,第一隔離材料411可為一材料,該材料具有一熱膨脹係數以及一楊氏模數,熱膨脹係數係小於大約20 ppm/°C,楊氏模數係小於大約15 GPa。
請參考圖18,可執行一平坦化製程,例如化學機械研磨,直到第一隔離層107的上表面107TS暴露為止,以移除多餘材料,提供一大致平坦表面給接下來的處理步驟,且同時形成第一組傾斜隔離層301以及第二組傾斜隔離層303。
第一組傾斜隔離層301的剖面輪廓可由第一組傾斜溝槽407所界定。在一些實施例中,第一組傾斜隔離層301可沿第一方向E1延伸。第一組傾斜隔離層301的各側壁301SW與第一組傾斜隔離層301的各下表面301BS之間的一銳角γ’’,可介於大約10度到大約80度之間。
第二組傾斜隔離層303的剖面輪廓可由第二組傾斜溝槽409所界定。在一些實施例中,第二組傾斜隔離層303可沿第二方向E2延伸。第二組傾斜隔離層303的各側壁303SW與第二組傾斜隔離層303的各下表面303BS之間的一銳角δ’’,可介於大約-10度到大約-80度之間。在一些實施例中,第一組傾斜隔離層301與第二組傾斜隔離層303的一些部分係可重疊。換言之,第一組傾斜隔離層301與第二組傾斜隔離層303的一些部分係可交叉。
請參考圖10及圖19,在步驟S21,一墊層109可形成在導電栓柱201-1、201-3上。請參考圖19,可形成墊層109以覆蓋導電栓柱201-1、201-3的各上表面、第一組傾斜隔離層301的各上表面以及第二組傾斜隔離層303的各上表面。墊層109的製作技術包含一沉積製程以及一接續的光蝕刻(photo-etch)製程。沉積製程可為物理氣相沉積、化學氣相沉積、噴濺或電鍍。
圖20到圖22例示本揭露另一實施例之半導體元件1F之製備方法的流程的剖視示意圖。請參考圖20,一中間半導體可以類似於圖11到圖16所例示的一程序進行製造。一層能量可移除複合物413可完全填滿第一組傾斜溝槽407、第二組傾斜溝槽409以及該等第一硬遮罩開孔405,並覆蓋第一硬遮罩層401。能量可移除複合物413可包括一材料,例如一熱可分解材料、一光可分解材料、一電子束可分解材料或其組合。舉例來說,能量可移除複合物413可包括一基礎材料以及一可分解成孔劑材料,該可分解成孔劑材料係在暴露於一能量源時被犧牲地移除。基礎材料可包括一甲基矽倍半氧烷基(methylsilsesquioxane based)材料、低介電質材料或氧化矽。可分解成孔劑材料可包括一成孔劑有機化合物,其係提供孔隙率給能量可移除複合物413的基礎材料。在一些實施例中,能量可移除複合物413可包含大約10%的可分解成孔劑材料以及大約90%的基礎材料。在一些實施例中,能量可移除複合物413可包含大約80%的可分解成孔劑材料以及大約20%的基礎材料。
請參考圖21,可執行類似於圖18所例示的一平坦化製程。墊層109可藉由類似於如圖19所例示的一程序而形成在第一隔離層107上。
請參考圖22,一能量處理製程可藉由對其施加一能量源而執行在如圖21所例示的中間半導體上。能量源可包括熱、光或其組合。當熱使用當成能量源時,能量處理的一溫度可介於大約800℃到大約900℃之間。當光使用當成能量源時,可施加一紫外光。能量處理可從該層能量可移除複合物413而移除該可分解成孔劑材料,以產生多個空的空間(孔洞),而基礎材料係保留在原處。在能量處理之後,該層能量可移除複合物413可轉換成為多孔的第一組傾斜隔離層301與第二組傾斜隔離層303。
本揭露之一實施例提供一種半導體元件,包括一基底;二導電栓柱,位在該基底上,並沿一垂直軸延伸;一第一組傾斜隔離層,係相互平行,並位在該二導電栓柱之間;以及一第二組傾斜隔離層,係相互平行,並位在該二導電栓柱之間;其中,該第一組傾斜隔離層沿一第一方向延伸,該第一方向相對於該垂直軸傾斜;該第二組傾斜隔離層沿一第二方向延伸,該第二方向相對於該垂直軸傾斜;以及該第一方向與該第二方向係交叉。
本揭露之另一實施例提供一種半導體元件的製備方法,包括提供一基底;形成一第一隔離層在該基底上;沿著該第一隔離層形成二導電栓柱;沿著該第一隔離層形成一第一組傾斜溝槽在該二導電栓柱之間;沿著該第一隔離層形成一第二組傾斜溝槽在該二導電栓柱之間;沿一第一方向形成一第一組傾斜隔離層在該第一組傾斜溝槽中;以及沿一第二方向形成一第二組傾斜隔離層在該第二組傾斜溝槽中;其中,該第一組傾斜隔離層與該第二組傾斜隔離層係同時形成,以及該第一方向與該第二方向係交叉。
由於本揭露該半導體元件的設計,第一組傾斜隔離層301以及第二組傾斜隔離層303可用來調整導電栓柱201-1、201-3之間的介電常數。因此,係可降低導電栓柱201-1、201-3之間的寄生電容。因此,係可改善半導體元件1A效能。此外,第一組傾斜隔離層301與第二組隔離層303可增加第一隔離層107的彈性,其係在一接合製程或一佈線製程期間,可改善半導體元件1A之接合強度的電阻。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
1A:半導體元件
1B:半導體元件
1C:半導體元件
1D:半導體元件
1E:半導體元件
1F:半導體元件
1G:半導體元件
1H:半導體元件
1I:半導體元件
10:製備方法
101:基底
103:下隔離層
105:下導電層
107:第一隔離層
107BS:下表面
107TS:上表面
109:墊層
201-1:導電栓柱
201-3:導電栓柱
201-5:導電栓柱
201-7:導電栓柱
301:第一組傾斜隔離層
301BP:最低點
301BS:下表面
301SW:側壁
301TS:上表面
303:第二組傾斜隔離層
303BP:最低點
303BS:下表面
303SW:側壁
303TS:上表面
401:第一硬遮罩層
403:第一遮罩層
405:第一硬遮罩開孔
407:第一組傾斜溝槽
407BS:下表面
407SW:側壁
409:第二組傾斜溝槽
409BS:下表面
409SW:側壁
411:第一隔離材料
413:能量可移除複合物
501:第一傾斜蝕刻製程
503:第二傾斜蝕刻製程
E1:第一方向
E2:第二方向
H1:高度
S11:步驟
S13:步驟
S15:步驟
S17:步驟
S19:步驟
S21:步驟
W1:寬度
W2:寬度
W3:寬度
Z:垂直軸
α:角度
β:角度
γ:入射角
γ’:銳角
γ’’:銳角
δ:入射角
δ’:銳角
δ’’:銳角
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1例示本揭露一些實施例之半導體元件的剖視示意圖。
圖2到圖9例示本揭露一些實施例之各半導體元件的剖視示意圖。
圖10例示本揭露一些實施例之半導體元件之製備方法的流程示意圖。
圖11到圖19例示本揭露一些實施例之半導體元件之製備方法的流程的剖視示意圖。
圖20到圖22例示本揭露另一實施例之半導體元件之製備方法的流程的剖視示意圖。
1A:半導體元件
101:基底
103:下隔離層
105:下導電層
107:第一隔離層
107BS:下表面
107TS:上表面
109:墊層
201-1:導電栓柱
201-3:導電栓柱
301:第一組傾斜隔離層
301BS:下表面
301TS:上表面
303:第二組傾斜隔離層
303BS:下表面
303TS:上表面
E1:第一方向
E2:第二方向
Z:垂直軸
α:角度
β:角度
Claims (20)
- 一種半導體元件,包括: 一基底; 二導電栓柱,位在該基底上,並沿一垂直軸延伸; 一第一組傾斜隔離層,係相互平行,並位在該二導電栓柱之間;以及 一第二組傾斜隔離層,係相互平行,並位在該二導電栓柱之間; 其中,該第一組傾斜隔離層沿一第一方向延伸,該第一方向相對於該垂直軸傾斜;該第二組傾斜隔離層沿一第二方向延伸,該第二方向相對於該垂直軸傾斜;以及該第一方向與該第二方向係交叉。
- 如請求項1所述之半導體元件,還包括一第一隔離層,係位在該基底上,其中該二導電栓柱係沿該第一隔離層設置,該第一組傾斜隔離層與該第二組傾斜隔離層係位在該第一隔離層中,以及該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料係不同於該第一隔離層的材料。
- 如請求項2所述之半導體元件,其中該第一組傾斜隔離層與該第二組傾斜隔離層包含一材料,該材料具有一介電常數,係低於該第一隔離層之材料的介電常數。
- 如請求項2所述之半導體元件,其中該第一組傾斜隔離層與該第二組傾斜隔離層為多孔的。
- 如請求項4所述之半導體元件,其中該第一組傾斜隔離層與該第二組傾斜隔離層的各孔隙率,係介於大約10%到大約80%之間。
- 如請求項2所述之半導體元件,其中該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料具有一熱膨脹係數以及一楊氏模數,該熱膨脹係數係小於大約20 ppm/°C,該楊氏模數係小於大約15 GPa。
- 如請求項3所述之半導體元件,還包括一墊層,位在該二導電栓柱、該第一組傾斜隔離層以及該第二組傾斜隔離層上。
- 如請求項7所述之半導體元件,其中該第一方向與該垂直軸之間的一角度,係介於大約10度到大約80度之間。
- 如請求項7所述之半導體元件,其中該第二方向與該垂直軸之間的一角度,係介於大約-10度到大約-80度之間。
- 如請求項7所述之半導體元件,其中該第一方向與該垂直軸之間的一角度,係不同於該第二方向與該垂直軸之間的一角度。
- 如請求項7所述之半導體元件,其中該第一方向與該垂直軸之間的一角度係與該第二方向與該垂直軸之間的一角度相反。
- 如請求項7所述之半導體元件,其中該第一組傾斜隔離層的各下表面與該第二組傾斜隔離層的各下表面,係大致與該第一隔離層的一下表面為共面。
- 如請求項7所述之半導體元件,其中該第一組傾斜隔離層的各最低點與該第二組傾斜隔離層的各最低點係位在一位面處,該位面係在該第一隔離層的一下表面上。
- 一種半導體元件的製備方法,包括: 提供一基底; 形成一第一隔離層在該基底上; 沿著該第一隔離層形成二導電栓柱; 沿著該第一隔離層形成一第一組傾斜溝槽在該二導電栓柱之間; 沿著該第一隔離層形成一第二組傾斜溝槽在該二導電栓柱之間; 沿一第一方向形成一第一組傾斜隔離層在該第一組傾斜溝槽中;以及 沿一第二方向形成一第二組傾斜隔離層在該第二組傾斜溝槽中; 其中,該第一組傾斜隔離層與該第二組傾斜隔離層係同時形成,以及該第一方向與該第二方向係交叉。
- 如請求項14所述之半導體元件的製備方法,其中該第一組傾斜隔離層與該第二組傾斜隔離層係包含一材料,該材料係不同於該第一隔離層的材料。
- 如請求項14所述之半導體元件的製備方法,其中該第一組傾斜隔離層與該第二組傾斜隔離層包含一材料,該材料具有一介電常數,係低於該第一隔離層之材料的介電常數。
- 如請求項15所述之半導體元件的製備方法,其中形成該第一組傾斜溝槽的該步驟係包括: 形成一第一硬遮罩層在該第一隔離層上; 沿著該第一硬遮罩層形成多個第一硬遮罩開孔;以及 使用該第一硬遮罩層與該等第一硬遮罩開孔當作多個圖案引導件,以執行一第一傾斜蝕刻製程在該第一隔離層上,以形成該第一組傾斜溝槽。
- 如請求項17所述之半導體元件的製備方法,其中該第一硬遮罩層包含下列材料:氧化矽、氮化矽、氮氧化矽、氧化氮化矽、氮化硼、矽硼氮化物、磷硼氮化物、硼碳矽氮化物或是一碳膜。
- 如請求項18所述之半導體元件的製備方法,其中形成該第二組傾斜隔離層的該步驟,係包括:使用該第一硬遮罩層與該等第一硬遮罩開孔當作多個圖案引導件,以執行一第二傾斜蝕刻製程在該第一隔離層上,以形成該第二組傾斜溝槽,以及該第一傾斜蝕刻製程的一入射角係與該第二傾斜蝕刻製程的一入射角相反。
- 如請求項19所述之半導體元件的製備方法,其中形成該第一組傾斜隔離層的該步驟以及形成該第二組傾斜隔離層的該步驟,係包括: 形成一層能量可移除複合物在該第一組傾斜溝槽與該第二組傾斜溝槽中,且該層能量可移除複合物包括一基礎材料以及一可分解成孔劑材料;以及 執行一能量處理以轉換該層能量可移除複合物成為該第一組傾斜隔離層與該第二組傾斜隔離層。
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Also Published As
Publication number | Publication date |
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US11728299B2 (en) | 2023-08-15 |
US20220278025A1 (en) | 2022-09-01 |
US11469195B2 (en) | 2022-10-11 |
TW202226489A (zh) | 2022-07-01 |
US20220093490A1 (en) | 2022-03-24 |
CN114256144A (zh) | 2022-03-29 |
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