TW201436233A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201436233A
TW201436233A TW103100029A TW103100029A TW201436233A TW 201436233 A TW201436233 A TW 201436233A TW 103100029 A TW103100029 A TW 103100029A TW 103100029 A TW103100029 A TW 103100029A TW 201436233 A TW201436233 A TW 201436233A
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TWI527237B (zh
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Hsiang-Jen Tseng
Ting-Wei Chiang
Wei-Yu Chen
Kuo-Nan Yang
Ming-Hsiang Song
Ta-Pen Guo
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Taiwan Semiconductor Mfg
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Abstract

本發明提供一種半導體裝置及其製造方法。在一實施例中，一種半導體裝置包括：第一半導體鰭，延伸於基底上；第一源極區，設於第一半導體鰭上，第一源極區具有第一寬度；及第一汲極區，設於第一半導體鰭上，第一汲極區具有第二寬度，第二寬度與第一寬度不同。

Description

半導體裝置及其製造方法
本發明係有關於半導體裝置及其製造方法，特別係有關於一種鰭式場效電晶體及其製造方法。
電晶體係現代積體電路中的關鍵元件。為了滿足提高元件操作速度的需求，電晶體的驅動電流必須相應增大。由於驅動電流與電晶體的閘極寬度成正比，因此具有較大的閘極寬度的電晶體是較有利的。
然而，增加閘極寬度卻與減小半導體裝置尺寸的需求互相衝突，因此發展出了鰭式場效電晶體。
鰭式場效電晶體的優點為其可在不佔據更多晶片面積的條件下增加驅動電流。然而鰭式場效電晶體的微小尺寸在其製程時產生許多問題。
一種半導體裝置包括：第一半導體鰭，延伸於基底上；第一源極區，設於第一半導體鰭上，第一源極區具有第一寬度；及第一汲極區，設於第一半導體鰭上，第一汲極區具有第二寬度，第二寬度與第一寬度不同。
一種半導體裝置包括：多個第一半導體鰭，延伸於基底上；第一源極區，設於多個第一半導體鰭上，第一源極 區具有第一寬度；第一汲極區，設於多個第一半導體鰭上，第一汲極區具有第二寬度；第一源極接點，設於第一源極區上且與第一源極區電性耦合，第一源極接點具有第三寬度；及第一汲極接點，設於第一汲極區上且與第一汲極區電性耦合，第一汲極接點具有第四寬度，第四寬度小於第三寬度。
一種半導體裝置之製造方法包括：形成第一半導體鰭於基底上；形成第一源極區於第一半導體鰭上，第一源極區具有第一寬度；形成第一汲極區於第一半導體鰭上，第一汲極區具有第二寬度，第二寬度小於第一寬度；及形成第一閘極於第一半導體鰭上，第一閘極橫向設於第一源極區及第一汲極區之間。
20‧‧‧半導體基底
22‧‧‧介電層
24‧‧‧半導體鰭
28‧‧‧族群
34‧‧‧結構
37‧‧‧閘極介電層
38‧‧‧閘極
39‧‧‧閘極間隔物
40‧‧‧源極區
42‧‧‧汲極區
50‧‧‧源極接點
52‧‧‧汲極接點
54‧‧‧層間介電層
56‧‧‧閘極接點
100‧‧‧鰭式場效電晶體裝置
200‧‧‧鰭式場效電晶體裝置
W1、W2、W3、W4‧‧‧寬度
第1A及1B圖係根據一實施例所繪製之鰭式場效電晶體裝置的俯視圖及剖面圖；第2-4、5A-5B、6A-6B圖係根據一實施例所繪製之鰭式場效電晶體裝置於各製程階段的俯視圖及剖面圖；第7圖係根據另一實施例所繪製之鰭式場效電晶體裝置的俯視圖；第8圖係根據一實施例所繪製之鰭式場效電晶體裝置之製造方法的流程圖。
應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本發明之不同樣態。以下所述特定的元件及 排列方式儘為簡單描述本發明。當然，這些僅用以舉例而非本發明之限定。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。
本案之實施例將以特定的例子描述，亦即使用具有非對稱的源極及汲極結構的鰭式場效電晶體裝置描述。然而，只要是為了增快元件速度及降低寄生電阻，其它實施例可應用於其它場效電晶體。
第1A及1B圖分別為製程中間步驟中的鰭式場效電晶體裝置100的俯視圖及剖面圖。鰭式場效電晶體裝置100包括多個半導體鰭24，半導體鰭24延伸於半導體基底20上且設於介電層22中(參見第3圖)。鰭式場效電晶體裝置100更包括位於半導體鰭上的閘極38及閘極介電層37、位於半導體鰭24上的源極區40及汲極區42(參見第1B圖)、源極接點50、汲極接點52、閘極接點56及結構34。源極接點50及汲極接點52分別形成於源極區40及汲極區42上且分別與源極區40及汲極區42電性接觸。源極接點50及汲極接點52可分別使源極區40及汲極區42電性耦合至外部裝置及/或後續形成之膜層。
如第1A及1B圖所示，源極區40比汲極區42寬，源極接點50比汲極接點52寬。藉由使源極區40及源極接點50的寬 度分別大於汲極區42及汲極接點52的寬度，可減少源極結構(40及50)的寄生電阻並增進鰭式場效電晶體裝置100的操作速度。
第2-6B圖為鰭式場效電晶體裝置100的形成步驟。如第2圖所示，鰭式場效電晶體裝置100可包括兩個半導體鰭24的群組28。儘管圖中顯示各群組28具有4個半導體鰭24，此僅為作為說明之實施例，更多或更少的半導體鰭24可包括於本發明之範圍內。
第2圖顯示圖案化之半導體鰭24設於半導體基底20上。半導體基底20可包括摻雜或未摻雜的主體矽或絕緣層上覆矽(SOI)基底的主動層。一般而言，絕緣層上覆矽基底包括半導體材料的層，此半導體材料例如為Si、Ge、SiGe、絕緣層上覆矽、絕緣層上覆矽鍺(SGOI)或上述之組合。其它可用之基底包括多層基底、梯度基底(gradient substrate)或混合定向基底(hybrid orientation substrate)。
半導體基底20可包括主動元件(未顯示於第2圖)。如本技術領域中具有通常知識者所知，許多裝置，例如電晶體、電容、電阻、上述之組合及其它相似之元件可用來形成鰭式場效電晶體裝置100並得到設計的結構及功能。此裝置可藉由任何適合之方法形成。半導體鰭24可電性耦合至主動及被動裝置。由於只需要要部分半導體基底20即可完整描述本發明之實施例，因此圖式中僅顯示部分之半導體基底20。
在一實施例中，半導體鰭24可藉由圖案化半導體基底20形成。圖案化步驟可藉由沉積罩幕材料(未顯示)於半 導體基底20上完成，此罩幕材料例如為光阻或氧化矽。此罩幕材料被圖案化，接著半導體基底20根據此圖案蝕刻。得到的結構包括多個形成於半導體基底20上的半導體鰭24。各半導體鰭24具有實質上與半導體基底20的頂面正交的側壁。在某些實施例中，半導體基底20被蝕刻至特定的深度，此表示形成之半導體鰭24具有一高度。半導體鰭24可具有約1nm至約500nm的高度。在一特定的實施例中，半導體鰭24具有約50nm的高度。半導體鰭24可具有約1nm至約100nm的寬度。半導體鰭24可具有約0.01μm至約10μm的長度。在另一實施例中，半導體鰭24可於半導體基底20上的圖案化層(例如介電層)中的溝槽或開口中形成於半導體基底20的頂面上。由於此步驟為公知的技術，故此處不再詳細描述。
半導體鰭24可為半導體材料，此半導體材料例如為Si、Ge、SiGe或其它相似材料。在一實施例中，半導體鰭24為矽。接著，半導體鰭24可藉由佈植步驟將P型或N型雜質摻雜入半導體鰭24中。
第3圖顯示介電層22形成於半導體基底20及半導體鰭24上。介電層22可毯覆沉積於鰭式場效電晶體裝置100上。介電層22可為一或多個適合的介電材料，此介電材料例如為氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃、例如為碳摻雜氧化物的低介電常數介電質、例如為多孔碳摻雜二氧化矽的極低介電常數介電質、例如為聚醯亞胺的聚合物、上述之組合或其它相似材料。介電層22可藉由例如為化學氣相沉積或旋塗玻璃(spin-on-glass)步驟沉積，亦可使用其它適合之方法沉積。
第4圖顯示製程的下一個步驟，其中介電層22被薄化使其低於半導體鰭24頂面的高度。介電層22可藉由各種方式薄化。在一實施例中，介電層22可藉由多步驟的方式薄化，此方法之第一步驟包括化學機械研磨，在此步驟中介電層22產生化學反應，接著藉由研磨料研磨移除。此步驟可持續進行直到半導體鰭24的頂面露出。在下一個步驟中，可藉由各種方式將介電層22薄化並使其低於半導體鰭24的頂面。其中一種方式為具有適當製程時間的稀釋氫氟酸處理或氣相氫氟酸處理。在另一實施例中，可省略化學機械研磨步驟並選擇性地在不移除半導體鰭24的條件下薄化介電層22。此選擇性薄化步驟可藉由上述稀釋氫氟酸處理或氣相氫氟酸處理完成。
第5A及5B圖顯示形成閘極38於半導體鰭24上、形成源極區40及汲極區42於半導體鰭24上及形成結構34於半導體鰭24的端點。閘極38可包括閘極介電層37及閘極間隔物39。閘極介電層37可藉由熱氧化、化學氣相沉積、濺鍍或其它任何已知可形成閘極介電質的方法形成。在其它實施例中，閘極介電層包括具有高介電常數(k值)的介電材料，例如，具有高於3.9的介電常數的介電材料。此介電材料包括金屬氧化物，此金屬氧化物例如為Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、其它相似金屬或上述之組合的氧化物及上述之多層結構。在一實施例中，閘極介電層37係厚度為約5埃至約30埃的高介電常數介電層。
閘極層可形成於閘極介電層37上。在一實施例 中，閘極層可為均勻或非均勻摻雜之摻雜多晶矽。在另一實施例中，閘極包括N型功函數金屬，此N型功函數金屬可包括W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、zr、其它相似金屬或上述之組合。在另一實施例中，閘極包括P型功函數金屬，此P型功函數金屬可包括TiN、WN、TaN、Ru、其它相似金屬或上述之組合。在一實施例中，閘極層具有約5nm至約60nm之厚度。閘極層可藉由化學氣相沉積、濺鍍沉積或其它任何已知可沉積導電材料的技術沉積。閘極層通常具有不平坦的頂面，其可在圖案化此閘極層或閘極蝕刻前被磨平。於此製程階段，離子可引入或可不引入閘極層。例如，可藉由離子佈植引入離子。閘極層及閘極介電層37可被圖案化並形成閘極38。圖案化閘極的步驟可藉由沉積罩幕材料(未顯示)完成，此罩幕材料例如為位於閘極層上的光阻或氧化矽。接著，罩幕材料被圖案化。之後，閘極層依據此圖案被蝕刻。在一實施例中，位於各半導體鰭24的族群28上的閘極38可互相電性耦合並形成兩個半導體鰭24的族群28共用的單一閘極38。
結構34提供可以控制及/或侷限源極區40及汲極區42磊晶成長的結構。在一實施例中，結構34可為藉由與上述形成閘極38的方法相似之方法形成的虛置閘極。結構34亦可為其它任何適合之結構。
形成閘極38及結構34後，源極區40及汲極區42可形成於半導體鰭24上。源極區40可具有約30nm至約600nm的寬度W1，汲極區42可具有約20nm至約400nm的寬度W2。在一實施例中，源極區40的寬度為汲極區42的寬度的約1.2至約5倍。 源極區40及汲極區42可藉由佈植步驟摻雜適當的雜質以補足半導體鰭24中的雜質。在另一實施例中，源極區40及汲極區42可藉由於半導體鰭24中形成凹口(未顯示)並於此凹口中磊晶成長形成。源極區40及汲極區42的摻雜可藉由上述佈植方法或藉由成長材料時的臨場摻雜完成。在一實施例中，連續導電層可形成於各源極區40中的4個半導體鰭24上，並於各半導體鰭24的族群28中形成單一源極區40。此外，連續導電層可形成於各汲極區42中的4個半導體鰭24上，並於各半導體鰭24的族群28中形成單一汲極區42。
在第5A及5B圖所示之實施例中，鰭式場效電晶體28可配置為PMOS或NMOS的結構。在PMOS的結構中，半導體鰭24可摻雜N型雜質，源極區40及汲極區42可摻雜P型雜質。在NMOS的結構中，半導體鰭24可摻雜P型雜質，源極區40及汲極區42可摻雜N型雜質。
閘極間隔物39可形成於閘極38的相反側上。閘極間隔物39通常係藉由毯覆沉積間隔物層(未顯示)於先前形成的結構上的方式形成。此間隔物層可包括氮化矽、氮氧化物、SiC、氮氧化矽、氧化物、其它相似材料或上述之組合。此間隔物層可藉由形成此類膜層的方法形成，例如化學氣相沉積、電漿輔助化學氣相沉積、濺鍍及其它本技術領域已知的方法。接著，閘極間隔物39被圖案化，並較佳地藉由非等向性蝕刻以移除此結構中水平表面上的間隔物層。
在另一實施例中，源極區40及汲極區42可包括輕摻雜區及重摻雜區。在本實施例中，可於閘極間隔物39形成之 前輕摻雜源極區40及汲極區42。接著，於閘極間隔物39形成之後，重摻雜源極區40及汲極區42。此方法可形成輕摻雜區及重摻雜區。此輕摻雜區主要位於閘極間隔物之下，而此重摻雜區主要位於沿著半導體鰭24的方向上的閘極間隔物之外。
第6A及6B圖顯示形成源極接點50於源極區40上、形成汲極接點52於汲極區42上及形成閘極接點56於閘極38上。源極接點50可將源極區40電性耦合至電源節點、接地節點或主動及/或被動裝置(未顯示)。汲極接點52可將汲極區42電性耦合至主動及/或被動裝置元件(未顯示)。閘極接點56可將閘極38電性耦合至偏壓節點以控制鰭式場效電晶體裝置100。
源極接點50、汲極接點52及閘極接點56可設於層間介電層54中。源極接點50可具有約15nm至約600nm的寬度W3。汲極接點52可具有約10nm至約400nm的寬度W4。在一實施例中，源極接點50的寬度為汲極接點52的寬度的約1.2至約5倍。較寬的源極結構(40及50)可減少寄生電阻並增進鰭式場效電晶體裝置100的操作速度。在層間介電層54形成之前，可形成蝕刻停止層(未顯示)於介電層22、源極區40、汲極區42、閘極38及半導體鰭24的頂面上。蝕刻停止層可順應性地沉積於半導體基底20上的元件上。在一實施例中，蝕刻停止層為氮化矽、氧化矽、碳化矽、其它相似材料或上述之組合。蝕刻停止層可藉由化學氣相沉積、流動式化學氣相沉積、其它相似方法或上述之組合形成。
層間介電層54可形成於蝕刻停止層上。在一實施例中，層間介電層54可為氧化矽、氮化物、其它相似材料或上 述之組合。層間介電層54可藉由化學氣相沉積、高密度電漿(HDP)、其它相似方法或上述之組合形成。此外，沉積層間介電層54之後，此層間介電層54可藉由例如為化學機械研磨的方法磨平。
在形成層間介電層54之後，開口可藉由蝕刻穿過層間介電層54及蝕刻停止層並蝕刻至源極區40、汲極區42及閘極38形成。開口可藉由可接受之微影技術，例如單鑲嵌或雙鑲嵌製程。應瞭解的是，可接受之微影技術可使用第一蝕刻劑蝕刻該層間介電層54，並使用第二蝕刻劑蝕刻該蝕刻停止層。接著，源極接點50、汲極接點52及閘極接點56可形成於開口中。例如，形成源極接點50、汲極接點52及閘極接點56的方法可包括沉積阻擋層，接著沉積導電材料於開口中。此阻擋層例如為TiN、TaN、WN、Ru、其它相似金屬或上述之組合。此導電材料例如為Al、Cu、W、其它相似金屬或上述之組合。例如，沉積方法可為化學氣相沉積、原子層沉積、物理氣相沉積、其它相似方法或上述之組合。多餘之阻擋層及/或導電材料可藉由例如為化學機械研磨的方法移除。
第7圖顯示另一鰭式場效電晶體裝置200之實施例，其中各半導體鰭24的族群28包括4個閘極38、三個源極區40、三個源極接點50、兩個汲極區42及兩個汲極接點52。在此配置中，可使四個分離的電晶體被利用且每個閘極38插入於源極區40及汲極區42之間。如上所述，源極區40可比汲極區42寬。在一實施例中，源極區40的寬度可為汲極區42的寬度的約1.2至約5倍。
第8圖係根據一實施例所繪製之鰭式場效電晶體裝置之製造方法800的流程圖。儘管方法800以一系列動作或項目揭示並描述於下，應瞭解的是此處揭示的動作或項目揭的順序並非用來限制本發明。例如，某些動作可以不同之順序進行及/或與其它未於此揭示及/或描述之動作或項目一同進行。此外，並非所有此處揭示之動作皆需要進行。更進一步，一或多個此處描述之動作可用一或多個分離的動作及/或階段進行。
在步驟802中，半導體鰭形成於基底上。步驟802顯示於第2圖中。
在步驟804中，介電層形成於半導體鰭上。步驟804顯示於第3圖中。
在步驟806中，介電層被薄化使其低於半導體鰭的頂面。步驟806顯示於第4圖中。
在步驟808中，閘極介電層形成於半導體鰭上。在步驟810中，閘極形成於半導體鰭上。在步驟812中，源極區及汲極區形成於半導體鰭上。在步驟814中，閘極間隔物形成於閘極的相反側上。步驟808、810、812及814顯示於第5A及5B圖中。
在步驟816中，層間介電層形成於半導體鰭、閘極、源極區、汲極區及基底上。在步驟818中，開口形成於層間介電層中並延伸至源極區、汲極區及閘極。在步驟820中，源極接點及汲極接點形成於開口中且分別位於源極區及汲極區上。步驟816、818及820顯示於第6A及6B圖中。
藉由使源極區40的寬度大於汲極區42的寬度，及 源極接點50的寬度大於汲極接點52的寬度，源極結構(40及50)可減少寄生電阻並增進鰭式場效電晶體裝置100的操作速度。實驗顯示源極結構(40及50)對寄生電阻的敏感度為汲極結構(42及52)的10倍。因此，藉由降低源極結構(40及50)的寄生電阻可增進鰭式場效電晶體裝置100的操作速度。
雖然本發明的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。此外，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本發明使用。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成分別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
24‧‧‧半導體鰭
34‧‧‧結構
38‧‧‧閘極
50‧‧‧源極接點
52‧‧‧汲極接點
54‧‧‧層間介電層
100‧‧‧鰭式場效電晶體裝置
W3、W4‧‧‧寬度

Claims (10)

  1. 一種半導體裝置，包括：一第一半導體鰭，延伸於一基底上；一第一源極區，設於該第一半導體鰭上，該第一源極區具有一第一寬度；及一第一汲極區，設於該第一半導體鰭上，該第一汲極區具有一第二寬度，該第二寬度與該第一寬度不同。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一寬度大於該第二寬度。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第一寬度為該第二寬度的1.2至5倍。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括：一第一源極接點，設於該第一源極區上且與該第一源極區電性耦合，該第一源極接點具有一第三寬度；及一第一汲極接點，設於該第一汲極區上且與該第一汲極區電性耦合，該第一汲極接點具有一第四寬度，該第四寬度與該第三寬度不同。
  5. 如申請專利範圍第4項所述之半導體裝置，其中該第三寬度為該第四寬度的1.2至5倍。
  6. 如申請專利範圍第1項所述之半導體裝置，更包括一第一閘極，設於該第一半導體鰭上，其中該第一閘極插入該第一源極區及該第一汲極區之間。
  7. 如申請專利範圍第1項所述之半導體裝置，更包括：一第二半導體鰭，延伸於該基底上，該第二半導體鰭與該 第一半導體鰭平行；一第二源極區，設於該第二半導體鰭上，該第二源極區具有該第一寬度；一第二汲極區，設於該第二半導體鰭上，該第二汲極區具有該第二寬度；及一第二閘極，設於該第二半導體鰭上，其中該第二閘極插入該第二源極區及該第二汲極區之間。
  8. 如申請專利範圍第7項所述之半導體裝置，更包括：一第二源極接點，設於該第二源極區上且與該第二源極區電性耦合，該第二源極接點具有一第三寬度；及一第二汲極接點，設於該第二汲極區上且與該第二汲極區電性耦合，該第二汲極接點具有一第四寬度，該第三寬度大於該第四寬度。
  9. 一種半導體裝置之製造方法，包括：形成一第一半導體鰭於一基底上；形成一第一源極區於該第一半導體鰭上，該第一源極區具有一第一寬度；形成一第一汲極區於該第一半導體鰭上，該第一汲極區具有一第二寬度，該第二寬度小於該第一寬度；及形成一第一閘極於該第一半導體鰭上，該第一閘極橫向設於該第一源極區及該第一汲極區之間。
  10. 如申請專利範圍第9項所述之半導體裝置之製造方法，更包括：形成一第一源極接點於該第一源極區上且與該第一源極區 電性接觸，該第一源極接點具有一第三寬度；及形成一第一汲極接點於該第一汲極區上且與該第一汲極區電性接觸，該第一汲極接點具有一第四寬度，其中該第三寬度為該第四寬度的1.2至5倍。
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