CN104037226A - 具有非对称源极/漏极结构的FinFET及其制造方法 - Google Patents

具有非对称源极/漏极结构的FinFET及其制造方法 Download PDF

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CN104037226A
CN104037226A CN201310236958.6A CN201310236958A CN104037226A CN 104037226 A CN104037226 A CN 104037226A CN 201310236958 A CN201310236958 A CN 201310236958A CN 104037226 A CN104037226 A CN 104037226A
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semiconductor fin
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CN104037226B (zh
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曾祥仁
江庭玮
陈威宇
杨国男
宋明相
郭大鹏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例为一种半导体器件、一种FinFET器件以及一种形成FinFET器件的方法。一种实施例为一种半导体器件，包括在衬底上方延伸的第一半导体鳍、在第一半导体鳍上的第一源极区以及在第一半导体鳍上的第一漏极区。第一源极区具有第一宽度并且第一漏极区具有与第一宽度不同的第二宽度。本发明还公开了一种具有非对称源极/漏极结构的FinFET及其制造方法。

Description

具有非对称源极/漏极结构的FinFET及其制造方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种具有非对称源极/漏极结构的FinFET及其制造方法。
背景技术
晶体管是现代集成电路的关键组件。为满足逐渐更快速度的要求，晶体管的驱动电流需要逐渐增大。由于晶体管的驱动电流与晶体管的栅极宽度成比例，因此优选具有更大宽度的晶体管。
然而，栅极宽度的增加与减小半导体器件的尺寸的要求相冲突。因此开发出了鳍式场效应晶体管（FinFET）。
FinFET的引入具有在不占用更多片上面积的情况下增加驱动电流的有利特点。然而，FinFET晶体管的小尺寸引起了在它们的制造和生产期间的各种问题。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：
在衬底上方延伸的第一半导体鳍；
位于所述第一半导体鳍上的第一源极区，所述第一源极区具有第一宽度；以及
位于所述第一半导体鳍上的第一漏极区，所述第一漏极区具有不同于所述第一宽度的第二宽度。
在可选实施例中，所述第一宽度大于所述第二宽度。
在可选实施例中，所述第一宽度比所述第二宽度大大约1.2至大约5倍。
在可选实施例中，所述半导体器件还包括：位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及，位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有不同于所述第三宽度的第四宽度。
在可选实施例中，所述第三宽度比所述第四宽度大大约1.2至大约5倍。
在可选实施例中，所述第一源极接触部和所述第一漏极接触部包括选自基本上由铝、铜、钨和它们的组合所组成的组中的材料。
在可选实施例中，所述第一源极区和所述第一漏极区都包括外延层。
在可选实施例中，所述半导体器件还包括位于所述第一半导体鳍上方的第一栅极，其中，所述第一栅极置于所述第一源极区和所述第二源极区之间。
在可选实施例中，所述半导体器件还包括：在所述衬底上方延伸的第二半导体鳍，所述第二半导体鳍与所述第一半导体鳍平行；位于所述第二半导体鳍上的第二源极区，所述第二源极区具有所述第一宽度；位于所述第二半导体鳍上的第二漏极区，所述第二漏极区具有所述第二宽度；以及，位于所述第二半导体鳍上方的第二栅极，其中，所述第二栅极置于所述第二源极区和所述第二漏极区之间。
在可选实施例中，所述半导体器件还包括：位于所述第二源极区上方并与所述第二源极区电连接的第二源极接触部，所述第二源极接触部具有第三宽度；以及，位于所述第二漏极区上方并与所述第二漏极区电连接的第二漏极接触部，所述第二漏极接触部具有大于所述第三宽度的第四宽度。
根据本发明的另一方面，还提供了一种FinFET器件，包括：
在衬底上方延伸的多个第一鳍；
位于所述多个第一鳍上的第一源极区，所述第一源极区具有第一宽度；
位于所述多个第一鳍上的第一漏极区，所述第一漏极区具有第二宽度；
位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及
位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有小于所述第三宽度的第四宽度。
在可选实施例中，所述第三宽度比所述第四宽度大大约1.2至大约5倍。
在可选实施例中，所述第一宽度比所述第二宽度大大约1.2至大约5倍。
在可选实施例中，所述FinFET器件还包括：在所述衬底上方延伸的多个第二鳍，所述多个第二鳍与所述多个第一鳍平行；位于所述多个第二鳍上的第二源极区，所述第二源极区具有所述第一宽度；以及，位于所述多个第二鳍上的第二漏极区，所述第二漏极区具有所述第二宽度。
在可选实施例中，所述FinFET器件还包括：位于所述第二源极区上方并与所述第二源极区电连接的第二源极接触部，所述第二源极接触部具有所述第三宽度；以及，位于所述第二漏极区上方并与所述第二漏极区电连接的第二漏极接触部，所述第二漏极接触部具有所述第四宽度。
在可选实施例中，所述FinFET器件还包括：位于所述多个第一鳍上方的第一栅极，其中，所述第一栅极置于所述第一源极区和所述第一漏极区之间；以及，位于所述多个第二鳍上方的第二栅极，其中，所述第二栅极置于所述第二源极区和所述第二漏极区之间。
在可选实施例中，所述FinFET器件还包括：位于所述多个第一鳍上方的第一栅极，其中，所述第一栅极置于所述第一源极区和所述第一漏极区之间；位于所述多个第一鳍上的第三源极区，所述第三源极区具有所述第一宽度；位于所述多个第一鳍上方的第三栅极，其中，所述第三栅极置于所述第一漏极区和所述第三源极区之间；位于所述多个第一鳍上的第三漏极区，所述第三漏极区具有所述第二宽度；位于所述多个第一鳍上方的第四栅极，其中，所述第四栅极置于所述第三源极区和所述第三漏极区之间；位于所述多个第一鳍上的第四源极区，所述第四源极区具有所述第一宽度；以及，位于所述多个第一鳍上方的第五栅极，其中，所述第五栅极置于所述第三漏极区和所述第四源极区之间。
根据本发明的又一方面，还提供了一种用于形成FinFET器件的方法，所述方法包括：
在衬底上方形成第一半导体鳍；
在所述第一半导体鳍上形成第一源极区，所述第一源极区具有第一宽度；
在所述第一半导体鳍上形成第一漏极区，所述第一漏极区具有小于所述第一宽度的第二宽度；以及
在所述第一半导体鳍上方形成第一栅极，所述第一栅极横向位于所述第一源极区和所述第一漏极区之间。
在可选实施例中，形成所述第一源极区还包括在所述第一半导体鳍上外延生长所述第一源极区，并且形成所述第一漏极区还包括在所述第一半导体鳍上外延成长所述第一漏极区。
在可选实施例中，所述方法还包括：形成位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及，形成位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有第四宽度，其中，所述第三宽度比所述第四宽度大大约1.2至大约5倍。
附图说明
为更完整的理解本发明实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1A和1B示出了根据实施例的FinFET器件的俯视图和横截面图；
图2至图6B以俯视图和横截面视图示出了根据实施例的制造FinFET器件的多个阶段；
图7以俯视图示出了根据另一实施例的FinFET器件；以及
图8示出了根据实施例的用于制造FinFET器件的方法流程图。
具体实施方式
现详细说明随附图示出的实施例。只要可能，附图和说明书中使用相同的附图标记以指代相同或相似的部分。在附图中，为了清楚和简明的目的，可能增大形状和厚度。说明书将特别指向形成根据本发明的方法和装置部分的元件，或与根据本发明的方法和设备直接相配合的元件。可以理解，没有特别示出或描述的元件可采用本领域技术人员熟知的多种形式。一旦知晓本公开内容，对本领域技术人员来讲，许多替代选择和修改将变得明显。
本说明书中提及的“一个实施例”或“实施例”意味着所描述的与该实施例相关的特定的特征、结构或特性被包括在至少一个实施例中。因此，整个说明书中多处出现的“在一个实施例中”或“在实施例中”并不必须都指代相同的实施例。此外，特定的特征、结构或特性可以任何适合的方式相结合在一个或多个实施例中。优选地，附图并非按比例绘制，而是仅做示例的目的。
将针对特殊环境描述实施例，也即具有非对称源极/漏极结构的FinFET及其制造方法。然而，为了速度增加和/或寄生电阻减小的目的，其他实施例也可应用至其他的晶体管器件。
图1A和1B分别示出了在工艺的中间阶段的FinFET器件100的俯视图和横截面图。FinFET器件100包括在半导体衬底20上方延伸并被设置在介电层22中的多个半导体鳍24（参见图3）。半导体器件100还包括半导体鳍上方的栅极38和栅极介电层37、半导体鳍24上的源极区40和漏极区42（参见图1B）、源极接触部50、漏极接触部52、栅极接触部56、以及结构34。源极接触部50和漏极接触部52分别形成在源极区40和漏极区42上方，并且分别与源极区40和漏极区42电接触。源极接触部50和漏极接触部52可将源极区40和漏极区42分别电连接至外部器件和/或后续形成的层。
如图1A和1B所示，源极区40比漏极区42宽，源极接触部50比漏极接触部52宽。由于具有比漏极区42和漏极接触部52宽的源极区40和源极接触部50，源极结构（40和50）的寄生电阻可被减小，这可增加FinFET器件100的速度。
图2至图6B示出了FinFET器件100的形成。如图2所述，FinFET器件100可包括两组28半导体鳍24。尽管示出每组28具有四个半导体鳍24，但这仅是示例性实施例，更多或更少的半导体鳍24也包括在本发明的范围之内。
图2示出了半导体衬底20上的半导体鳍24的图案化。半导体衬底20可包括掺杂或不掺杂的块状硅、或绝缘体上硅（SOI）衬底的有源层。通常地，SOI衬底包括半导体材料层，半导体材料可以是诸如硅、锗、硅锗、SOI、绝缘体上硅锗（SGOI）或它们的组合。可用的其他衬底包括多层衬底、梯度衬底，或混合取向衬底。
半导体衬底20可包括有源器件（图2中未示出）。本领域普通技术人员将知道，诸如晶体管、电容器、电阻器以及它们的组合等的广泛的多种器件可被用于产生符合FinFET器件100的结构和功能要求的设计。器件可使用任何适合的方法形成。半导体鳍24可电连接至有源器件和无源器件。图中仅示出了半导体衬底20的一部分，因为这足够充分描述示例性实施例。
在实施例中，可通过图案化半导体衬底20来形成半导体鳍24。可通过在半导体衬底20上沉积诸如光刻胶或硅氧化物的掩模材料来执行图案化工艺。然后将掩模材料图案化并根据该图案蚀刻半导体衬底20。所得到的结构包括形成在半导体衬底20上的多个半导体鳍24。多个半导体鳍24中的每个具有与半导体衬底20的顶面大致垂直的侧壁。在一些实施例中，半导体衬底20被蚀刻至特定深度，意味着半导体鳍24形成至特定高度，半导体鳍24可具有大约1nm至大约500nm的高度。在一个特定实施例中，半导体鳍24形成为具有大约110nm的高度。半导体鳍24可具有大约1nm至100nm的宽度。半导体鳍24可具有大约0.01nm至10nm的长度。在可选实施例中，半导体鳍24可从半导体衬底20的顶面外延生长，并且位于形成在半导体衬底顶上的图案化层（例如，介电层）中的沟槽或开口内。由于现有技术中上述工艺是已知的，因此在此不再赘述细节。
半导体鳍24可由诸如硅、锗、硅锗等的半导体材料形成。在实施例中，半导体鳍24为硅。然后，可通过注入工艺来掺杂半导体鳍24以将p型或n型杂质引入到半导体鳍24中。
图3示出了半导体衬底20和半导体鳍24上的介电层22的形成。介电层22可均厚沉积在FinFET器件100上。介电层22由一种或多种适合的介电材料形成，诸如氧化硅、氮化硅、氮氧化硅、掺杂氟化物的硅酸盐玻璃（FSG）、低k电介质（诸如掺杂碳氧化物）、极低k电介质（诸如掺杂多孔碳的二氧化硅）、聚合物（诸如聚酰亚胺）以及它们的组合等。介电层22可通过诸如化学汽相沉积（CVD）或旋涂玻璃工艺的工艺来沉积，然而也可利用任何可接受的工艺。
图4示出了制造工艺中的接下来的步骤，其中介电层被减薄以降低半导体鳍24的顶部水平。介电层22可以多种方式背面减薄。在一个实施例中，使用具有包括化学机械抛光（CMP）的第一步骤的多步骤工艺，在该步骤中介电层22进行反应并在之后使用研磨料研磨。可继续该工艺直到半导体衬底的顶部露出为止。将介电层22减薄至半导体鳍24的顶部之下的下一步骤可以多种方式来进行。一个这样的方法是通过稀释氢氟酸（DHF）处理或汽相氢氟酸（VHF）处理一段适合的时间。在另一实施例中，可跳过CMP工艺步骤并可在不移去半导体鳍24的情况下选择性地背面减薄介电层22。可通过上述DHF处理或VHF处理来进行选择性地减薄。
图5A和5B示出了在半导体鳍24上方形成栅极38，在半导体鳍24上形成源极区40和漏极区42，以及在半导体鳍24的端部形成结构34。栅极38可包括栅极介电层37和栅极间隔件39。栅极介电层37可通过热氧化、CVD、溅射或任何已知的、用于形成栅极电介质领域的其他方法来形成。在其他实施例中，栅极介电层包括具有高介电常数（k值）的介电材料，例如大于3.9。材料可包括金属氧化物，诸如Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu等的氧化物，或者它们的组合以及它们的多层。在实施例中，栅极介电层37是具有厚度在大约5埃至大约30埃的高k介电层。
栅极电极层可形成于栅极介电层37上方。在实施例中，栅极电极层可为均匀或非均匀掺杂的掺杂多硅。在另一实施例中，栅极电极层可包括n型功函数金属。n型功函数金属可包括W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Zr等，或它们的组合。在另一实施例中，栅极电极层可包括p型功函数金属。p型功函数金属可包括TiN、WN、TaN、Ru等、或它们的组合。在实施例中，可形成具有厚度为大约20nm至大约60nm的栅极电极层。栅极电极层可通过CVD、溅射沉积或其他本领域已知或用来沉积传导材料的方法来沉积。栅极电极层的顶面通常具有非平坦的顶面，并可在图案化栅极电极层或蚀刻栅极之前被平坦化。在这点上，离子可被引入或可不被引入栅极电极层。例如，可通过离子注入技术来引入离子。可图案化栅极电极层和栅极介电层37以形成栅极38。栅极图案化工艺可通过在栅极电极层上方沉积诸如光刻胶或氧化硅的掩模材料（未示出）来实现。然后图案化掩模材料并根据该图案蚀刻栅极电极层。在实施例中，在半导体鳍24的每组28上的栅极38可电连接在一起以形成用于半导体鳍24的两个组28的单个栅极38。
结构34可提供使源极区40和漏极区42的外延生长被控制和/或限制的结构。在实施例中，结构34可为以与上述的栅极38类似的方式形成的伪栅极，然而也可利用任何适合的结构。
在形成栅极38和结构34之后，可在半导体鳍24上形成源极区40和漏极区42。源极区40可形成为具有大约30nm至大约600nm的宽度W1。漏极区42可形成为具有大约20nm至大约400nm的宽度W2。在实施例中，源极区40可比漏极区42宽大约1.2至大约5倍。可通过实施注入工艺注入适合的掺杂剂来对源极区40和漏极区42进行掺杂以在半导体鳍24中补充掺杂剂。在另一实施例中，可通过在半导体鳍24中形成凹槽（未示出）并在凹槽中外延生长材料来形成源极区40和漏极区42。可通过上述的注入方法，或通过材料生长的原位掺杂来对源极区40和漏极区42进行掺杂。在实施例中，连续导电层可覆在每个源极区40中的四个半导体鳍24上方，以在半导体鳍24的每组28中形成单个源极区40。进一步地，连续导电层可覆在每个漏极区42中的四个半导体鳍24的上方，以在半导体鳍24的每组28中形成单个漏极区42。
在图5A和5B示出的实施例中，FinFET28可构建为PMOS或NMOS结构。在PMOS结构中，半导体鳍24可掺杂n型掺杂剂并且源极区40和漏极区42可掺杂p型掺杂剂。在NMOS结构中，半导体鳍24可掺杂p型掺杂剂并且源极区40和漏极区42可掺杂n型掺杂剂。
栅极间隔件39可形成在栅极38的相对侧。典型地，通过在之前形成的结构上均厚沉积间隔件层（未示出）来形成栅极间隔件39。间隔件层可包括SiN、氮氧化物、SiC、SiON、氧化物等，或它们的组合，并且可通过利用以形成这样的层的方法来形成，诸如CVD、等离子体增强CVD、溅射以及其他本领域已知的方法。然后图案化栅极间隔件39，优选通过各向异性蚀刻从该结构的水平表面移除间隔件层。
在另一实施例中，源极区40和漏极区42包括轻掺杂区和重掺杂区。在该实施例中，在形成栅极间隔件39之前，可轻掺杂源极区40和漏极区42。在形成栅极间隔件之后，然后可重掺杂源极区40和漏极区42。这形成了轻掺杂区和重掺杂区。轻掺杂区主要是在栅极间隔件的下面，而重掺杂区在栅极间隔件的外部并且沿着半导体鳍24。
图6A和6B示出了在源极区40上方形成源极接触部50，在漏极区42上方形成漏极接触部52，在栅极38上方形成栅极接触部56。源极接触部50可将源极区40电连接至电源节点、接地节点、或有源和/或无源器件（未示出）。漏极接触部52可将漏极区42电连接至有源和/或无源器件（未示出）。栅极接触部56可将栅极38电连接至偏压节点以控制FinFET器件100。
源极接触部50、漏极接触部52，以及栅极接触部56可设置在层间电介质（ILD）54中。源极接触部50可形成为具有大约15nm至大约600nm的宽度W3。漏极接触部52可形成为具有大约10nm至大约400nm的宽度W4。在实施例中，源极接触部50可比漏极接触部52宽大约1.2至大约5倍。较宽的源极结构（40和50）可减少寄生电阻，并因此提高FinFET器件100的性能。在形成ILD54之前，可在介电层22、源极区40、漏极区42、栅极38以及半导体鳍24的顶面上方形成蚀刻停止层（ESL）（未示出）。ESL可共形地沉积在半导体衬底20上的组件上方。在实施例中，ESL为氮化硅、氧化硅、碳化硅等，或它们的组合。可通过CVD、流动CVD等或它们的组合来形成ESL。
ILD54可形成在ESL上方。在实施例中，ILD54为氧化硅、氮化物等，或它们的组合。可通过CVD、高密度等离子体（HDP）等或它们的组合来形成ILD54。此外，在沉积ILD54之后，ILD54可被平坦化，例如通过使用CMP。
在形成ILD54之后，可蚀刻开口以穿过ILD54和ESL至源极区40、漏极区42和栅极38。可使用可接受的光刻技术，诸如单或双镶嵌工艺来蚀刻开口。注意，可接受的光刻技术可使用第一蚀刻剂来蚀刻穿过ILD54并且可使用第二蚀刻剂来蚀刻穿过ESL。然后，源极接触部50、漏极接触部52，以及栅极接触部56可形成在开口中。形成源极接触部50、漏极接触部52和栅极接触部56可包括例如沉积诸如氮化钛、氮化钽、氮化钨、钌等或它们的组合的阻挡层，然后在开口中沉积诸如铝、铜、钨等金属或它们的组合的导电材料。沉积可通过例如CVD、ALD、物理汽相沉积（PVD）等或它们的组合。可通过例如CMP来去除多余的阻挡层材料和/或传导材料。
图7示出FinFET器件200的另一实施例，其中半导体鳍24的每组28包括四个栅极38、三个源极区40、三个源极接触部50、两个漏极区42以及两个漏极接触部52。该结构可允许利用四个单独的晶体管，其中每个栅极38插入在源极区40和漏极区42之间。如上文所述，源极区40可形成为比漏极区42宽。在实施例中，源极区40可比漏极区42宽大约1.2至大约5倍。
图8示出根据实施例的用于制造FinFET器件的方法800的流程图。虽然以下以动作或事件来示出并描述方法800，但应当理解这些动作或事件的所示出的顺序并不限于特定实施例。例如，与此处所示出和/或描述的动作或事件不同，一些动作可按照不同的顺序和/或与其它的动作或事件同时发生。此外，并非所有示出的动作对实施此处说明书的实施例的一个或多个方面是必须的。进一步地，一个或多个此处描述的动作可在一个或多个单独的动作和/或阶段中实施。
在步骤802，在衬底上方形成半导体鳍。步骤802在图2中被示出。
在步骤804，在半导体鳍上方形成介电层。步骤804在图3中被示出。
在步骤806，减薄介电层至在半导体鳍的顶部之下。步骤806在图4中被示出。
在步骤808，在半导体鳍上方形成栅极介电层。在步骤810，在半导体鳍上方形成栅极。在步骤812，在半导体鳍上形成源极区和漏极区。在步骤814，在栅极的相对侧形成栅极间隔件。在图5A和5B中示出步骤808、810、812和814。
在步骤816中，在半导体鳍、源极区、漏极区和衬底上方形成ILD。在步骤818，在ILD中形成开口至源极区、漏极区和栅极。在步骤820，源极接触部和漏极接触部分别形成在开口中并且位于源极区和漏极区上方。在图6A和6B中示出步骤816、818和820。
通过形成比漏极区42宽的源极区40并形成比漏极接触部52宽的源极接触部50，可降低源极结构（40和50）的寄生电阻，这可增加FinFET器件100的速度。实验表明相比于漏极结构（42和52），源极结构（40和50）对寄生电阻具有十倍以上的敏感度。因此，通过减少源极结构（40和50）的寄生电阻，可提高FinFET器件的速度。
一个实施例为半导体器件，该半导体器件包括在衬底上方延伸的第一半导体鳍、在第一半导体鳍上的第一源极区、以及在第一半导体鳍上的第一漏极区。第一源极区具有第一宽度并且第一漏极区具有第二宽度，并且第二宽度与第一宽度不同。
另一实施例为FinFET器件，该FinFET器件包括在衬底上方延伸的多个第一鳍、在多个第一鳍上的第一源极区，以及在多个第一鳍上的第一漏极区，第一源极区具有第一宽度，第二漏极区具有第二宽度。FinFET器件还包括在第一源极区上方并且电连接至第一源极区的第一源极接触部、以及在第一漏极区上方并且电连接第一漏极区的第一漏极接触部，其中，第一源极接触部具有第三宽度，第一漏极接触部具有第四宽度，第四宽度小于第三宽度。
又一实施例是一种用于形成FinFET器件的方法，该方法包括在衬底上方形成第一半导体鳍，在第一半导体鳍上形成第一源极区，在第一半导体鳍上形成第一漏极区，并且在第一半导体鳍上形成第一栅极，该第一栅极横向位于第一源极区和第一漏极区之间。第一源极区具有第一宽度，第一漏极区具有第二宽度，第二宽度小于第一宽度。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (10)

1.一种半导体器件，包括：
在衬底上方延伸的第一半导体鳍；
位于所述第一半导体鳍上的第一源极区，所述第一源极区具有第一宽度；以及
位于所述第一半导体鳍上的第一漏极区，所述第一漏极区具有不同于所述第一宽度的第二宽度。
2.根据权利要求1所述的半导体器件，其中，所述第一宽度大于所述第二宽度。
3.根据权利要求1所述的半导体器件，其中，所述第一宽度比所述第二宽度大大约1.2至大约5倍。
4.根据权利要求1所述的半导体器件，还包括：
位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及
位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有不同于所述第三宽度的第四宽度。
5.一种FinFET器件，包括：
在衬底上方延伸的多个第一鳍；
位于所述多个第一鳍上的第一源极区，所述第一源极区具有第一宽度；
位于所述多个第一鳍上的第一漏极区，所述第一漏极区具有第二宽度；
位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及
位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有小于所述第三宽度的第四宽度。
6.根据权利要求5所述的FinFET器件，其中，所述第三宽度比所述第四宽度大大约1.2至大约5倍。
7.根据权利要求5所述的FinFET器件，其中，所述第一宽度比所述第二宽度大大约1.2至大约5倍。
8.一种用于形成FinFET器件的方法，所述方法包括：
在衬底上方形成第一半导体鳍；
在所述第一半导体鳍上形成第一源极区，所述第一源极区具有第一宽度；
在所述第一半导体鳍上形成第一漏极区，所述第一漏极区具有小于所述第一宽度的第二宽度；以及
在所述第一半导体鳍上方形成第一栅极，所述第一栅极横向位于所述第一源极区和所述第一漏极区之间。
9.根据权利要求8所述的方法，其中，形成所述第一源极区还包括在所述第一半导体鳍上外延生长所述第一源极区，并且形成所述第一漏极区还包括在所述第一半导体鳍上外延成长所述第一漏极区。
10.根据权利要求8所述的方法，还包括：
形成位于所述第一源极区上方并与所述第一源极区电连接的第一源极接触部，所述第一源极接触部具有第三宽度；以及
形成位于所述第一漏极区上方并与所述第一漏极区电连接的第一漏极接触部，所述第一漏极接触部具有第四宽度，其中，所述第三宽度比所述第四宽度大大约1.2至大约5倍。
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