WO2018199999A1 - Microelectronic transistor source/drain formation using angled etching - Google Patents

Microelectronic transistor source/drain formation using angled etching Download PDF

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Publication number
WO2018199999A1
WO2018199999A1 PCT/US2017/030222 US2017030222W WO2018199999A1 WO 2018199999 A1 WO2018199999 A1 WO 2018199999A1 US 2017030222 W US2017030222 W US 2017030222W WO 2018199999 A1 WO2018199999 A1 WO 2018199999A1
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WO
WIPO (PCT)
Prior art keywords
doped region
gate
forming
transistor
sidewall
Prior art date
Application number
PCT/US2017/030222
Other languages
French (fr)
Inventor
Seung Hoon Sung
Marko Radosavljevic
Han Wui Then
Sansaptak DASGUPTA
Original Assignee
Intel Corporation
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Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/030222 priority Critical patent/WO2018199999A1/en
Publication of WO2018199999A1 publication Critical patent/WO2018199999A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Definitions

  • Embodiments of the present description generally relate to the field of microelectronic devices, and, more particularly, to using angled etching to fabricate microelectronic transistors.
  • Some microelectronic devices such as tunnel field-effect transistors (TFETS) and power amplifier transistors, have asymmetric sources and drains, i.e. positioned at differing distances from their respective transistor gates, as will be understood to those skilled in the art.
  • asymmetric sources and drain may be complex, as there is no self-aligned process for forming such asymmetric sources and drains with when utilizing conventional symmetric gate spacers.
  • FIGs. 1 -6 are side cross-sectional views of a process of using angled etches to form p- type doped regions and/or n-type doped regions for a microelectronic transistor, according to an embodiment of the present description.
  • FIG. 7 is a side cross-sectional view of a microelectronic transistor, according to other embodiment of the present description.
  • FIG. 8 illustrates a computing device in accordance with one implementation of the present description.
  • over, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers.
  • One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
  • microelectronic devices such as tunnel field-effect transistors (TFETS) and power amplifier transistors, require asymmetric sources and drains (i.e. positioned at differing distances from their respective transistor gates) for optimal performance, as will be understood to those skilled in the art.
  • Embodiments of the present description relate to microelectronic transistors having asymmetric sources and drains, which may be from by utilizing angled etching.
  • a transistor gate may be formed on a microelectronic substrate having a pair of symmetric gate spacers formed on opposing sidewalls of the transistor gate.
  • a first angled etch may be directed toward a first gate spacer to form a first recess and a second angled etch may be directed toward a second gate spacer to form a second recess, wherein the first recess is closer to or extends further under the transistor gate than the second recess.
  • a source may then be formed in the first recess and a drain may be formed in the second recess, such as through a regrowth process.
  • FIGs. 1-6 illustrate a method of using angled etches to form asymmetric source/drain configurations on opposing sides of a transistor gate. For the sake of conciseness and clarity, a single microelectronic transistor will be illustrated.
  • RF CMOS radio frequency complementary metal-oxide-semiconductor
  • breakdown voltage may be an issue, particularly between the gate and drain, as will be understood to those skilled in the art.
  • the following embodiments of asymmetric source/drain designs and their implementation can enable a lower overlap capacitance on the drain side and a matched external resistance on the source side, and, in RF CMOS applications, may increase breakdown voltage, while not sacrificing drain current saturation (Id sat).
  • a microelectronic substrate 110 may be provided or formed from any suitable material.
  • the microelectronic substrate 1 10 may be a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material.
  • the microelectronic substrate 1 10 may comprise a silicon- on-insulator substrate (SOI), wherein an upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy -nitride, disposed on the bulk substrate.
  • SOI silicon- on-insulator substrate
  • the microelectronic substrate 110 may be formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer.
  • the microelectronic substrate 110 may also be other types of substrates, such as germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon.
  • a transistor gate 120 may be formed on the
  • the transistor gate 120 may be a sacrificial gate (shown), which would be removed and replaced in subsequent processing with a gate electrode (not shown) with a gate dielectric (not shown) disposed between the gate electrode and the microelectronic substrate 1 10, as will be understood to those skilled in the art.
  • the transistor gate 120 could include the gate dielectric (not shown) and the gate electrode (not shown) at this point.
  • the functions and fabrication processes for the gate electrode and the gate dielectric are well known in the art and for the sake of conciseness and clarity will not be discussed herein.
  • the transistor gate 120 may include a first sidewall 122 and an opposing second sidewall 124.
  • a spacer material layer 130 may be conformally deposited over the transistor gate 120 and the microelectronic substrate 110.
  • the spacer material layer 130 may be made of any appropriate dielectric material, such as silicon nitride (e.g. S13N4), silicon oxynitride (e.g. SiON), silicon oxycarbonitride (e.g. SiOCN), or silicon carbonitride (e.g. SiCN).
  • the spacer material layer 130 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition ("ALD").
  • the spacer material layer 130 may be etched (shown with arrows 140), such as by a directional etch in a direction substantially parallel with the first sidewall 122 and the second sidewall 124 of the transistor gate 120 with an appropriate etchant, to formed a first gate spacer 132 abutting the first sidewall 122 of the transistor gate 120 and a second gate spacer 134 abutting the second sidewall 124 of the transistor gate 120, wherein a thickness Ti of the first gate spacer 132 is substantially equal to a thickness T2 of the second gate spacer 134.
  • the etch 140 may expose a first portion 112 of the microelectronic substrate 110 proximate the first gate spacer 132 and may expose a second portion 114 of the microelectronic substrate 110 proximate the second gate spacer 134.
  • a first angled etch may be directed toward the first gate spacer 132 of the transistor gate 120, such that a portion of the microelectronic substrate 110 at the exposed first portion 112 (see FIG. 3) may be removed to form a first recess 152.
  • the first angled etch 142 may result in the first recess 152 extending under the first gate spacer 132 and defining a first underlap Xudl, which is a distance between the first recess 152 and the transistor gate 120.
  • the first angled etch 142 proposed in the present description may be a deep etch for asymmetric undercut.
  • a distribution angle A of the etching stream (direction shown by the arrow of the first angled etch 142) may be between about 0 and 45 degrees from vertical V.
  • a second angled etch may be directed toward the second gate spacer 134 of the transistor gate 120, such that a portion of the microelectronic substrate 110 at the exposed second portion 114 (see FIG. 4) may be removed to form a second recess 154.
  • the second angled etch 144 may result in the second recess 154 extending under the second gate spacer 134 and defining a second underlap Xud2, which is a distance between the second recess 154 and the transistor gate 120.
  • the second angled etch 144 proposed in the present description may be a shallow etch of asymmetric undercut.
  • a distribution angle B of the etching stream (direction shown by the arrow of the second angled etch 144) may be between about 0 and 45 degrees from vertical V.
  • the first recess 152 may be closer to the transistor gate 120 than the second recess 154.
  • the first underlay Xudl is less than the second underlap Xud2.
  • the difference in the Xudl and Xud2 may be achieve with differing etching angles, differing etching chemistry, and differing processing time, as well as differing power levels, when plasma etching is used.
  • the distribution angle A of the first angled etch 142 is greater than the distribution angle B of the second angled etch 144
  • a first doped region 162 (such as a source region) may then be formed in the first recess 152 (see FIG. 5) of microelectronic substrate 110 and a second doped region 164 (such as a drain region) may be formed in the second recess 154 (see FIG. 5) of the microelectronic substrate 1 10.
  • the first doped region 162 and the second doped region 164 may be formed by any appropriate method, including but not limited to a regrowth process. The regrowth process is well known in the art and for the sake of conciseness and clarity will not be discussed herein.
  • the first doped region 162 and the second doped region 164 may both be formed with a p-type dopant, including, but not limited to, boron, aluminum, nitrogen, gallium, and indium, for the formation of the pMOS microelectronic transistor.
  • the first doped region 162 and the second doped region 164 may both be formed with an n-type dopant, including but limited to, phosphorous, arsenic, antimony, bismuth, and lithium, for the formation of an nMOS microelectronic transistor.
  • the first doped region 162 may be one of a p-type doped region or a n-type doped region, which is opposite to that of the second doped region 164, and the undoped portion of the microelectronic substrate 110 under the transistor gate 120 may form an intrinsic region 166 for the formation of the basic P-I-N (p-type/intrinsic/n-type) junction for a tunnel field effect transistor (TFET), e.g. a microelectronic transistor 170.
  • TFET tunnel field effect transistor
  • the first doped region 162 may be closer to (illustrated as first underlap Xudl) the transistor gate 120 than the second doped region 164 (illustrated as second underlap Xud2).
  • first underlap Xudl the transistor gate 120
  • second underlap Xud2 the second doped region 164
  • the asymmetry between the first doped region 162 and the second doped region 164 relative to the transistor gate 120 can enable a lower overlap capacitance (Cov) on the drain side (e.g. the second doped region 164) and a matched external resistance (Rext) on the source side (e.g. the first doped region 162).
  • a similar process to that shown and described with regard to FIGs. 1-6 may be used to result in either one of or both the first doped region 162 and the second doped region 164 extending under the transistor gate 120.
  • the first doped region 162 may extend further under the transistor gate 120 than the second doped region 164.
  • the asymmetry between the first doped region 162 and the second doped region 164 relative to the transistor gate 120 can enable a lower overlap capacitance (Cov) on the drain side (e.g. the second doped region 164) and a matched external resistance (Rext) on the source side (e.g. the first doped region 162).
  • FIG. 8 illustrates a computing device 200 in accordance with one implementation of the present description.
  • the computing device 200 houses a board 202.
  • the board may include a number of microelectronic components, including but not limited to a
  • processor 204 at least one communication chip 206 A, 206B, volatile memory 208, (e.g., DRAM), non-volatile memory 210 (e.g., ROM), flash memory 212, a graphics processor or CPU 214, a digital signal processor (not shown), a crypto processor (not shown), a chipset 216, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory 208 e.g., DRAM
  • non-volatile memory 210 e.g., ROM
  • flash memory 212 e.g.,
  • the communication chips 206A, 206B enable wireless communications for the transfer of data to and from the computing device 200.
  • the term "wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 206 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 200 may include a plurality of communication chips 206A, 206B.
  • a first communication chip 206A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 206B may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • microelectronic components within the computing device 200 may include microelectronic devices having at least one microelectronic transistor described above and/or having at least one microelectronic transistor fabricated in the manner described above.
  • the computing device 200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 200 may be any other electronic device that processes data.
  • Example 1 is a microelectronic transistor, comprising a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing side sidewall; a first gate spacer abutting the first sidewall of the transistor gate; a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; a first doped region proximate the transistor gate first sidewall; and a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
  • Example 2 the subject matter of Example 1 can optionally include the first doped region comprising a source and the second doped region comprising a drain.
  • Example 3 the subject matter of either Example 1 or 2 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
  • Example 4 the subject matter of either Example 1 or 2 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, the second doped region comprises one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
  • Example 5 the subject matter of either Example 1 or 2 can optionally include the first gate spacer and the second gate spacer comprising a dielectric material.
  • Example 6 is a method for forming a microelectronic transistor, comprising forming a transistor gate on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall; forming a first gate spacer abutting the transistor gate first sidewall; forming a second gate spacer abutting the transistor gate second sidewall, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; performing a first angled etch toward the first gate spacer to form a first recess in the microelectronic substrate; performing a second angled etch toward the second gate spacer to form a second recess in the microelectronic substrate, wherein the first recess is either closer to or further under the transistor gate than the second recess; forming a first doped region within the first recess; and forming a second doped region within the second recess.
  • Example 7 the subject matter of Example 6 can optionally include forming the first gate spacer and forming the second gate spacer comprising depositing a spacer material layer over the transistor gate and over the microelectronic substrate, and performing a directional etch toward the transistor gate.
  • Example 8 the subject matter of claim 7 can optionally include depositing the spacer material layer comprising depositing a dielectric material layer.
  • Example 9 the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming a source, and forming the second doped region comprising forming a drain.
  • Example 10 the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming one of a p-type doped region and an n- type doped region, and forming the second doped region comprising forming one of a p-type doped region and an n-type doped region.
  • Example 11 the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming one of a p-type doped region and an n- type doped region, forming the second doped region comprising forming one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising forming an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
  • Example 12 the subject matter of either Example 6 or 7 can optionally include performing the first angled etch directed toward the first gate spacer comprising performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
  • Example 13 the subject matter of either Example 6 or 7 can optionally include performing the second angled etch directed toward the second gate spacer comprising performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
  • Example 14 the subject matter of either Example 6 or 7 can optionally include performing the first angled etch directed toward the first gate spacer comprising performing the first angled etch directed toward the first gate spacer comprises performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, performing the second angled etch directed toward the second gate spacer comprising performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, and wherein the distribution angle of the first angled etch is greater than the distribution angle of the second angled etch.
  • Example 15 the subject matter of either Example 5 or 6 can optionally include forming the first doped region comprising a regrowth process.
  • Example 16 the subject matter of either Example 5 or 6 can optionally include forming the second doped region comprising a regrowth process.
  • Example 17 is an electronic system, comprising a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic transistor comprising a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall; a first gate spacer abutting the first sidewall of the transistor gate; a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; a first doped region proximate the transistor gate first sidewall; and a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
  • the microelectronic device includes at least one microelectronic transistor comprising a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall
  • Example 18 the subject matter of Example 17 can optionally include the first doped region comprising a source and the second doped region comprising a drain.
  • Example 19 the subject matter of either Example 17 or 18 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
  • Example 20 the subject matter of either Example 17 or 18 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, the second doped region comprises one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
  • Example 21 the subject matter of either Example 17 or 18 can optionally include the first gate spacer and the second gate spacer comprising a dielectric material.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A microelectronic transistor may be fabricated having asymmetric sources and drains by utilizing angled etching. In one embodiment, a transistor gate may be formed on a microelectronic substrate having a pair of symmetric gate spacers formed on opposing sidewalls of the transistor gate. A first angled etch may be directed toward a first gate spacer to form a first recess and a second angled etch may be directed toward a second gate spacer to form a second recess, wherein the first recess is closer to or extends further under the transistor gate than the second recess. A source may then be formed in the first recess and a drain may be formed in the second recess, such as through a regrowth process.

Description

MICROELECTRONIC TRANSISTOR SOURCE/DRAIN FORMATION
USING ANGLED ETCHING
TECHNICAL FIELD
Embodiments of the present description generally relate to the field of microelectronic devices, and, more particularly, to using angled etching to fabricate microelectronic transistors.
BACKGROUND
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the microelectronic industry for the fabrication of microelectronic devices. To achieve these goals, there is a drive to improve efficiency with improvements in their designs, materials used, and/or in their fabrication processes.
Some microelectronic devices, such as tunnel field-effect transistors (TFETS) and power amplifier transistors, have asymmetric sources and drains, i.e. positioned at differing distances from their respective transistor gates, as will be understood to those skilled in the art. However, forming such asymmetric sources and drain may be complex, as there is no self-aligned process for forming such asymmetric sources and drains with when utilizing conventional symmetric gate spacers.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which: FIGs. 1 -6 are side cross-sectional views of a process of using angled etches to form p- type doped regions and/or n-type doped regions for a microelectronic transistor, according to an embodiment of the present description.
FIG. 7 is a side cross-sectional view of a microelectronic transistor, according to other embodiment of the present description.
FIG. 8 illustrates a computing device in accordance with one implementation of the present description.
DESCRIPTION OF EMBODIMENTS
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description. The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "over" or "on" another layer or bonded "to" another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
Some microelectronic devices, such as tunnel field-effect transistors (TFETS) and power amplifier transistors, require asymmetric sources and drains (i.e. positioned at differing distances from their respective transistor gates) for optimal performance, as will be understood to those skilled in the art. Embodiments of the present description relate to microelectronic transistors having asymmetric sources and drains, which may be from by utilizing angled etching. In one embodiment, a transistor gate may be formed on a microelectronic substrate having a pair of symmetric gate spacers formed on opposing sidewalls of the transistor gate. A first angled etch may be directed toward a first gate spacer to form a first recess and a second angled etch may be directed toward a second gate spacer to form a second recess, wherein the first recess is closer to or extends further under the transistor gate than the second recess. A source may then be formed in the first recess and a drain may be formed in the second recess, such as through a regrowth process.
FIGs. 1-6 illustrate a method of using angled etches to form asymmetric source/drain configurations on opposing sides of a transistor gate. For the sake of conciseness and clarity, a single microelectronic transistor will be illustrated.
As will be understood to those skilled in the art, external resistance (Rext) control is critical to achieving higher drain current saturation (Id sat). However, the external resistance on the source side plays a more critical role in the drain current saturation because it lowers the effective voltage gate source (Vgs) and voltage drain source (Vds). The external resistance on the drain side has more of an impact on the linear drain current (Id lin) due to the lower effective voltage drain source. This allows for design flexibility to achieve a matched current saturation while lowering an overlap capacitance (Cov) on the drain side. It is noted that the overlap capacitance (Cov) will play a role in the circuit performance because the Miller effect will make the overlap capacitance larger than that estimated by calculation, which can degrade circuit performance. Furthermore, in radio frequency complementary metal-oxide-semiconductor (RF CMOS) applications, breakdown voltage may be an issue, particularly between the gate and drain, as will be understood to those skilled in the art. However, the following embodiments of asymmetric source/drain designs and their implementation can enable a lower overlap capacitance on the drain side and a matched external resistance on the source side, and, in RF CMOS applications, may increase breakdown voltage, while not sacrificing drain current saturation (Id sat).
As illustrated in FIG. 1 , a microelectronic substrate 110 may be provided or formed from any suitable material. In one embodiment, the microelectronic substrate 1 10 may be a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In other embodiments, the microelectronic substrate 1 10 may comprise a silicon- on-insulator substrate (SOI), wherein an upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy -nitride, disposed on the bulk substrate. Alternatively, the microelectronic substrate 110 may be formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer. The microelectronic substrate 110 may also be other types of substrates, such as germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon.
As further shown in FIG. 1, a transistor gate 120 may be formed on the
microelectronic substrate 1 10. The transistor gate 120 may be a sacrificial gate (shown), which would be removed and replaced in subsequent processing with a gate electrode (not shown) with a gate dielectric (not shown) disposed between the gate electrode and the microelectronic substrate 1 10, as will be understood to those skilled in the art. Thus, the transistor gate 120 could include the gate dielectric (not shown) and the gate electrode (not shown) at this point. The functions and fabrication processes for the gate electrode and the gate dielectric are well known in the art and for the sake of conciseness and clarity will not be discussed herein. The transistor gate 120 may include a first sidewall 122 and an opposing second sidewall 124.
As shown in FIG. 2, a spacer material layer 130 may be conformally deposited over the transistor gate 120 and the microelectronic substrate 110. The spacer material layer 130 may be made of any appropriate dielectric material, such as silicon nitride (e.g. S13N4), silicon oxynitride (e.g. SiON), silicon oxycarbonitride (e.g. SiOCN), or silicon carbonitride (e.g. SiCN). The spacer material layer 130 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition ("ALD").
As shown in FIG. 3, the spacer material layer 130 may be etched (shown with arrows 140), such as by a directional etch in a direction substantially parallel with the first sidewall 122 and the second sidewall 124 of the transistor gate 120 with an appropriate etchant, to formed a first gate spacer 132 abutting the first sidewall 122 of the transistor gate 120 and a second gate spacer 134 abutting the second sidewall 124 of the transistor gate 120, wherein a thickness Ti of the first gate spacer 132 is substantially equal to a thickness T2 of the second gate spacer 134. Furthermore, the etch 140 may expose a first portion 112 of the microelectronic substrate 110 proximate the first gate spacer 132 and may expose a second portion 114 of the microelectronic substrate 110 proximate the second gate spacer 134.
As shown in FIG. 4, a first angled etch (shown as arrow 142) may be directed toward the first gate spacer 132 of the transistor gate 120, such that a portion of the microelectronic substrate 110 at the exposed first portion 112 (see FIG. 3) may be removed to form a first recess 152. The first angled etch 142 may result in the first recess 152 extending under the first gate spacer 132 and defining a first underlap Xudl, which is a distance between the first recess 152 and the transistor gate 120. The first angled etch 142 proposed in the present description may be a deep etch for asymmetric undercut. In one embodiment, a distribution angle A of the etching stream (direction shown by the arrow of the first angled etch 142) may be between about 0 and 45 degrees from vertical V.
As shown in FIG. 5, a second angled etch (shown as arrow 144) may be directed toward the second gate spacer 134 of the transistor gate 120, such that a portion of the microelectronic substrate 110 at the exposed second portion 114 (see FIG. 4) may be removed to form a second recess 154. The second angled etch 144 may result in the second recess 154 extending under the second gate spacer 134 and defining a second underlap Xud2, which is a distance between the second recess 154 and the transistor gate 120. The second angled etch 144 proposed in the present description may be a shallow etch of asymmetric undercut. In one embodiment, a distribution angle B of the etching stream (direction shown by the arrow of the second angled etch 144) may be between about 0 and 45 degrees from vertical V. As further illustrated in FIG. 5, the first recess 152 may be closer to the transistor gate 120 than the second recess 154. In other words, the first underlay Xudl is less than the second underlap Xud2.
It is understood that the difference in the Xudl and Xud2 may be achieve with differing etching angles, differing etching chemistry, and differing processing time, as well as differing power levels, when plasma etching is used. In one embodiment, the distribution angle A of the first angled etch 142 is greater than the distribution angle B of the second angled etch 144
As shown in FIG. 6, a first doped region 162 (such as a source region) may then be formed in the first recess 152 (see FIG. 5) of microelectronic substrate 110 and a second doped region 164 (such as a drain region) may be formed in the second recess 154 (see FIG. 5) of the microelectronic substrate 1 10. The first doped region 162 and the second doped region 164 may be formed by any appropriate method, including but not limited to a regrowth process. The regrowth process is well known in the art and for the sake of conciseness and clarity will not be discussed herein. In one embodiment, the first doped region 162 and the second doped region 164 may both be formed with a p-type dopant, including, but not limited to, boron, aluminum, nitrogen, gallium, and indium, for the formation of the pMOS microelectronic transistor. In another embodiment, the first doped region 162 and the second doped region 164 may both be formed with an n-type dopant, including but limited to, phosphorous, arsenic, antimony, bismuth, and lithium, for the formation of an nMOS microelectronic transistor. In still another embodiment, with additional lithographic steps (as will be understood to those skilled in the art), the first doped region 162 may be one of a p-type doped region or a n-type doped region, which is opposite to that of the second doped region 164, and the undoped portion of the microelectronic substrate 110 under the transistor gate 120 may form an intrinsic region 166 for the formation of the basic P-I-N (p-type/intrinsic/n-type) junction for a tunnel field effect transistor (TFET), e.g. a microelectronic transistor 170.
As further illustrated in FIG. 6, due to the first angled etch 142 used to form the first recess 152 (see FIG. 4) and the second angled etch 144 used to form the second recess 154 (see FIG. 5), the first doped region 162 may be closer to (illustrated as first underlap Xudl) the transistor gate 120 than the second doped region 164 (illustrated as second underlap Xud2). Thus, as will be understood to those skilled in the art, the asymmetry between the first doped region 162 and the second doped region 164 relative to the transistor gate 120 can enable a lower overlap capacitance (Cov) on the drain side (e.g. the second doped region 164) and a matched external resistance (Rext) on the source side (e.g. the first doped region 162).
A similar process to that shown and described with regard to FIGs. 1-6 may be used to result in either one of or both the first doped region 162 and the second doped region 164 extending under the transistor gate 120. As illustrated in FIG. 7, the first doped region 162 may extend further under the transistor gate 120 than the second doped region 164. Again, the asymmetry between the first doped region 162 and the second doped region 164 relative to the transistor gate 120 can enable a lower overlap capacitance (Cov) on the drain side (e.g. the second doped region 164) and a matched external resistance (Rext) on the source side (e.g. the first doped region 162).
FIG. 8 illustrates a computing device 200 in accordance with one implementation of the present description. The computing device 200 houses a board 202. The board may include a number of microelectronic components, including but not limited to a
processor 204, at least one communication chip 206 A, 206B, volatile memory 208, (e.g., DRAM), non-volatile memory 210 (e.g., ROM), flash memory 212, a graphics processor or CPU 214, a digital signal processor (not shown), a crypto processor (not shown), a chipset 216, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the microelectronic components may be physically and electrically coupled to the board 202. In some implementations, at least one of the microelectronic components may be a part of the processor 204.
The communication chips 206A, 206B enable wireless communications for the transfer of data to and from the computing device 200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 206 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 200 may include a plurality of communication chips 206A, 206B. For instance, a first communication chip 206A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 206B may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the microelectronic components within the computing device 200 may include microelectronic devices having at least one microelectronic transistor described above and/or having at least one microelectronic transistor fabricated in the manner described above.
In various implementations, the computing device 200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 200 may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-8. The subject matter may be applied to other microelectronic device and assembly applications, as well as any other appropriate transistor applications, as will be understood to those skilled in the art.
The following examples pertain to further embodiments, wherein Example 1 is a microelectronic transistor, comprising a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing side sidewall; a first gate spacer abutting the first sidewall of the transistor gate; a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; a first doped region proximate the transistor gate first sidewall; and a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
In Example 2, the subject matter of Example 1 can optionally include the first doped region comprising a source and the second doped region comprising a drain.
In Example 3, the subject matter of either Example 1 or 2 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
In Example 4, the subject matter of either Example 1 or 2 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, the second doped region comprises one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
In Example 5, the subject matter of either Example 1 or 2 can optionally include the first gate spacer and the second gate spacer comprising a dielectric material.
The following examples pertain to further embodiments, wherein Example 6 is a method for forming a microelectronic transistor, comprising forming a transistor gate on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall; forming a first gate spacer abutting the transistor gate first sidewall; forming a second gate spacer abutting the transistor gate second sidewall, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; performing a first angled etch toward the first gate spacer to form a first recess in the microelectronic substrate; performing a second angled etch toward the second gate spacer to form a second recess in the microelectronic substrate, wherein the first recess is either closer to or further under the transistor gate than the second recess; forming a first doped region within the first recess; and forming a second doped region within the second recess.
In Example 7, the subject matter of Example 6 can optionally include forming the first gate spacer and forming the second gate spacer comprising depositing a spacer material layer over the transistor gate and over the microelectronic substrate, and performing a directional etch toward the transistor gate.
In Example 8, the subject matter of claim 7 can optionally include depositing the spacer material layer comprising depositing a dielectric material layer.
In Example 9, the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming a source, and forming the second doped region comprising forming a drain.
In Example 10, the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming one of a p-type doped region and an n- type doped region, and forming the second doped region comprising forming one of a p-type doped region and an n-type doped region.
In Example 11, the subject matter of either Example 6 or 7 can optionally include forming the first doped region comprising forming one of a p-type doped region and an n- type doped region, forming the second doped region comprising forming one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising forming an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
In Example 12, the subject matter of either Example 6 or 7 can optionally include performing the first angled etch directed toward the first gate spacer comprising performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
In Example 13, the subject matter of either Example 6 or 7 can optionally include performing the second angled etch directed toward the second gate spacer comprising performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
In Example 14, the subject matter of either Example 6 or 7 can optionally include performing the first angled etch directed toward the first gate spacer comprising performing the first angled etch directed toward the first gate spacer comprises performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, performing the second angled etch directed toward the second gate spacer comprising performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, and wherein the distribution angle of the first angled etch is greater than the distribution angle of the second angled etch.
In Example 15, the subject matter of either Example 5 or 6 can optionally include forming the first doped region comprising a regrowth process.
In Example 16, the subject matter of either Example 5 or 6 can optionally include forming the second doped region comprising a regrowth process.
The following examples pertain to further embodiments, wherein Example 17 is an electronic system, comprising a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic transistor comprising a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall; a first gate spacer abutting the first sidewall of the transistor gate; a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer; a first doped region proximate the transistor gate first sidewall; and a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
In Example 18, the subject matter of Example 17 can optionally include the first doped region comprising a source and the second doped region comprising a drain.
In Example 19, the subject matter of either Example 17 or 18 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
In Example 20, the subject matter of either Example 17 or 18 can optionally include the first doped region comprising one of a p-type doped region and an n-type doped region, the second doped region comprises one of a p-type doped region and an n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region. In Example 21, the subject matter of either Example 17 or 18 can optionally include the first gate spacer and the second gate spacer comprising a dielectric material.
Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims

CLAIMS What is claimed is:
1. A microelectronic transistor, comprising:
a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall;
a first gate spacer abutting the first sidewall of the transistor gate;
a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer;
a first doped region proximate the transistor gate first sidewall; and
a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
2. The microelectronic transistor of claim 1 , wherein the first doped region comprises a source and the second doped region comprises a drain.
3. The microelectronic transistor of either claim 1 or 2, wherein the first doped region comprises one of a p-type doped region and an n-type doped region; and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
4. The microelectronic transistor of either claim 1 or 2, wherein the first doped region comprises one of a p-type doped region or a n-type doped region, wherein the second doped region comprises one of a p-type doped region or a n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the
microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
5. The microelectronic transistor of either claim 1 or 2, wherein the first gate spacer and the second gate spacer comprise a dielectric material.
6. A method for forming a microelectronic transistor, comprising:
forming a transistor gate on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall;
forming a first gate spacer abutting the transistor gate first sidewall;
forming a second gate spacer abutting the transistor gate second sidewall, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer;
performing a first angled etch toward the first gate spacer to form a first recess in the microelectronic substrate;
performing a second angled etch toward the second gate spacer to form a second recess in the microelectronic substrate, wherein the first recess is either closer to or further under the transistor gate than the second recess;
forming a first doped region within the first recess; and
forming a second doped region within the second recess.
7. The method of claim 6, wherein forming the first gate spacer and forming the second gate spacer, comprises:
depositing a spacer material layer over the transistor gate and over the microelectronic substrate; and
performing a directional etch directed toward the transistor gate first sidewall.
8. The method of claim 7, wherein depositing the spacer material layer comprises depositing a dielectric material layer.
9. The method of either claim 6 or 7, wherein forming the first doped region comprises forming a source and wherein forming the second doped region comprises forming a drain.
10. The method of either claim 6 or 7, wherein forming the first doped region comprises forming one of a p-type doped region and an n-type doped region, and wherein forming the second doped region comprises forming one of a p-type doped region and an n-type doped region.
1 1. The method of either claim 6 or 7, wherein forming the first doped region comprises forming one of a p-type doped region or a n-type doped region, wherein forming the second doped region comprises forming one of a p-type doped region or a n-type doped region, which is opposite to that of the first doped region, and further comprising forming an undoped portion of the microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region.
12. The method of either claim 6 or 7, wherein performing the first angled etch directed toward the first gate spacer comprises performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
13. The method of either claim 6 or 7, wherein performing the second angled etch directed toward the second gate spacer comprises performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical.
14. The method of either claim 6 or 7, wherein performing the first angled etch directed toward the first gate spacer comprises performing the first angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, wherein performing the second angled etch directed toward the second gate spacer comprises performing the second angled etch directed at a distribution angle of between about 0 and 45 degrees from vertical, and wherein the distribution angle of the first angled etch is greater than the distribution angle of the second angled etch.
15. The method of either claim 6 or 7, wherein forming the first doped region comprises a regrowth process.
16. The method of either claim 6 or 7, wherein forming the second doped region comprises a regrowth process.
17. An electronic system, comprising:
a board; and
a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic transistor comprising:
a transistor gate disposed on a microelectronic substrate, wherein the transistor gate includes a first sidewall and an opposing second sidewall;
a first gate spacer abutting the first sidewall of the transistor gate; a second gate spacer abutting the second sidewall of the transistor gate, wherein the first gate spacer has a thickness that is substantially equal to a thickness of the second gate spacer;
a first doped region proximate the transistor gate first sidewall; and a second doped region proximate the transistor gate second sidewall, wherein the first doped region is either closer to or further under the transistor gate than the second doped region.
18. The electronic system of claim 17, wherein the first doped region comprises a source and the second doped region comprises a drain.
19. The electronic system of either claim 17 or 18, wherein the first doped region comprises one of a p-type doped region and an n-type doped region; and wherein the second doped region comprises one of a p-type doped region and an n-type doped region.
20. The electronic system of either claim 17 or 18, wherein the first doped region comprises one of a p-type doped region or a n-type doped region, wherein the second doped region comprises one of a p-type doped region or a n-type doped region, which is opposite to that of the first doped region, and further comprising an undoped portion of the
microelectronic substrate under the transistor gate forming an intrinsic region between the first doped region and the second doped region. The electronic system of either claim 17 or 18, wherein the first gate spacer and the gate spacer comprise a dielectric material.
PCT/US2017/030222 2017-04-28 2017-04-28 Microelectronic transistor source/drain formation using angled etching WO2018199999A1 (en)

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