TW200633005A - Method for manufacturing semiconductor device with recess channels and asymmetrical junctions - Google Patents
Method for manufacturing semiconductor device with recess channels and asymmetrical junctionsInfo
- Publication number
- TW200633005A TW200633005A TW094114906A TW94114906A TW200633005A TW 200633005 A TW200633005 A TW 200633005A TW 094114906 A TW094114906 A TW 094114906A TW 94114906 A TW94114906 A TW 94114906A TW 200633005 A TW200633005 A TW 200633005A
- Authority
- TW
- Taiwan
- Prior art keywords
- bit line
- semiconductor substrate
- junction
- forming
- junctions
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 7
- 238000000034 method Methods 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 5
- 238000003860 storage Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050020926A KR100712989B1 (ko) | 2005-03-14 | 2005-03-14 | 리세스 채널 및 비대칭접합 구조를 갖는 반도체 소자의제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200633005A true TW200633005A (en) | 2006-09-16 |
TWI279845B TWI279845B (en) | 2007-04-21 |
Family
ID=36971557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094114906A TWI279845B (en) | 2005-03-14 | 2005-05-09 | Method for manufacturing semiconductor device with recess channels and asymmetrical junctions |
Country Status (5)
Country | Link |
---|---|
US (1) | US7381612B2 (zh) |
JP (1) | JP4993248B2 (zh) |
KR (1) | KR100712989B1 (zh) |
CN (1) | CN100463146C (zh) |
TW (1) | TWI279845B (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100675889B1 (ko) * | 2005-04-26 | 2007-02-02 | 주식회사 하이닉스반도체 | 리세스 채널을 가지는 반도체 소자 및 그 제조방법 |
JP4773169B2 (ja) * | 2005-09-14 | 2011-09-14 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
KR100843712B1 (ko) * | 2007-02-26 | 2008-07-04 | 삼성전자주식회사 | 활성 영역 내 채널 불순물 확산 영역과 자기 정렬하는데적합한 게이트 패턴을 가지는 트랜지스터들 및 그의형성방법들 |
JP5608313B2 (ja) * | 2007-03-16 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法 |
TWI349340B (en) * | 2007-09-03 | 2011-09-21 | Nanya Technology Corp | Method for manufacturing non-volatile memory |
KR100920045B1 (ko) * | 2007-12-20 | 2009-10-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
JP2010141107A (ja) * | 2008-12-11 | 2010-06-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN101924075B (zh) * | 2009-06-09 | 2012-06-27 | 中芯国际集成电路制造(上海)有限公司 | 快闪存储器制造方法 |
KR101096226B1 (ko) * | 2010-10-28 | 2011-12-22 | 주식회사 하이닉스반도체 | 매립게이트를 구비한 반도체장치 제조 방법 |
JP2012204689A (ja) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | 半導体装置及びその製造方法 |
CN104637822B (zh) * | 2015-01-23 | 2018-05-11 | 无锡同方微电子有限公司 | 一种双沟槽场效应管及其制备方法 |
CN110246841B (zh) | 2018-03-08 | 2021-03-23 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN108735608B (zh) * | 2018-05-30 | 2023-10-24 | 长鑫存储技术有限公司 | 半导体器件及其制作方法 |
CN115259679B (zh) * | 2022-07-26 | 2024-02-27 | Oppo广东移动通信有限公司 | 基板的蚀刻方法、壳体组件和电子设备 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2507502B2 (ja) * | 1987-12-28 | 1996-06-12 | 三菱電機株式会社 | 半導体装置 |
KR960003864B1 (ko) * | 1992-01-06 | 1996-03-23 | 삼성전자주식회사 | 반도체 메모리장치 및 그 제조방법 |
US5640034A (en) * | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
JPH0897419A (ja) * | 1994-09-29 | 1996-04-12 | Toshiba Corp | Mos型トランジスタ及びその製造方法 |
KR0161398B1 (ko) * | 1995-03-13 | 1998-12-01 | 김광호 | 고내압 트랜지스터 및 그 제조방법 |
JPH08264562A (ja) * | 1995-03-24 | 1996-10-11 | Mitsubishi Electric Corp | 半導体装置,及びその製造方法 |
US5990509A (en) * | 1997-01-22 | 1999-11-23 | International Business Machines Corporation | 2F-square memory cell for gigabit memory applications |
US6246083B1 (en) * | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
JPH11354541A (ja) * | 1998-06-11 | 1999-12-24 | Fujitsu Quantum Devices Kk | 半導体装置およびその製造方法 |
JP2002539637A (ja) * | 1999-03-17 | 2002-11-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | フローティングゲート電界効果型トランジスタの製造方法 |
DE60001601T2 (de) * | 1999-06-18 | 2003-12-18 | Lucent Technologies Inc | Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren |
US6501131B1 (en) * | 1999-07-22 | 2002-12-31 | International Business Machines Corporation | Transistors having independently adjustable parameters |
US6285060B1 (en) | 1999-12-30 | 2001-09-04 | Siliconix Incorporated | Barrier accumulation-mode MOSFET |
US6621107B2 (en) * | 2001-08-23 | 2003-09-16 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
JP4005805B2 (ja) * | 2001-12-17 | 2007-11-14 | 株式会社東芝 | 半導体装置 |
US20030134479A1 (en) * | 2002-01-16 | 2003-07-17 | Salling Craig T. | Eliminating substrate noise by an electrically isolated high-voltage I/O transistor |
DE10204871A1 (de) * | 2002-02-06 | 2003-08-21 | Infineon Technologies Ag | Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren |
US6878646B1 (en) * | 2002-10-16 | 2005-04-12 | Taiwan Semiconductor Manufacturing Company | Method to control critical dimension of a hard masked pattern |
US7081391B2 (en) * | 2002-11-26 | 2006-07-25 | Samsung Electronics Co., Ltd. | Integrated circuit devices having buried insulation layers and methods of forming the same |
KR100539276B1 (ko) * | 2003-04-02 | 2005-12-27 | 삼성전자주식회사 | 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법 |
KR100568854B1 (ko) * | 2003-06-17 | 2006-04-10 | 삼성전자주식회사 | 반도체 메모리에서의 리세스 채널을 갖는 트랜지스터 형성방법 |
KR100471001B1 (ko) * | 2003-07-02 | 2005-03-14 | 삼성전자주식회사 | 리세스형 트랜지스터 및 그의 제조방법 |
KR100593443B1 (ko) * | 2004-02-11 | 2006-06-28 | 삼성전자주식회사 | 트랜지스터들 및 그 제조방법들 |
KR100549580B1 (ko) * | 2004-06-24 | 2006-02-08 | 주식회사 하이닉스반도체 | 리세스 채널 구조를 갖는 반도체 소자의 제조 방법 |
KR20060075079A (ko) * | 2004-12-28 | 2006-07-04 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
JP4984398B2 (ja) * | 2005-02-04 | 2012-07-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
-
2005
- 2005-03-14 KR KR1020050020926A patent/KR100712989B1/ko not_active IP Right Cessation
- 2005-05-09 TW TW094114906A patent/TWI279845B/zh not_active IP Right Cessation
- 2005-06-20 CN CNB2005100783816A patent/CN100463146C/zh not_active Expired - Fee Related
- 2005-06-24 US US11/166,482 patent/US7381612B2/en not_active Expired - Fee Related
- 2005-07-04 JP JP2005194721A patent/JP4993248B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100712989B1 (ko) | 2007-05-02 |
KR20060099605A (ko) | 2006-09-20 |
JP2006261627A (ja) | 2006-09-28 |
CN1835209A (zh) | 2006-09-20 |
US7381612B2 (en) | 2008-06-03 |
JP4993248B2 (ja) | 2012-08-08 |
TWI279845B (en) | 2007-04-21 |
CN100463146C (zh) | 2009-02-18 |
US20060205162A1 (en) | 2006-09-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |