TW200300282A - Semiconductor package and method of production thereof - Google Patents

Semiconductor package and method of production thereof Download PDF

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Publication number
TW200300282A
TW200300282A TW091132188A TW91132188A TW200300282A TW 200300282 A TW200300282 A TW 200300282A TW 091132188 A TW091132188 A TW 091132188A TW 91132188 A TW91132188 A TW 91132188A TW 200300282 A TW200300282 A TW 200300282A
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capacitor
dielectric constant
mounting hole
conductor
board
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TW091132188A
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Takahiro Iijima
Akio Rokugawa
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Shinko Electric Ind Co
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Description

200300282 坎、發明說明 (發明說明應敘明 發明所屬之技術領域 先前技術、内容、實施方式及圖式簡單說明） 【發明所屬^技術領域】 發明領域 本發明係有關半導體封裝體及其製造方法，尤係關於 5 一種高頻率特性優異的半導體封裝體及其製造方法。 L 前 發明背景 在處理U處理器等之高頻率信號的半導體封裝體中， 其信號傳輸路徑的頻率特性會是一個問題。因此，於實務 上曰見藉匹配特性阻抗或盡可能地縮短信號線，而來在輪 入及輸出端子處防止信號的反射者。例如，有關匹配特性 阻抗的方法，曾有將信號傳輸路徑製成共平面狀而實際形 成一共軸線的方法；或在電路板中形成一凹槽，並將—共 軸鏡線插設於該凹槽内來製成一共轴結構（曰本未審查專 15利公告（k〇kai)“_167258號）等之方法。而，有關縮短該信 號線的方法，實務上曾見將一晶片電容器及其它的電路構 件設成盡可能地靠近該半導體晶片之連接端子的作法。 概觀本發明所要解決的問題係，若該半導體封裝體所 處理的信號頻率變成1GHz高，則電源供應的波動將會對 頻率特性有所影響，故實務上曾將—大尺寸的電容器連接 於該電源供應線，而來在傳輪信號時抑止其電源供應電壓 的任何減降。假使該相關技術之半導體元件係由一設在電 路板上的半導體晶片所構成，則—電容器會被設在該電路 上，其乃將-晶片電容器設在該電路板之相反於設有該半 200300282 玖、發明說明 導體晶片的表面上，或將一晶片電容器設在該半導體晶片 的附近。此係為能將該晶片電容器設成盡可能地靠近該半 導體晶片的連接端子，而來儘量減少其傳輸路徑的電感。 但是，半導體元件的操作頻率逐漸變高。若其需要在 5操作時滿足將該電感值減至不大於數PH的條件，則將會發 生問題，即使以上述之方法將該晶片電容器設在安裝該半 導體晶片的相反表面上盡可能靠近該半導體晶片之處，但 在與電極連接部份處的電感最後亦會高到超過該所需值； 此乃視該板的厚度，或該晶片電容器的尺寸而定，故該半 10導體元件將不能獲得所需的性能。 C 明内】 發明概要 15 本發明之一目的係為提供一種高頻率特性優異的半導 體封裝體’其能容易安褒—大尺寸的電容器，而可抑止電 源供應電壓的起伏波動’並能減少連接該電容器與連接: 子之線路部份的電容者；以及該半導體封裝體的製造方法。而 為達到上述目的’依據本發明之第一態樣，乃在提供 -種半導體元件其裝有一電容器可抑止電源供應電壓的波 動升降，而該電容器係由以下結構所形成··在—沿厚度方 向來貫穿-板的裝設孔中，有一在末端會連接於 晶片之連接端子的導線，及-以預定厚度來包覆該導線之 高介電常數材料’和—設在該高介電常數材料的外緣盘号 裝設孔内壁之間的導體層等，將會以該導線作為中心來形 成一共轴結構。 20 200300282 ίο 15 20 玖、發明說明 較好是’至少有-設在該板上的信號線係由以下結構 所形成：在一沿厚度方向來貫穿該板的裝設孔中，一在蕊 心的信號線’-低介電常數材料，及_導體層等，將會形 成匹配其阻抗的共軸纜線部。 依據本發明的第二態樣，乃在提供一種設有一電容器 而可抑止電源供應電壓波動之半導體封敦體的方法，乃包 含下列步驟：形成-裳設孔沿厚度方向來貫穿一板，及將 一電容器纜線壓裝於該裝設孔内，該電容㈣線包含一導 線位於蕊心，一高介電常數材料會以預定厚度同軸地包覆 。亥導線& |體勒套包覆在該高介電常數材料的外周緣 上，而將該電容器裝設於該板中。 依據本發明的第三態樣，係在提供一種設有一電容器 而可抑止電源供應電壓波動之半導體封装體的製造方法， 乃包含：形成一裝設孔沿厚度方向來貫穿一板，在該裝設 孔的内壁製成-導體層，並在該設有導電層的裝設孔内麼 裝-電容器i線’其具有一導線位於蕊心，及一高介電常 數材料以-預定厚度同軸地包覆該導線，而將該電容器裝 設於該板中。 圖式簡單說明 本毛明之足些及其它的目的和特徵，將可由以下較佳 實施例的說明並參照所附圖式而得更清楚暸解；其中： 第1圖為本發明之一半導體封裝體裝設一半導體晶片 的狀態之截面圖； 弟2A至2DU為本發明之—半導體封裝體的製程步驟
8 玖、發明說明 之截面圖；及 第3A與3B圖為用來製造半導體封裝 的立體圖。 〜為#見線 C實施方式】 較佳實施例之詳細說明 本發明的較佳實施騎參照所_式_細說明 第1圖為本發明一每 只苑例之半導體封裝體的構造截面 圖。該圖中係示屮—生诣_ ^ ^ +冷肢封裝體20上裝有一半導俨曰 1 〇的狀態。本實施例之半導 、曰曰 10 <牛¥ to封裝體的特徵係，_ 半導體封裝體2 0之板2 2的帝、 勺兒谷态3 0，將會與該半導體晶 1〇之連接端子咖的列設位置吻合地來裝設。 a曰曰 15 該電容器30係包含一導線32, 一高介電常數材祕 以預定厚度來包覆該導線32,及一導體勒套36形成—導二 層來包覆該高介電常數材料34的外周緣。該導線32與該導 體勒’套36係同心地列設。該電容器30即由該導線32,高介 電常數材料34’及該導體鞘套36等所形成，而具有—丘軸 結構。該高介電常數材料34係能供在該導線32和導體勒套 36之間來獲得—所需的靜電電容。該導線32及導體勒套36 即形如該電容器30的電極。於高介電常數材料Μ係由鈦化 鏍、鈦化鋇’或其它的高介電常數材料所製成，或由一種 其中混有-高介電常數材料來作為填充料的有機材料所製 成’俾可獲得所需的靜電電容。 在本實施例的半導體封裝體中，該電容器3 〇係用來抑 制電源供應電壓的起伏波動’因此該導㈣會連接於電源 20 200300282 玫、發明說明 10 15 20 供應線’而該包覆著高介電常數材料34外周面的導體勒套 36會連接於-接地線來形成接地電位。故而，該電容器％ 會被设在該電路的電源供應線與接地線之間。 如第1圖所示，該電容器30係套裝於一沿厚度方向貫 穿該板22的裝設孔中來形成一共輛結構。該導線32會直接 連接於半導體晶的連接料⑽。料線被設成 垂直地穿過該電容器30。其係同時為該電容器％之一構件 及供連接料接端子1Ga和電源供應的線路。因此，該連 接端子H)a與該電容器會被以最短的距離來連接，而沒有 任何線路的迁迴。連接該電容器3〇和連接端子心的線路 長度會變成最短，且線路部份的電感會變成最小。故，當 其在處理數GHz的高頻率信號時，將能有效地抑止特性的 另化。在一晋通半導體封裝體的結構中，電感會有200至 3〇〇 pH，但依據該結構，乃可將電感減少到⑺至咒 於第1圖中，標號40係為一可供阻抗匹配的共軸纜線 部，而被設在一信號線的連接部處。標號41為一作為該信 號 '、泉的.線，42為一低介電常數材料，而43為一導體鞘套 其冒包覆该低介電常數材料42的外周面。該導體鞘套43 係連接於-接地線，而會成為接地電位。該共軸欖部部糾 的4寸被係纟製成一共轴結構，而可在形成該信號線之特性 阻抗的。亥$線41之輸入/輸出端子處來匹配阻抗。該低介 電常數材料42係為一可供匹配50〇之特性阻抗的介電材料 。製成該電容器30的介電材料具有3〇至4〇的單位介電常數 ，而该低介電常數材料42係為一種約為3之低單位介電常
10 200300282 玖、發明說明 數的材料。 t圖例的半導體封裝體中，標號45係為—類似於導線 41紅唬線，但其並未形成一共軸結構，因該信號線45在 本實施例的半導體封裝體中係僅供—低頻信號的輪人/輸出。 該接地線46係經由一設在該板22 標號46為一接地線 别述導體勒套3 6和4 3，以使 。標號50係設在該板22底面 内層之互接圖案47來電連接於 該一鞘套36和43形成接地電位 的外。P連接ife子。㈣外部連制子㈣將焊球連結於設 在5亥板22表面上的平墊52而來製成者。 10 第2A至2DD乃示出上述半導體封裝體之各製程步驟。 第2A圖不出一板22設有形成信號線45和接地線衫的導 體線路，以及一互接圖案47。 該板22可被製成一多層板 而包含-由樹脂製成的核心板，其兩面會透過絕緣層來疊 設各互接層等。 15 第⑶圖乃示出裝設孔⑼與62沿著厚度方向貫穿該板22 來被形成的狀態。該等裝設孔6〇，62係在用來製成上述電 容器30和高頻信號使用的共軸纜線部4〇之位置處鑽孔而被 形成。該等裝設孔60與62係被製成使其内徑尺寸匹配於所 要I a又在该板22中之該電容器3〇和共軸纜線部4〇的外徑尺 20 寸。 第2C圖乃示出该電容器3〇和共軸纜線部4〇被裝設於該 板22之孔60與62中的狀態。為將該電容器3〇安裝於該裝設 孔60中，一事先製成圓筒狀的電容器纜線會被插入該裝設 孔60内。 200300282 玖、發明說明 第3A圖為一電容器纜線30a的立體圖。該電容器纜線 30a係由一前述之導線32，一高介電常數材料34，及一形 成長共軸纜線形狀的導體鞘套36等所組成。該電容器30可 藉將該電容器纜線30a切成預定長度，而壓裝於該板22的 5 裝設孔60中來被固設。
藉將該電容器30插入於該裝設孔60中，該導體鞘套36 將會觸接曝現於該裝設孔60内周壁上的互接圖案47，因此 該互接圖案47與導體鞘套36即會電連接。 請暸解將該電容器30裝入裝設孔60内的方法，除了使 10 用第3 A圖所示的電容器纜線30a的方法之外，使用第3B圖 所示之電容器纜線30b的方法亦為可行。在第3B圖中所示 的電容器纜線30b並沒有第30A圖中所示之電容器纜線30a 的導體鞘套36。
當使用第3B圖所示之電容器纜線30b來將該電容器30 15 裝設於該板22中時，首先一裝設孔60會被設於該板22中， 嗣該孔60的内壁會被電鍍而來形成一導體層，然後第3B圖 所示的電容器纜線30b會被壓裝於該裝設孔60内。在此情 況下，該導體層會變成接地電位，且設在該孔60内壁上的 導體層會具有如第3A圖所示之電容器纜線30a之導體鞘套 20 36的功能，而可供形成該電容器30。 該供作為板22之信號線的共軸纜線部40之安裝方法， 係類似於將該電容器30裝設於該板22中的方法。即，可將 第2C圖所示之共軸纜線部40，藉將一如第3A或3B圖所示 之電容器纜線30a或30b的相同方式所製成之一共軸纜線壓 12 ^00300282 ίο 15 20 玖、發明說明 裝於被^在板22中的裝設孔62内而來完成。該共軸繞線係 可在該低介電常數材料42的外表面上設有—導體勒套，或 亦可不設具該導體鞍套。當在該低介電常數材料42的外表 面上未設有該導體勒套時，其亦得以如同前述方式藉電鑛 该裝設孔62的内壁而來製成一導體層。 第2D圖係示出當將該電容器％及共歸線㈣設於該 板22中之後’在該板22的表面上形成—互接圖案的狀態。 該互接圖案係可藉以電鑛等之方法，在該㈣的頂面和底 面上形成一導體層，然後姓刻該導體層來形成一預定圖宰 而被製成。標號52係可供與外部連接端子連結的平塾’而 標號54為用來連結該半導體晶片1G之爆點的接墊。 以此方式，將可製成—半導體封裝體’其呈有一電容 ㈣係沿厚度方向貫穿該板22而來裝設。該實施例之半導 體封裝體’如上所述’乃具有形成電源供應線的導線32來 作為該電容㈣的-部份，並具有該導線以接連結於該 連接端子⑽，故可形成最短的電源供應線長度，而能抑 止其電源供應電壓的波動，並減少其電感，來形成一且有 絕佳高頻特性的封裝體。且，對傳輸該頻信號的信號線而 ::亦能藉匹配其特性阻抗而來改善該高頻特性。故將可 獲得一高頻特性優異的半導體封裝體。 综結本發明之功效，依據本發明的半導體封裝體及其 製造方法’乃可容易地將—電容器裝設於—板中，而來抑 止該電源供應電壓的波動’並能將連接該電路板與連接端 子的線路長度減至最小，而來降低電感。因此，其將能形
13 200300282 玖、發明說明 成一種具有絕佳高頻特性的半導體封裝體。 雖本發明已參照選供說明的特定實施例來詳加描述， 惟專業人士應可暸解各種修正仍可被製成，而不超出本發 明的基本概念和範圍。 5 【圖式簡單說明】 第1圖為本發明之一半導體封裝體裝設一半導體晶片 的狀態之截面圖；
第2A至2D圖為本發明之一半導體封裝體的製造步驟 之截面圖；及 10 第3A與3B圖為用來製造半導體封裝體之電容器纜線 的立體圖。 【圖式之主要元件代表符號表】 10…半導體晶片 10a···連接端子 20···半導體封裝體 22…板 30···電容器 30a，3b···電容器纜線 3 2…導線 34···高介電常數材料 3 6…導體鞘套 40···共軸纜線部 41…導線 42…低介電常數材料 43…導體鞘套 4 5…信號線 4 6…接地線 47…互接圖案 50···外部連接端子 52…平墊 54···接墊 60,62…裝設孔
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Claims (1)

  1. 200300282 10 15 20 拾、申請專利範圍 1. -種半導體元件，裝有一電容器可抑止電源供應電麈 的波動，其中該電容器係如下來構成：在一沿厚度方 向貫穿一板的裝設孔中，有一導線可在一端連接於一 半導體晶片的連接端子，一高介電常數材料會以一預 定厚度來包覆該導線，及一導體層被設於該高介電常 數材料的外周緣與該裝設孔的内壁之間，而以該導線 為其中心來形成一共軸結構。 2·如申請專利範圍第w之半導體元件，其中至少有—設 在該板中的信號線係如下來構成：在-沿厚度方向貫 穿該板的裝設孔中，有一在蕊心的信號線，一低介電 I數材料’及—導體層等會形成—匹配阻抗的共軸^ 3 ’種叙有一電容器可抑止電源供應電壓波動之半導叫 封裝體的製造方法，包含： h 沿厚度方向貫穿一板來形成一裝設孔；及 將一電容器纜線壓裝於該裝設孔内，而該電容哭 i線含有-在蕊心的導線，—高介電常數#㈣二 預定厚度共軸地包覆該導線，及一導體鞠套會包覆， 兩介電常數材料的外周表" 中。 而將4电谷裔固裝於該奴 種裝有一電容器可抑止 電源供應電壓波動之半導 封裝體的製造方法，包含： 沿厚度方向貫穿一板來形成一褒設孔; 在該裝設孔的内壁製成—導體層；及 趲 15 4. 200300282 拾、申請專利範圍 將一電容器纜線壓裝於該設有導體層的裝設孔内 ，而該電容器纟覽線包含一在蕊心的導線，及一高介電 常數材料會以預定厚度共軸地包覆該導線，而將該電 容器固設於該板中。 16
TW091132188A 2001-11-07 2002-10-30 Semiconductor package and method of production thereof TW200300282A (en)

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