US20030085471A1 - Semiconductor package and method of production thereof - Google Patents

Semiconductor package and method of production thereof Download PDF

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Publication number
US20030085471A1
US20030085471A1 US10281791 US28179102A US2003085471A1 US 20030085471 A1 US20030085471 A1 US 20030085471A1 US 10281791 US10281791 US 10281791 US 28179102 A US28179102 A US 28179102A US 2003085471 A1 US2003085471 A1 US 2003085471A1
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Prior art keywords
capacitor
board
attachment hole
conductor
dielectric constant
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US10281791
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Takahiro Iijima
Akio Rokugawa
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, and noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, and noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/642Capacitive arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • H01L2223/6622Coaxial feed-throughs in active or passive substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809Coaxial layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections or via connections
    • H05K3/4046Through-connections or via connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Abstract

A semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and a connection terminal, that is, a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire at its center, and a method of production of the same.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a semiconductor package and a method of production of the same, more particularly relates to a semiconductor package superior in high frequency characteristics and a method of production of the same. [0002]
  • 2. Description of the Related Art [0003]
  • In semiconductor packages handling high frequency signals of microprocessors etc., the frequency characteristics in the signal transmission path become a problem. Therefore, the practice has been to prevent reflection of signals at the input and output terminals by matching the characteristic impedance or shortening the signal line as much as possible. For example, as methods of matching the characteristic impedance, there are the method of making the signal transmission path coplanar in shape to virtually form a coaxial line, the method of providing a recess in the circuit board and inserting a coaxial cable in the recess to obtain a coaxial structure (Japanese Unexamined Patent Publication (Kokai) No. 5-167258), etc. Further, as the method of shortening the signal line, the practice has been to arrange a chip capacitor and other circuit parts as close as possible to the connection terminals of the semiconductor chip. [0004]
  • Summarizing the problem to be solved by the invention, if however the frequency of the signal handled by the semiconductor package becomes a high one of 1 GHz, fluctuations in the power supply will have an effect on the frequency characteristics, so the practice has been to connect a large-sized capacitor to the power supply line so as to suppress any drop in power supply voltage when a signal is transmitted. In the case of a semiconductor device of the related art comprised of a semiconductor chip mounted on a circuit board, a capacitor has been mounted at the circuit by arranging a chip capacitor at the surface of the circuit board opposite to the surface mounting the semiconductor chip or arranging a chip capacitor in the vicinity of the semiconductor chip. This is so as to arrange the chip capacitor as close as possible to the connection terminal of the semiconductor chip and thereby reduce the inductance of the transmission path as much as possible. [0005]
  • The operating frequencies of semiconductor devices are becoming higher, however. If it becomes necessary to satisfy the condition of reducing the inductance value at the time of operation to not more than several pH, the problem arises that even with the method of arranging the chip capacitor at a position as close to the semiconductor chip as possible at the surface opposite to the position where the semiconductor chip is mounted, the inductance at the part connected with the electrode may end up exceeding the desired value depending on the thickness of the board or the size of the chip capacitor and the required performance of the semiconductor device will no longer be able to be obtained. [0006]
  • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and connection terminal and a method of production of the same. [0007]
  • To attain the above object, according to a first object of the present invention, there is provided a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through a board in a thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between an outer circumference of the high dielectric constant material and an inner wall of the attachment hole, provided as a coaxial structure having the conductor wire as its center. [0008]
  • Preferably, at least one of the signal wires provided at the board is comprised of, in an attachment hole passing through the board in a thickness direction, a signal wire at the core, a low dielectric constant material, and a conductor layer, formed as a coaxial cable part matching the impedance. [0009]
  • According to a second aspect of the present invention, there is provided a method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising providing an attachment hole passing through a board in a thickness direction and press-fitting into the attachment hole a capacitor cable comprised of a conductor wire at the core, a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness, and a conductor sheath covering the outer circumference of the high dielectric constant material so as to attach the capacitor to the board. [0010]
  • According to a third aspect of the present invention, there is provided a method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising providing an attachment hole passing through a board in a thickness direction, forming a conductor layer at an inner wall of the attachment hole, and press-fitting into the attachment hole formed with the conductor layer a capacitor cable comprised of a conductor wire at the core and a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness so as to attach the capacitor to the board.[0011]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein: [0012]
  • FIG. 1 is a sectional view of the state of a semiconductor package according to the present invention mounting a semiconductor chip; [0013]
  • FIGS. 2A to [0014] 2D are sectional views of the process of production of a semiconductor package according to the present invention; and
  • FIGS. 3A and 3B are perspective views of capacitor cables used for the production of the semiconductor package.[0015]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Preferred embodiments of the present invention will be described in detail below while referring to the attached figures. [0016]
  • FIG. 1 is a sectional view of the configuration of a semiconductor package according to an embodiment of the present invention. The figure shows the state of a semiconductor package [0017] 20 on which a semiconductor chip 10 is mounted. The characterizing feature of the semiconductor package of the present embodiment is the attachment of a capacitor 30 passing through a board 22 of the semiconductor package 20 matched with the position of arrangement of a connection terminal 10 a of the semiconductor chip 10.
  • The capacitor [0018] 30 is comprised of a conductor wire 32, a high dielectric constant material 34 covering this at a predetermined thickness, and a conductor sheath 36 serving as a conductor layer covering the outer circumference of the high dielectric constant material 34. The conductor wire 32 and the conductor sheath 36 are arranged concentrically. The capacitor 30 formed by the conductor wire 32, high dielectric constant material 34, and conductor sheath 36 therefore has a coaxial structure. The high dielectric constant material 34 is for obtaining a required electrostatic capacitance between the conductor wire 32 and the conductor sheath 36. The conductor wire 32 and conductor sheath 36 act as electrodes of the capacitor 30. The high dielectric constant material 34 is formed by strontium titanate, barium titanate, or another high dielectric constant material or an organic material in which a high dielectric constant material is mixed as a filler in order to obtain the required electrostatic capacitance.
  • In the semiconductor package of the present embodiment, the capacitor [0019] 30 is used for the purpose of suppressing fluctuation of the power supply voltage, so the conductor wire 32 is connected to the power supply line and the conductor sheath 36 covering the outer circumference of the high dielectric constant material 34 is connected to a ground line to become the ground potential. Due to this, the capacitor 30 is provided between the power supply line and ground line of the electronic circuit.
  • As shown in FIG. 1, the capacitor [0020] 30 fits in an attachment hole passing through the board 22 in the thickness direction as a coaxial structure. The conductor wire 32 is directly connected to the connection terminal 10 a of the semiconductor chip 10. The conductor wire 32 is arranged so as to pass through the capacitor 30 vertically. It is both a structural part of the capacitor 30 and wiring connecting the connection terminal 10 a and the power supply. Due to this, the connection terminal 10 a and the capacitor are connected at the shortest distance without any detour in the wiring. The length of the wiring connecting the capacitor 30 and the connection terminal 10 a becomes the shortest and the inductance of the wiring portion becomes the smallest. Therefore, it is possible to effectively suppress deterioration of the characteristics when handling a high frequency signal of several GHz. In the structure of an ordinary semiconductor package, the inductance becomes 200 to 300 pH, but according to the present structure, it is possible to reduce the inductance to 10 to 50 pH.
  • In FIG. 1, reference numeral [0021] 40 is a coaxial cable part for impedance matching provided at the connection part of a signal line. Reference numeral 41 is a conductor wire serving as the signal line, 42 a low dielectric constant material, and 43 a conductor sheath covering the outer circumference of the low dielectric constant material 42. The conductor sheath 43 is connected to a ground wire and becomes the ground potential. The coaxial cable part 40 is characterized by formation into a coaxial structure for matching the impedance at the input/output terminals of the conductor wire 41 forming the signal wire with the characteristic impedance. The low dielectric constant material 42 is a dielectric material used for matching the characteristic impedance of 50 Ω. The dielectric material forming the capacitor 30 has a specific dielectric constant of 30 to 40, while the low dielectric constant material 42 is a material of a low specific dielectric constant of about 3.
  • In the semiconductor package of the illustrated example, reference numeral [0022] 45 indicates a signal wire similar to the conductor wire 41, but this is not formed into a coaxial structure since this signal wire is for the input/output of a low frequency signal in the semiconductor package of this embodiment.
  • Reference numeral [0023] 46 is a ground wire. The ground wire 46 is electrically connected to the conductor sheaths 36 and 43 through an interconnect pattern 47 provided at an inside layer of the board 22, whereby the conductor sheaths 36 and 43 become the ground potential. Reference numerals 50 are external connection terminals provided at the bottom of the board 22. The external connection terminals 50 are formed by bonding solder balls with lands 52 formed on the surface of the board 22.
  • FIGS. 2A to [0024] 2D show the process of production of the above semiconductor package.
  • FIG. 2A shows a board [0025] 22 formed with conductor wires forming a signal wire 45 and a ground wire 46 and an interconnect pattern 47. The board 22 can be formed as a multilayer board comprised of a core board made of a resin on the two sides of which interconnect layers are laminated through insulation layers.
  • FIG. 2B shows the state with attachment holes [0026] 60 and 62 formed passing through the board 22 in the thickness direction. The attachment holes 60 and 62 are formed by drilling at portions for forming the above-mentioned capacitor 30 and high frequency signal use coaxial cable part 40. The attachment holes 60 and 62 are formed to have inside diameter dimensions matching the outside diameter dimensions of the capacitor 30 and coaxial cable part 40 to be attached to the board 22.
  • FIG. 2C shows the state with the capacitor [0027] 30 and the coaxial cable part 40 attached to the attachment holes 60 and 62 formed in the board 22. To attach the capacitor 30 to the attachment hole 60, a capacitor cable formed in advance into a cylindrical shape is inserted into the attachment hole 60.
  • FIG. 3A is a perspective view of a capacitor cable [0028] 30 a. The capacitor cable 30 a is comprised of the above-mentioned conductor wire 32, a high dielectric constant material 34, and a conductor sheath 36 formed into the shape of a long coaxial cable. The capacitor 30 can be attached by press-fitting the capacitor cable 30 a cut to a predetermined length into the attachment hole 60 of the board 22.
  • By inserting the capacitor [0029] 30 into the attachment hole 60, the conductor sheath 36 contacts the interconnect pattern 47 exposed at the wall of the inner circumference of the attachment hole 60, whereby the interconnect pattern 47 and conductor sheath 36 are electrically connected.
  • Note that as the method of attaching the capacitor [0030] 30 to the attachment hole 60, aside from the method of using the capacitor cable 30 a shown in FIG. 3A, the method of using a capacitor cable 30 b shown in FIG. 3B is also possible. The capacitor cable 30 b shown in FIG. 3B lacks the conductor sheath 36 of the capacitor cable 30 a shown in FIG. 3A.
  • When using the capacitor cable [0031] 30 b shown in FIG. 3B to attach the capacitor 30 to the board 22, first an attachment hole 60 is formed in the board 22, then the inside wall of the attachment hole 60 is plated to form a conductor layer at the inside wall of the attachment hole 60, then the capacitor cable 30 b shown in FIG. 3B is press-fit in the attachment hole 60. In this case, the conductor layer becomes the ground potential, and the conductor layer provided at the inside wall of the attachment hole 60 performs the same function as the conductor sheath 36 of the capacitor cable 30 a shown in FIG. 3A for formation of the capacitor 30.
  • The method of attaching the coaxial cable part [0032] 40 for a signal wire of the board 22 is similar to the method of attaching the capacitor 30 at the board 22. That is, it is possible to attach the coaxial cable part 40 shown in FIG. 2C by press-fitting a coaxial cable formed in the same manner as the capacitor cable 30 a or 30 b shown in FIG. 3A or 3B in the attachment hole 62 provided in the board 22. The coaxial cable may be formed with a conductor sheath at the outer surface of the low dielectric constant material 42 or not be formed with the conductor sheath. When no conductor sheath is formed at the outer surface of the low dielectric constant material 42, it is sufficient, in the same way as above, to plate the inner wall of the attachment hole 62 to form a conductor layer.
  • FIG. 2D shows the state of formation of an interconnect pattern on the surface of the board [0033] 22 after formation of the capacitor 30 and coaxial cable part 40 at the board 22. The interconnect pattern can be obtained by forming a conductor layer on the top and bottom surfaces of the board 22 by plating etc., then etching the conductor layer to form a predetermined pattern. Reference numerals 52 are lands for connection with external connection terminal, while reference numerals 54 are pads for connection with bumps of the semiconductor chip 10.
  • In this way, it is possible to obtain a semiconductor package mounting a capacitor [0034] 30 in an arrangement passing through the board 22 in the thickness direction. The semiconductor package of the present embodiment, as explained above, has the conductor wire 32 forming the power supply line serving as a part of the capacitor 30 and has the conductor wire 32 directly connected to the connection terminal 10 a and the length of the power supply line formed shortest, so suppression of fluctuation of the power supply voltage and reduction of the inductance are realized and a package with extremely good high frequency characteristics is formed. Further, for the signal wire transmitting the high frequency signal, it is possible to improve the high frequency characteristics by matching with the characteristic impedance. In this respect as well, a semiconductor package superior in high frequency characteristics is obtained.
  • Summarizing the effects of the invention, according to the semiconductor package and method of production of the same of the present invention, it is possible to easily mount a capacitor to a board so as to suppress fluctuation of the power supply voltage and possible to minimize the length of the wiring connecting the capacitor and the connection terminal so as to lower the inductance. Therefore, it is possible to provide a semiconductor package with extremely superior high frequency characteristics. [0035]
  • While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention. [0036]

Claims (4)

    What is claimed is:
  1. 1. A semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire as its center.
  2. 2. A semiconductor package as set forth in claim 1, wherein at least one of the signal wires provided at said board is comprised of, in an attachment hole passing through said board in a thickness direction, a signal wire at the core, a low dielectric constant material, and a conductor layer, formed as a coaxial wire matching the impedance.
  3. 3. A method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising:
    providing an attachment hole passing through a board in a thickness direction and
    press-fitting into said attachment hole a capacitor cable comprised of a conductor wire at the core, a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness, and a conductor sheath covering the outer circumference of the high dielectric constant material so as to attach the capacitor to said board.
  4. 4. A method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising:
    providing an attachment hole passing through a board in a thickness direction,
    forming a conductor layer at an inner wall of said attachment hole, and
    press-fitting into said attachment hole formed with said conductor layer a capacitor cable comprised of a conductor wire at the core and a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness so as to attach the capacitor to said board.
US10281791 2001-11-07 2002-10-28 Semiconductor package and method of production thereof Abandoned US20030085471A1 (en)

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Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20060278993A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip connector
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US20060278989A1 (en) * 2005-06-14 2006-12-14 John Trezza Triaxial through-chip connection
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
EP1775761A1 (en) * 2004-07-06 2007-04-18 Tokyo Electron Limited Through substrate and interposer, and method for manufacturing through substrate
US20070124930A1 (en) * 2005-12-02 2007-06-07 Cisco Technology, Inc. Coaxial via in PCB for high-speed signaling designs
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070257708A1 (en) * 2004-08-31 2007-11-08 Kabushiki Kaisha Toshiba Semiconductor module
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US20080090413A1 (en) * 2006-10-17 2008-04-17 John Trezza Wafer via formation
KR100856450B1 (en) * 2004-07-06 2008-09-04 도쿄엘렉트론가부시키가이샤 Method for manufacturing through substrate
US20080246145A1 (en) * 2007-04-05 2008-10-09 John Trezza Mobile binding in an electronic connection
US20080245846A1 (en) * 2007-04-05 2008-10-09 John Trezza Heat cycle-able connection
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US20090267219A1 (en) * 2007-04-23 2009-10-29 John Trezza Ultra-thin chip packaging
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US20100163295A1 (en) * 2008-12-31 2010-07-01 Mihir Roy Coaxial plated through holes (pth) for robust electrical performance
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US20110108973A1 (en) * 2009-11-12 2011-05-12 Industrial Technology Research Institute Chip package structure and method for fabricating the same
US20130048344A1 (en) * 2011-08-30 2013-02-28 Star Technologies Inc. High frequency circuit board
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
WO2015099668A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
US9275975B2 (en) 2014-03-28 2016-03-01 Intel Corporation Electronic package and method of connecting a first die to a second die to form an electronic package
JPWO2015141107A1 (en) * 2014-03-18 2017-04-06 株式会社日本マイクロニクス battery
US20170231083A1 (en) * 2016-02-04 2017-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method of manufacturing the same

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4005451B2 (en) * 2002-08-29 2007-11-07 富士通株式会社 Multilayer board and a semiconductor device
US7767876B2 (en) * 2003-10-30 2010-08-03 The Procter & Gamble Company Disposable absorbent article having a visibly highlighted wetness sensation member
JP2006019455A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor device and manufacturing method thereof
CN100505178C (en) 2004-07-06 2009-06-24 东京毅力科创株式会社 Through substrate and interposer, and method for manufacturing through substrate
JP4185499B2 (en) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7701052B2 (en) * 2005-10-21 2010-04-20 E. I. Du Pont De Nemours And Company Power core devices
US7767913B2 (en) * 2006-02-20 2010-08-03 Micron Technology, Inc. Electronic devices including conductive vias having two or more conductive elements for providing electrical communication between traces in different planes in a substrate, and accompanying methods
JP2007227002A (en) 2006-02-21 2007-09-06 Sumitomo Electric Ind Ltd Wiring member
JP2008028188A (en) * 2006-07-21 2008-02-07 Sharp Corp Printed wiring board, method for manufacturing the same, and electronic apparatus
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7570493B2 (en) * 2006-11-16 2009-08-04 Sony Ericsson Mobile Communications Printed circuit board with embedded circuit component
KR20090096174A (en) * 2008-03-07 2009-09-10 주식회사 하이닉스반도체 Circuit substrate and semiconductor package using the circuit substrate
CN101661920B (en) 2008-08-26 2011-06-29 欣兴电子股份有限公司 Chip packaging carrying plate and making method thereof
US20100327433A1 (en) * 2009-06-25 2010-12-30 Qualcomm Incorporated High Density MIM Capacitor Embedded in a Substrate
US8558345B2 (en) * 2009-11-09 2013-10-15 International Business Machines Corporation Integrated decoupling capacitor employing conductive through-substrate vias
FR2953069B1 (en) * 2009-11-24 2012-03-09 Eads Europ Aeronautic Defence Device for protecting against lightning of a receiver antenna and the plane comprising
US8519515B2 (en) * 2011-04-13 2013-08-27 United Microlectronics Corp. TSV structure and method for forming the same
JP5938918B2 (en) * 2012-01-24 2016-06-22 株式会社デンソー The semiconductor device having a wiring substrate
CN104604345A (en) * 2012-08-31 2015-05-06 索尼公司 Wiring substrate and wiring substrate fabrication method
US9368440B1 (en) * 2013-07-31 2016-06-14 Altera Corporation Embedded coaxial wire and method of manufacture
US9378778B1 (en) 2015-06-14 2016-06-28 Darryl G. Walker Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072690A (en) * 1998-01-15 2000-06-06 International Business Machines Corporation High k dielectric capacitor with low k sheathed signal vias
US6314013B1 (en) * 1998-11-23 2001-11-06 Micron Technology, Inc. Stacked integrated circuits
US20020017399A1 (en) * 2000-08-11 2002-02-14 Huey-Ru Chang Coaxial via hole and process of fabricating the same
US6605551B2 (en) * 2000-12-08 2003-08-12 Intel Corporation Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05167258A (en) 1991-12-12 1993-07-02 Nec Corp Multilayer wiring board
JPH10163A (en) 1996-06-15 1998-01-06 Chubu Corp:Kk Method for using heat roaster
JP4390368B2 (en) 2000-06-08 2009-12-24 新光電気工業株式会社 A method for manufacturing a wiring board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072690A (en) * 1998-01-15 2000-06-06 International Business Machines Corporation High k dielectric capacitor with low k sheathed signal vias
US6314013B1 (en) * 1998-11-23 2001-11-06 Micron Technology, Inc. Stacked integrated circuits
US20020017399A1 (en) * 2000-08-11 2002-02-14 Huey-Ru Chang Coaxial via hole and process of fabricating the same
US6717071B2 (en) * 2000-08-11 2004-04-06 Industrial Technology Research Institute Coaxial via hole and process of fabricating the same
US6605551B2 (en) * 2000-12-08 2003-08-12 Intel Corporation Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance

Cited By (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1775761A1 (en) * 2004-07-06 2007-04-18 Tokyo Electron Limited Through substrate and interposer, and method for manufacturing through substrate
US7866038B2 (en) 2004-07-06 2011-01-11 Tokyo Electron Limited Through substrate, interposer and manufacturing method of through substrate
KR100856450B1 (en) * 2004-07-06 2008-09-04 도쿄엘렉트론가부시키가이샤 Method for manufacturing through substrate
US20070246253A1 (en) * 2004-07-06 2007-10-25 Masami Yakabe Through Substrate, Interposer and Manufacturing Method of Through Substrate
EP1775761A4 (en) * 2004-07-06 2007-08-29 Tokyo Electron Ltd Through substrate and interposer, and method for manufacturing through substrate
US7633153B2 (en) * 2004-08-31 2009-12-15 Kabushiki Kaisha Toshiba Semiconductor module
US20070257708A1 (en) * 2004-08-31 2007-11-08 Kabushiki Kaisha Toshiba Semiconductor module
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
US20060278994A1 (en) * 2005-06-14 2006-12-14 John Trezza Inverse chip connector
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US20060278989A1 (en) * 2005-06-14 2006-12-14 John Trezza Triaxial through-chip connection
US20060278331A1 (en) * 2005-06-14 2006-12-14 Roger Dugas Membrane-based chip tooling
US20060278992A1 (en) * 2005-06-14 2006-12-14 John Trezza Post & penetration interconnection
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060278988A1 (en) * 2005-06-14 2006-12-14 John Trezza Profiled contact
US20060281292A1 (en) * 2005-06-14 2006-12-14 John Trezza Rigid-backed, membrane-based chip tooling
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
US20060281307A1 (en) * 2005-06-14 2006-12-14 John Trezza Post-attachment chip-to-chip connection
US7157372B1 (en) * 2005-06-14 2007-01-02 Cubic Wafer Inc. Coaxial through chip connection
US20060281243A1 (en) * 2005-06-14 2006-12-14 John Trezza Through chip connection
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US20070120241A1 (en) * 2005-06-14 2007-05-31 John Trezza Pin-type chip tooling
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US20070138562A1 (en) * 2005-06-14 2007-06-21 Cubic Wafer, Inc. Coaxial through chip connection
US20070158839A1 (en) * 2005-06-14 2007-07-12 John Trezza Thermally balanced via
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070167004A1 (en) * 2005-06-14 2007-07-19 John Trezza Triaxial through-chip connection
US20070196948A1 (en) * 2005-06-14 2007-08-23 John Trezza Stacked chip-based system and method
US20070197013A1 (en) * 2005-06-14 2007-08-23 Cubic Wafer, Inc. Processed Wafer Via
US20060278980A1 (en) * 2005-06-14 2006-12-14 John Trezza Patterned contact
US20070228576A1 (en) * 2005-06-14 2007-10-04 John Trezza Isolating chip-to-chip contact
US20060281309A1 (en) * 2005-06-14 2006-12-14 John Trezza Coaxial through chip connection
US20060278966A1 (en) * 2005-06-14 2006-12-14 John Trezza Contact-based encapsulation
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US20080171174A1 (en) * 2005-06-14 2008-07-17 John Trezza Electrically conductive interconnect system and method
US8643186B2 (en) 2005-06-14 2014-02-04 Cufer Asset Ltd. L.L.C. Processed wafer via
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20100148343A1 (en) * 2005-06-14 2010-06-17 John Trezza Side stacking apparatus and method
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US20090137116A1 (en) * 2005-06-14 2009-05-28 Cufer Asset Ltd. L.L.C. Isolating chip-to-chip contact
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US8232194B2 (en) 2005-06-14 2012-07-31 Cufer Asset Ltd. L.L.C. Process for chip capacitive coupling
US20060278993A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip connector
US7659202B2 (en) 2005-06-14 2010-02-09 John Trezza Triaxial through-chip connection
US8197626B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US8154131B2 (en) 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7847412B2 (en) 2005-06-14 2010-12-07 John Trezza Isolating chip-to-chip contact
US8093729B2 (en) 2005-06-14 2012-01-10 Cufer Asset Ltd. L.L.C. Electrically conductive interconnect system and method
US8084851B2 (en) 2005-06-14 2011-12-27 Cufer Asset Ltd. L.L.C. Side stacking apparatus and method
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US20100197134A1 (en) * 2005-06-14 2010-08-05 John Trezza Coaxial through chip connection
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7785987B2 (en) 2005-06-14 2010-08-31 John Trezza Isolating chip-to-chip contact
US7785931B2 (en) 2005-06-14 2010-08-31 John Trezza Chip-based thermo-stack
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7808111B2 (en) 2005-06-14 2010-10-05 John Trezza Processed wafer via
US20100261297A1 (en) * 2005-06-14 2010-10-14 John Trezza Remote chip attachment
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US8067312B2 (en) 2005-06-14 2011-11-29 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20110212573A1 (en) * 2005-06-14 2011-09-01 John Trezza Rigid-backed, membrane-based chip tooling
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US7919870B2 (en) 2005-06-14 2011-04-05 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US7932584B2 (en) 2005-06-14 2011-04-26 Cufer Asset Ltd. L.L.C. Stacked chip-based system and method
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US7946331B2 (en) 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US7404250B2 (en) * 2005-12-02 2008-07-29 Cisco Technology, Inc. Method for fabricating a printed circuit board having a coaxial via
US20070124930A1 (en) * 2005-12-02 2007-06-07 Cisco Technology, Inc. Coaxial via in PCB for high-speed signaling designs
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US7871927B2 (en) 2006-10-17 2011-01-18 Cufer Asset Ltd. L.L.C. Wafer via formation
US20080090413A1 (en) * 2006-10-17 2008-04-17 John Trezza Wafer via formation
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US7748116B2 (en) 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US20080246145A1 (en) * 2007-04-05 2008-10-09 John Trezza Mobile binding in an electronic connection
US20080245846A1 (en) * 2007-04-05 2008-10-09 John Trezza Heat cycle-able connection
US7850060B2 (en) 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
US20090267219A1 (en) * 2007-04-23 2009-10-29 John Trezza Ultra-thin chip packaging
US7960210B2 (en) 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US8227706B2 (en) * 2008-12-31 2012-07-24 Intel Corporation Coaxial plated through holes (PTH) for robust electrical performance
US20100163295A1 (en) * 2008-12-31 2010-07-01 Mihir Roy Coaxial plated through holes (pth) for robust electrical performance
US8102058B2 (en) * 2009-11-12 2012-01-24 Industrial Technology Research Institute Chip package structure and method for fabricating the same
US20110108973A1 (en) * 2009-11-12 2011-05-12 Industrial Technology Research Institute Chip package structure and method for fabricating the same
US20130048344A1 (en) * 2011-08-30 2013-02-28 Star Technologies Inc. High frequency circuit board
US9911689B2 (en) 2013-12-23 2018-03-06 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
WO2015099668A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
JPWO2015141107A1 (en) * 2014-03-18 2017-04-06 株式会社日本マイクロニクス battery
US9741686B2 (en) 2014-03-28 2017-08-22 Intel Corporation Electronic package and method of connecting a first die to a second die to form an electronic package
US9275975B2 (en) 2014-03-28 2016-03-01 Intel Corporation Electronic package and method of connecting a first die to a second die to form an electronic package
US20170231083A1 (en) * 2016-02-04 2017-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method of manufacturing the same
US9807867B2 (en) * 2016-02-04 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method of manufacturing the same

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