US20060278966A1 - Contact-based encapsulation - Google Patents

Contact-based encapsulation Download PDF

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Publication number
US20060278966A1
US20060278966A1 US11/329,874 US32987406A US2006278966A1 US 20060278966 A1 US20060278966 A1 US 20060278966A1 US 32987406 A US32987406 A US 32987406A US 2006278966 A1 US2006278966 A1 US 2006278966A1
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United States
Prior art keywords
chip
wafer
contact
chips
process
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Abandoned
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US11/329,874
Inventor
John Trezza
John Callahan
Gregory Dudoff
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Cufer Asset Ltd LLC
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Cubic Wafer Inc
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Priority to US69075905P priority Critical
Application filed by Cubic Wafer Inc filed Critical Cubic Wafer Inc
Priority to US11/329,874 priority patent/US20060278966A1/en
Assigned to CUBIC WAFER, INC. reassignment CUBIC WAFER, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CALLAHAN, JOHN, DUDOFF, GREGORY, TREZZA, JOHN
Priority claimed from PCT/US2006/023246 external-priority patent/WO2006138423A2/en
Priority claimed from CN200680029328XA external-priority patent/CN101796636B/en
Publication of US20060278966A1 publication Critical patent/US20060278966A1/en
Priority claimed from US11/688,088 external-priority patent/US7687400B2/en
Assigned to CUFER ASSET LTD. L.L.C. reassignment CUFER ASSET LTD. L.L.C. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CUBIC WAFER, INC.
Application status is Abandoned legal-status Critical

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Abstract

An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

Description

    FIELD OF THE INVENTION
  • The present invention relates to semiconductors and, more particularly, to electrical connections for such devices.
  • BACKGROUND
  • Making electrical contacts that extend all the way through an electronic chip (by creating electrically conductive vias) is difficult. Doing so with precision or controlled repeatability, let alone in volume is nearly impossible unless one or more of the following is the case: a) the vias are very shallow, i.e. significantly less than 100 microns in depth, b) the via width is large, or c) the vias are separated by large distances, i.e. many times the via width. The difficulty is compounded when the vias are close enough for signal cross-talk to occur, or if the chip through which the via passes has a charge, because the conductor in the via can not be allowed act as a short, nor can it carry a charge different from the charge of the pertinent portion of the chip. In addition, conventional processes, to the extent they exist, are unsuitable for use with formed integrated circuit (IC) chips (i.e. containing active semiconductor devices) and increase cost because those processes can damage the chips and thereby reduce the ultimate yield. Adding further to the above difficulties is the need to be concerned with capacitance and resistance problems when the material the via passes through has a charge or when the frequencies of the signals to be carried through the vias are very high, for example, in excess of about 0.3 GHz.
  • Indeed, there are numerous problems that are extant in the semiconductor art including: use of large, non-scaleable packaging; assembly costs don't scale like semiconductors; chip cost is proportional to area, and the highest performance processes are the most expensive, but only fraction of chip area actually requires high-performance processes; current processes are limited in voltage and other technologies; chip designers are limited to one process and one material for design; large, high power pad drivers are needed for chip-to-chip (through package) connections; even small changes or correction of trivial design errors require fabrication of one or more new masks for a whole new chip; making whole new chips requires millions of dollars in mask costs alone; individual chips are difficult and complicated to test and combinations of chips are even more difficult to test prior to complete packaging.
  • Accordingly, there is a significant need in the art for technology that can address one or more of the above problems.
  • SUMMARY OF THE INVENTION
  • We have developed a process that facilitates forming chip to chip electrical connections with vias that pass through a wafer, a preformed third-party chip, or a doped semiconductor substrate. Aspects described herein aid in the approach and represent improvements in the general field of joining of chips to each other.
  • One aspect involves an electrical connection between two chips has an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.
  • Another aspect involves a rigid metal material located between the malleable electrically conductive metal and one of the first or second barrier metals.
  • The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a simplified representation a side view of a portion of a chip containing multiple active electronic devices;
  • FIG. 2 is a top view of the upper surface of the specified area of FIG. 1;
  • FIG. 3 shows a simplified cutaway view of the portion of FIG. 1;
  • FIG. 4 is a top view of the upper surface of the specified area of FIG. 1 following creation of the trench shown in side view in FIG. 3;
  • FIG. 5 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;
  • FIG. 6 is a top view of the upper surface of the specified area of FIG. 1 following the filling of the trench with electrically insulating material shown in side view in FIG. 5;
  • FIG. 7 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;
  • FIG. 8 is a top view of the upper surface of the specified area 124 of FIG. 1 following the creation of the via trench;
  • FIG. 9 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;
  • FIG. 10 is a top view of the upper surface of the specified area of FIG. 1 following metalization of the via trench;
  • FIG. 11 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued optional processing;
  • FIG. 12 is a top view of the upper surface of the specified area of FIG. 1 following the optional introduction of the bonding substance into the remaining void;
  • FIG. 13 shows a simplified cutaway view of the portion of FIG. 1 as a result of other optional processing;
  • FIG. 14 is a top view of the upper surface of the specified area of FIG. 1 following the optional addition of the finishing substance into the remaining void;
  • FIG. 15 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;
  • FIG. 16 shows a simplified cutaway view of the portion of FIG. 1 following thinning of the substrate to remove the bottom metalization;
  • FIG. 17 shows a simplified cutaway view of the portion of FIG. 5 as a result of processing of an alternative variant;
  • FIG. 18 is a top view of a section taken below the specified area of FIG. 1 following the creation of the via trench;
  • FIG. 19 shows a simplified cutaway view of the portion of FIG. 5 as a result of further processing in the manner described in connection with FIG. 9;
  • FIG. 20 shows a simplified cutaway view of the portion of FIG. 5 as a result of further optional processing in the manner described in connection with FIG. 11;
  • FIG. 21 shows a simplified cutaway view of the portion of FIG. 5 as a result of further optional processing in the manner described in connection with FIG. 13;
  • FIG. 22 shows a simplified cutaway view of the portion of FIG. 5 as a result of thinning the substrate to expose the bottom metalization in the manner described in connection with FIG. 15 in the alternative variant of FIG. 17;
  • FIG. 23 shows a simplified cutaway view of the portion of FIG. 5 as a result of thinning the substrate to remove the bottom metalization in the manner described in connection with FIG. 16 for the alternative variant of FIG. 17;
  • FIG. 24 illustrates in simplified form a dual conductor variant following metallization of the sidewalls;
  • FIG. 25 illustrates in simplified form the dual conductor variant following filling the trench with electrically insulating material 500;
  • FIG. 26 illustrates in simplified form, a via trench created by removing the entire island of semiconductor material;
  • FIG. 27 illustrates in simplified form, a via trench created by removing only an inner portion island of semiconductor material;
  • FIG. 28 illustrates in simplified form one example dual-conductor variant;
  • FIG. 29 illustrates in simplified form another example dual-conductor variant;
  • FIGS. 30A and 30B respectively illustrate use of an optional additional thermally created dielectric or insulator in the approaches of FIGS. 28 and 29;
  • FIG. 31 illustrates in simplified form one example three-conductor variant;
  • FIG. 32 shows a simplified cutaway view of a portion of an example alternative chip implementation similar to the implementation of FIG. 9 through FIG. 16 except the void remaining after metalization is not filled;
  • FIG. 33 shows a simplified cutaway view of a portion of an example alternative chip implementation, similar to that of FIG. 23 except the void remaining after metalization is not filled;
  • FIG. 34 and FIG. 35 each show the respective cross sections of the chips of FIG. 32 and FIG. 33 following hybridization to each other;
  • FIG. 36 shows the implementation of FIG. 34 after optional coating with an insulator or conformal coating;
  • FIG. 37 shows representative examples of cross sections of annulus trenches;
  • FIG. 38 illustrates in simplified form, a generic overview form a process for preparing a wafer for stacking;
  • FIGS. 39 through 41 illustrate portions of example chips processed to create through-chip connections using different variants of the herein-described processes that have, thereafter, been stacked together to form a chip unit;
  • FIG. 42 illustrates in simplified form the process for making a back to front variant;
  • FIG. 43 illustrates in simplified form the process for making a capacitive coupling variant;
  • FIG. 44 illustrates in simplified form the process for making a pre-connect variant;
  • FIGS. 45 and 46 illustrate in simplified form, example tack and fuse parameters;
  • FIG. 47 is a simplified example involving “minimal” contacts;
  • FIG. 48 is a simplified example involving an extended contact;
  • FIG. 49 illustrates a portion of a stack of semiconductor chips each having through-chip connections as described herein;
  • FIG. 50 illustrates a portion of the simplified stack of the chips shown in FIG. 49 stacked using a the post and penetration connection approach;
  • FIG. 51 illustrates in simplified form a void within the metalization filled by a pre-formed post;
  • FIG. 52 illustrates, in simplified form, the chip of FIG. 51 after it has been hybridized to an electronic chip;
  • FIG. 53 through FIG. 71 illustrate a simplified example variant of a basic contact formation and hybridization approach;
  • FIG. 72 through FIG. 87 illustrate an alternative simplified example variant of a basic contact formation and hybridization approach;
  • FIG. 88 through FIG. 91 illustrate, in simplified parallel form, a first part of two further example variant approaches for forming what will later become a rigid post on the back side of a daughter wafer;
  • FIG. 92 is a cross sectional photograph of example sloping vias;
  • FIG. 93 is a photograph of an example via having a depth of 100 microns and a diameter of 20 microns;
  • FIG. 94 is a photograph, in cross section, of a chip having pointed vias formed therein;
  • FIG. 95 through FIG. 102 illustrate, in simplified parallel form, a second part of the two further example variant from FIGS. 88 through 91;
  • FIG. 103 through FIG. 125 illustrate, in simplified parallel form, a variant process of preparing wafers for hybridization to other elements;
  • FIG. 126 through FIG. 139 illustrate in abbreviated form, a further variant process of preparing wafers for hybridization to other elements;
  • FIG. 140 which illustrates, in simplified form, a daughter wafer contact and a mother wafer contact immediately prior to the tack phase;
  • FIG. 141 shows, in simplified form, the contacts of FIG. 140 after the fuse process is complete;
  • FIG. 142 illustrates a profiled malleable contact;
  • FIGS. 143A through 143P are representative, illustrative examples of some of the myriad of possible mother contact profiles;
  • FIG. 144 is a photograph of an alternative example profiled malleable contact;
  • FIG. 145 is a photograph of a profiled rigid contact designed to penetrate the malleable contact of FIG. 144;
  • FIG. 146 illustrates, in simplified form, a further profiled conatct example;
  • FIGS. 147 through 152 illustrate one variant process for implementing the well attach concept;
  • FIGS. 153 through 156 illustrate, in simplified form, classes of reverse well variants;
  • FIGS. 157A and 157B are, respectively, photographs in longitudinal cross section of a set of 15 micron diameter vias extending 135 microns deep and 25 micron diameter vias extending 155 microns deep;
  • FIG. 158, is a photograph of a via dimilar to those of FIGS. 157A and 157B but not filled all of the way to the bottom;
  • FIGS. 159 through 167 illustrate a further variant of a Class II-type rigid well attach approach;
  • FIG. 168 through FIG. 170 show a further variant of the well attach approach in which the chips are attached to one another by separate remote contacts;
  • FIGS. 171A and 171B illustrate top views of alternative remote contact variants;
  • FIG. 172 illustrates cross sections of example coaxial contacts;
  • FIGS. 173 through 175 illustrate example uses of coaxial contacts;
  • FIGS. 176 through 179 illustrate two simple examples of hermetic sealing using contacts as described herein;
  • FIG. 180 is a chart summarizing different approaches for forming other variants using the rigid/malleable contact paradigm;
  • FIGS. 181 and 182 are charts summarizing different approaches for for