CN1417856A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

Info

Publication number
CN1417856A
CN1417856A CN02146445A CN02146445A CN1417856A CN 1417856 A CN1417856 A CN 1417856A CN 02146445 A CN02146445 A CN 02146445A CN 02146445 A CN02146445 A CN 02146445A CN 1417856 A CN1417856 A CN 1417856A
Authority
CN
China
Prior art keywords
capacitor
installing hole
lead
semiconductor packages
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN02146445A
Other languages
English (en)
Other versions
CN1306601C (zh
Inventor
饭岛隆广
六川昭雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN1417856A publication Critical patent/CN1417856A/zh
Application granted granted Critical
Publication of CN1306601C publication Critical patent/CN1306601C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/642Capacitive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • H01L2223/6622Coaxial feed-throughs in active or passive substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809Coaxial layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种高频特性优越的半导体封装,能容易安装大尺寸的电容器,由此能够抑制电源电压的波动,并且能够减少连接电容器和连接端的布线部分的电感,即,一种半导体封装,安装有电容器用于抑制电源电压波动,其中在厚度方向中穿过板的安装孔中,电容器由以下组成:一端连接到半导体芯片连接端的导线、以预定厚度覆盖导线的高介电常数材料、以及设置在高介电常数材料外周边和安装孔内壁之间的导体层,具有导线作为它的中心的同轴结构,并且提供一种半导体封装的制造方法。

Description

半导体封装及其制造方法
发明领域
本发明涉及半导体封装及其制造方法,特别涉及高频特性优越的半导体封装及其制造方法。
相关技术介绍
在处理微处理器等的高频信号的半导体封装中,信号传输路径中的频率特性成为问题。因此,通过使特性阻抗匹配或尽可能使信号线缩短等措施防止输入和输出端处的信号反射。例如,作为使特性阻抗匹配的方法,有使信号传输路径形状上共面实质上形成同轴电缆的方法,有在电路板中提供凹槽并将同轴电缆插入凹槽中得到同轴结构的方法(日本待审专利公开(Kokai)No.5-167258)等。此外,作为缩短信号线的方法,实践中将芯片电容器和其它电路部分设置得尽可能靠近半导体芯片的连接端。
然而,如果半导体封装处理的信号频率变为高达1GHz,电源中的波动会影响频率特性,所以实践中将大尺寸的电容器连接到电源线,以抑制传输信号时电源中的任何压降。对于由安装在电路板上的半导体芯片组成的现有技术的半导体器件,通过将芯片电容器设置在与半导体芯片的安装表面相对的电路板的表面上或将芯片电容器设置在半导体芯片附近,将电容器安装在电路上。这样将芯片电容器设置得尽可能靠近半导体芯片的连接端,由此尽可能地减少了传输路径的电感。
然而,半导体器件的工作频率变得较高。如果需要满足工作时将电感值减小到不超过几pH的条件,甚至将芯片电容器设置在与安装半导体芯片的位置相对的表面上尽可能靠近半导体芯片的位置处的方法也产生问题,根据板的厚度或芯片电容器的尺寸,在与电极连接部分处的电感上升超过需要的值,不再能得到半导体器件的需要性能。
发明概述
本发明的一个目的是提供一种高频特性优越的半导体封装,能容易安装大尺寸的电容器,由此能够抑制电源电压的波动,并且能够减少连接电容器和连接端的布线部分的电感,并且提供一种半导体封装的制造方法。
为实现以上目的,根据本发明的第一目的,提供一种半导体封装,安装有电容器用于抑制电源电压波动,其中在厚度方向中穿过板的安装孔中,电容器由以下组成:一端连接到半导体芯片连接端的导线、以预定厚度覆盖导线的高介电常数材料、以及设置在高介电常数材料外周边和安装孔内壁之间的导体层,具有导线作为它的中心的同轴结构。
优选,在厚度方向中穿过板的安装孔中,提供在板上的至少一个信号线由中心的信号线、低介电常数材料、以及导体层组成,形成匹配阻抗的同轴电缆部分。
根据本发明的第二方案,提供一种半导体封装的制造方法,半导体封装安装有电容器用于抑制电源电压波动,该方法包括提供在厚度方向中穿过板的安装孔并将电容器电缆按压到安装孔内,由此将电容器安装到板,电容器电缆由中心的导线、以预定厚度同轴地覆盖导线的高介电常数材料、以及覆盖高介电常数材料外周边的导体包皮组成。
根据本发明的第三方案,提供一种半导体封装的制造方法,半导体封装安装有电容器用于抑制电源电压波动,该方法包括提供在厚度方向中穿过板的安装孔,在安装孔的内壁上形成导体层,并将电容器电缆压入到形成有导体层的安装孔内,由此将电容器安装到板,电容器电缆由中心的导线、以预定厚度同轴地覆盖导线的高介电常数材料组成。
附图简介
从下面参考附图给出的优选实施例的说明中,本发明的这些和其它目的和特点将变得很显然,其中:
图1为根据本发明安装半导体芯片的半导体封装的剖面图;
图2A到2D为根据本发明的半导体封装的制造工艺的剖面图;以及
图3A和3B为制造半导体封装使用的电容器电缆的透视图。
优选实施例的说明
下面参考附图详细介绍本发明的优选实施例。
图1为根据本发明的一个实施例的半导体封装结构的剖面图。图中示出了其上安装有半导体芯片10的半导体封装20。本实施例的半导体封装的特点在于电容器30穿过半导体封装20的板22,与半导体芯片10的连接端10a的设置位置匹配。
电容器30由导线32、以预定厚度覆盖导线32的高介电常数材料34、以及覆盖高介电常数材料34的外周边作为导电层的导体包皮36组成。导线32和导体包皮36同心地设置。由导线32、高介电常数材料34和导体包皮36形成的电容器30具有同轴结构。高介电常数材料34用于在导线32和导体包皮36之间获得需要的静电电容量。导线32和导体包皮36作为电容器30的电极。高介电常数材料34由钛酸锶、钛酸钡或其它高介电常数材料或有机材料形成,其中混合高介电常数材料作为填料以获得需要的静电电容量。
在本实施例的半导体封装中,电容器30用于抑制电源电压的波动,由此导线32连接到电源线,覆盖高介电常数材料34外周边的导体包皮36连接到地线变成地电位。由此,电容器30提供在电子电路的电源线和地线之间。
如图1所示,电容器30装入厚度方向中穿过板22的安装孔中作为同轴结构。导线32直接连接到半导体芯片10的连接端10a。设置导线32垂直地穿过电容器30。这既是电容器30的结构部分也是连接连接端10a和电源的布线。为此,连接端10a和电容器以最短的距离连接,同时布线中没有任何弯路。连接电容器30和连接端10a的布线长度最短,并且布线部分的电感最小。因此,当处理几GHz的高频信号时,可以有效地抑制特性失真。在普通的半导体封装结构中,电感为200到300pH,但根据本结构,电感可以减小到10到50pH。
在图1中,参考数字40是提供在信号线的连接部分用于阻抗匹配的同轴电缆。参考数字41为作为信号线的导线,42是低介电常数材料,43是覆盖低介电常数材料42外周边的导体包皮。导体包皮43连接到地线并且变为地电位。同轴电缆部分40的特点为形成同轴结构,将形成信号线的导线41的输入/输出端处的阻抗与特性阻抗匹配。低介电常数材料42是匹配50Ω的特性阻抗使用的介质材料。形成电容器30的介质材料具有30到40的特定介电常数,而低介电常数材料42具有约为3的特定的低介电常数。
在示出的半导体封装的例子中,参考数字45表示类似于导线41的信号线,但没有形成同轴结构,这是由于该信号线用于本实施例的半导体封装中的低频信号的输入/输出。
参考数字46为地线。通过提供在板22内层的互连图形47,地线46电连接到导体包皮36和43,由此导体包皮36和43变成地电位。参考数字50为提供在板22底部的外部连接端子。通过焊料球与板22表面上形成的焊盘52结合形成外部连接端50。
图2A到2D示出了以上半导体封装的制造工艺。
图2A示出了用形成信号线45和地线46以及互连图形47的导线形成的板22。板22可以形成为多层板,由树脂制成的芯板组成,在它的两面上穿过绝缘层叠置有互连层。
图2B示出了在厚度方向中穿过板22形成的安装孔60和62。通过在形成以上提到的电容器30和高频信号使用的同轴电缆部分40的部分处钻孔形成安装孔60和62。形成安装孔60和62,具有的内部直径尺寸与要安装到板22的电容器30和同轴电缆部分40的外部直径尺寸匹配。
图2C示出了电容器30和同轴电缆部分40安装到板22中形成的安装孔60和62中的状态。要将电容器30安装到安装孔60,将预先形成的圆柱形的电容器电缆插入到安装孔60内。
图3A为电容器电缆30a的透视图。电容器电缆30a由以上提到的导线32、高介电常数材料34、以及形成长同轴电缆形的导体包皮36组成。通过将切成预定长度的电容器电缆30a按压到板22的安装孔60内安装电容器30。
通过将电容器30插入到安装孔60内,导体包皮36接触在安装孔60的内壁露出的互连图形47,由此互连图形47和导体包皮36电连接。
注意作为将电容器30安装到安装孔60的方法,除使用图3A所示的电容器电缆30a的方法之外,还可以使用图3B所示的电容器电缆30b的方法。图3B所示的电容器电缆30b没有图3A所示电容器电缆30a的导体包皮36。
当使用图3B所示的电容器电缆30b将电容器30安装到板22时,首先在板22中形成安装孔60,然后镀安装孔60的内壁在安装孔60的内壁形成导体层,接着将图3B所示的电容器电缆30b按压在安装孔60中。此时,导体层变成地电位,提供在安装孔60内壁的导体层的功能与图3A所示用于形成电容器30的电容器电缆30a的导体包皮36的功能相同。
用作板22的信号线的同轴电缆部分40的安装方法与将电容器30安装在板22的方法类似。即,通过按与图3A或3B所示电容器电缆30a或30b相同的方式形成的同轴电缆按压到提供在板22中的安装孔62内,安装图2C所示的同轴电缆部分40。形成的同轴电缆可以带有低介电常数材料42外表面的导体包皮,或不带有导体包皮。当低介电常数材料42外表面不形成导体包皮时,按上面介绍的相同方式镀安装孔62的内壁形成导电层就足够了。
图2D示出了在板22上形成电容器30和同轴电缆部分40之后在板22表面上形成互连图形的状态。通过电镀等在板22的上表面和下表面上形成导体层,然后腐蚀导体层形成预定图形得到互连图形。参考数字52为与外部连接端连接的焊盘,而参考数字54为连接半导体芯片10的突点的焊盘。
以此方式,可以得到安装有在厚度方向中穿过板22的电容器30的半导体封装。如上所述,本发明的半导体封装具有形成电源线作为电容器30一部分的导线32,并且导线32直接连接到连接端10a,电源线的长度最短,由此实现了抑制电源电压波动和减少电感,形成的封装具有极好的高频特性。此外,对于传输高频信号的信号线,通过与特性阻抗匹配,可以改善高频特性。由此,可以得到高频特性优越的半导体封装。
根据本发明的半导体封装及其制造方法,可以容易地将电容器安装到板,由此抑制了电源电压的波动,并且可以使连接电容器和连接端的布线长度最短,以降低电感。因此,可以提供高频特性极优越的半导体封装。
虽然参考为了示例选择的特定实施例介绍了本发明,显然本领域的技术人员可以不脱离本发明的基本概念和范围进行多种修改。

Claims (4)

1.一种半导体封装,安装有电容器用于抑制电源电压波动,其中在厚度方向中穿过板的安装孔中,电容器由以下组成:一端连接到半导体芯片连接端的导线、以预定厚度覆盖导线的高介电常数材料、以及设置在高介电常数材料外周边和安装孔内壁之间的导体层,具有导线作为它的中心的同轴结构。
2.根据权利要求1所述的半导体封装,其中在厚度方向中穿过所述板的安装孔中,提供在所述板上的至少一个信号线由中心的信号线、低介电常数材料、以及导体层组成,形成匹配阻抗的同轴电缆部分。
3.一种半导体封装的制造方法,半导体封装安装有电容器用于抑制电源电压波动,包括:
提供在厚度方向中穿过板的安装孔,以及
将电容器电缆按压到所述安装孔内,由此将电容器安装到所述板,电容器电缆由中心的导线、以预定厚度同轴地覆盖导线的高介电常数材料、以及覆盖高介电常数材料外周边的导体包皮组成。
4.一种半导体封装的制造方法,半导体封装安装有电容器用于抑制电源电压波动,包括:
提供在厚度方向中穿过板的安装孔,
在安装孔的内壁上形成导体层,以及
将电容器电缆压入所述形成有所述导体层的安装孔内,由此将电容器安装到所述板,电容器电缆由中心的导线、以预定厚度同轴地覆盖导线的高介电常数材料组成。
CNB021464456A 2001-11-07 2002-11-07 半导体封装及其制造方法 Expired - Fee Related CN1306601C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP341643/2001 2001-11-07
JP2001341643A JP3495727B2 (ja) 2001-11-07 2001-11-07 半導体パッケージおよびその製造方法

Publications (2)

Publication Number Publication Date
CN1417856A true CN1417856A (zh) 2003-05-14
CN1306601C CN1306601C (zh) 2007-03-21

Family

ID=19155631

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021464456A Expired - Fee Related CN1306601C (zh) 2001-11-07 2002-11-07 半导体封装及其制造方法

Country Status (5)

Country Link
US (2) US20030085471A1 (zh)
JP (1) JP3495727B2 (zh)
KR (1) KR20030038445A (zh)
CN (1) CN1306601C (zh)
TW (1) TW200300282A (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661920B (zh) * 2008-08-26 2011-06-29 欣兴电子股份有限公司 芯片封装载板及其制造方法
CN102598263A (zh) * 2009-11-09 2012-07-18 国际商业机器公司 采用导电贯穿基板通路的集成去耦电容器
CN102970817A (zh) * 2011-08-30 2013-03-13 思达科技股份有限公司 电子电路板
CN104604345A (zh) * 2012-08-31 2015-05-06 索尼公司 布线板及布线板的制造方法
CN106912160A (zh) * 2017-03-14 2017-06-30 上海摩软通讯技术有限公司 一种pcb板及其制作方法
CN109841430A (zh) * 2019-03-22 2019-06-04 杭州灵通电子有限公司 一种用于大尺寸多层瓷介电容器的封端装置及封端工艺
CN112956177A (zh) * 2018-10-26 2021-06-11 三星电子株式会社 包括基板的基板连接构件以及包括该基板连接构件的电子设备,该基板具有围绕其中形成直通导线的区域的开口部分和形成在开口部分的侧表面上的导电构件
CN113194598A (zh) * 2018-03-15 2021-07-30 华为技术有限公司 连接板、电路板组件及电子设备

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4005451B2 (ja) * 2002-08-29 2007-11-07 富士通株式会社 多層基板及び半導体装置
US7767876B2 (en) * 2003-10-30 2010-08-03 The Procter & Gamble Company Disposable absorbent article having a visibly highlighted wetness sensation member
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
KR100858075B1 (ko) * 2004-07-06 2008-09-11 도쿄엘렉트론가부시키가이샤 인터포저
KR100856450B1 (ko) * 2004-07-06 2008-09-04 도쿄엘렉트론가부시키가이샤 관통 기판의 제조 방법
JP4445351B2 (ja) * 2004-08-31 2010-04-07 株式会社東芝 半導体モジュール
SG135065A1 (en) * 2006-02-20 2007-09-28 Micron Technology Inc Conductive vias having two or more elements for providing communication between traces in different substrate planes, semiconductor device assemblies including such vias, and accompanying methods
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
US7534722B2 (en) * 2005-06-14 2009-05-19 John Trezza Back-to-front via process
US7687400B2 (en) * 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7521806B2 (en) * 2005-06-14 2009-04-21 John Trezza Chip spanning connection
US7851348B2 (en) * 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7786592B2 (en) * 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US7989958B2 (en) * 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7560813B2 (en) * 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7701052B2 (en) * 2005-10-21 2010-04-20 E. I. Du Pont De Nemours And Company Power core devices
US7404250B2 (en) * 2005-12-02 2008-07-29 Cisco Technology, Inc. Method for fabricating a printed circuit board having a coaxial via
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
JP2008028188A (ja) * 2006-07-21 2008-02-07 Sharp Corp プリント配線板、プリント配線板の製造方法、及び電子機器
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7871927B2 (en) * 2006-10-17 2011-01-18 Cufer Asset Ltd. L.L.C. Wafer via formation
US7570493B2 (en) * 2006-11-16 2009-08-04 Sony Ericsson Mobile Communications Printed circuit board with embedded circuit component
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US7748116B2 (en) * 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US7850060B2 (en) * 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US7960210B2 (en) * 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
KR20090096174A (ko) * 2008-03-07 2009-09-10 주식회사 하이닉스반도체 회로 기판 및 이를 이용한 반도체 패키지
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US8227706B2 (en) * 2008-12-31 2012-07-24 Intel Corporation Coaxial plated through holes (PTH) for robust electrical performance
US20100327433A1 (en) * 2009-06-25 2010-12-30 Qualcomm Incorporated High Density MIM Capacitor Embedded in a Substrate
TWI370532B (en) * 2009-11-12 2012-08-11 Ind Tech Res Inst Chip package structure and method for fabricating the same
FR2953069B1 (fr) * 2009-11-24 2012-03-09 Eads Europ Aeronautic Defence Dispositif de protection contre la foudre d'un recepteur d'antenne et avion le comportant
US8519515B2 (en) * 2011-04-13 2013-08-27 United Microlectronics Corp. TSV structure and method for forming the same
CN103563072B (zh) * 2011-05-24 2017-09-26 三菱电机株式会社 高频封装
JP5938918B2 (ja) * 2012-01-24 2016-06-22 株式会社デンソー 配線基板を有する半導体装置
US9368440B1 (en) * 2013-07-31 2016-06-14 Altera Corporation Embedded coaxial wire and method of manufacture
US9911689B2 (en) 2013-12-23 2018-03-06 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
CN106463617B (zh) * 2014-03-18 2019-08-16 日本麦可罗尼克斯股份有限公司 电池
US9275975B2 (en) 2014-03-28 2016-03-01 Intel Corporation Electronic package and method of connecting a first die to a second die to form an electronic package
US10119993B2 (en) * 2014-10-30 2018-11-06 Tongfu Microelectronics Co., Ltd. Testing probe and semiconductor testing fixture, and fabrication methods thereof
US9455189B1 (en) 2015-06-14 2016-09-27 Darryl G. Walker Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture
US9807867B2 (en) 2016-02-04 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method of manufacturing the same
JP2017204511A (ja) * 2016-05-10 2017-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
KR102509050B1 (ko) * 2018-06-26 2023-03-13 에스케이하이닉스 주식회사 전자기 밴드갭 구조를 갖는 패키지 기판 및 이를 이용한 반도체 패키지
KR20220146907A (ko) 2021-04-26 2022-11-02 삼성전기주식회사 인쇄회로기판
KR20230135849A (ko) * 2022-03-17 2023-09-26 삼성전자주식회사 캐패시터 와이어가 매립된 배선 기판
WO2024204479A1 (ja) * 2023-03-30 2024-10-03 京セラ株式会社 構造体、量子プロセッサ、量子コンピュータ、及び構造体の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891375B2 (ja) * 1990-02-27 1999-05-17 新光電気工業株式会社 高速電子部品用セラミック基板とその製造方法
JPH05167258A (ja) * 1991-12-12 1993-07-02 Nec Corp 多層配線基板
JPH10163A (ja) 1996-06-15 1998-01-06 Chubu Corp:Kk 焼き肉ロースタの使用方法
US6072690A (en) * 1998-01-15 2000-06-06 International Business Machines Corporation High k dielectric capacitor with low k sheathed signal vias
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
JP4390368B2 (ja) 2000-06-08 2009-12-24 新光電気工業株式会社 配線基板の製造方法
TW525417B (en) * 2000-08-11 2003-03-21 Ind Tech Res Inst Composite through hole structure
US6605551B2 (en) * 2000-12-08 2003-08-12 Intel Corporation Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661920B (zh) * 2008-08-26 2011-06-29 欣兴电子股份有限公司 芯片封装载板及其制造方法
CN102598263A (zh) * 2009-11-09 2012-07-18 国际商业机器公司 采用导电贯穿基板通路的集成去耦电容器
CN102598263B (zh) * 2009-11-09 2015-03-11 国际商业机器公司 采用导电贯穿基板通路的集成去耦电容器
CN102970817A (zh) * 2011-08-30 2013-03-13 思达科技股份有限公司 电子电路板
CN104604345A (zh) * 2012-08-31 2015-05-06 索尼公司 布线板及布线板的制造方法
CN106912160A (zh) * 2017-03-14 2017-06-30 上海摩软通讯技术有限公司 一种pcb板及其制作方法
CN113194598A (zh) * 2018-03-15 2021-07-30 华为技术有限公司 连接板、电路板组件及电子设备
US11706871B2 (en) 2018-03-15 2023-07-18 Huawei Technologies Co., Ltd. Connection plate, circuit board assembly, and electronic device
CN112956177A (zh) * 2018-10-26 2021-06-11 三星电子株式会社 包括基板的基板连接构件以及包括该基板连接构件的电子设备,该基板具有围绕其中形成直通导线的区域的开口部分和形成在开口部分的侧表面上的导电构件
US11690179B2 (en) 2018-10-26 2023-06-27 Samsung Electronics Co., Ltd. Substrate connection member comprising substrate having opening part, which encompasses region in which through wire is formed, and conductive member formed on side surface of opening part, and electronic device comprising same
CN112956177B (zh) * 2018-10-26 2023-09-29 三星电子株式会社 基板连接构件以及包括该基板连接构件的电子设备
CN109841430A (zh) * 2019-03-22 2019-06-04 杭州灵通电子有限公司 一种用于大尺寸多层瓷介电容器的封端装置及封端工艺

Also Published As

Publication number Publication date
JP3495727B2 (ja) 2004-02-09
US20030085471A1 (en) 2003-05-08
TW200300282A (en) 2003-05-16
US7033934B2 (en) 2006-04-25
CN1306601C (zh) 2007-03-21
JP2003142627A (ja) 2003-05-16
KR20030038445A (ko) 2003-05-16
US20040238949A1 (en) 2004-12-02

Similar Documents

Publication Publication Date Title
CN1306601C (zh) 半导体封装及其制造方法
US6446317B1 (en) Hybrid capacitor and method of fabrication therefor
JP3995596B2 (ja) 多段アレイキャパシター及びその製造方法
US7411278B2 (en) Package device with electromagnetic interference shield
CN1185715C (zh) 一种集成电路及其制造方法
US6700076B2 (en) Multi-layer interconnect module and method of interconnection
US9095067B2 (en) Apparatus and method for vertically-structured passive components
US20110018119A1 (en) Semiconductor packages including heat slugs
JPH0765883A (ja) 電気コネクタ
EP1104026B1 (en) Ground plane for a semiconductor chip
KR100663265B1 (ko) 다층 기판 및 그 제조 방법
CN1273457A (zh) 用于电子部件的封装
CN1133230C (zh) 高频电路装置及其使用的电子元件
CN1045140C (zh) 高频阻波电路
CN1842910A (zh) 复合电子部件
WO2012106221A1 (en) Ic device socket
JP2004531049A (ja) 拡張表面ランドを有するキャパシター及びその製造方法
CN101044801A (zh) 具有降低的电容耦合的电路板组件
US6674645B2 (en) High frequency signal switching unit
US7671704B2 (en) LC resonant circuit
EP3712932A1 (en) Package and semiconductor device
CN1286238C (zh) 通信线路电涌保护系统
CN1433105A (zh) 天线装置
US6509633B1 (en) IC package capable of accommodating discrete devices
JP4460855B2 (ja) フィルタ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070321

Termination date: 20201107

CF01 Termination of patent right due to non-payment of annual fee