JP3995596B2 - 多段アレイキャパシター及びその製造方法 - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims abstract description 275
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000004020 conductor Substances 0.000 claims abstract description 41
- 239000003989 dielectric material Substances 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 52
- 239000000919 ceramic Substances 0.000 claims description 31
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 239000003985 ceramic capacitor Substances 0.000 claims description 2
- 230000007704 transition Effects 0.000 description 13
- 230000008569 process Effects 0.000 description 12
- 239000010409 thin film Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000005553 drilling Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
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- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000002991 molded plastic Substances 0.000 description 2
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- 239000004033 plastic Substances 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
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- 239000000758 substrate Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
Claims (30)
- キャパシターであって、
パターン形成された導電性材料の多数の第1層が誘電性材料の層で分離された第1の容量段と、
キャパシターの上面から多数の第1層を貫通し、一部が多数の第1層のうちの1つおきの層と電気的に接触し、他の部分が多数の第1層のうちの残りの層と電気的に接触する第1の数の第1のキャパシタービアと、
第1の容量段に電気的に接続され、パターン形成された導電性材料の多数の第2層が誘電性材料の層で分離された第2の容量段と、
多数の第1層及び多数の第2層を貫通し、一部が多数の第2層のうちの1つおきの層と電気的に接触し、他の部分が多数の第2層のうちの残りの層と電気的に接触する第2の数の第2のキャパシタービアとより成り、
第1のキャパシタービアは多数の第2層を貫通しないキャパシター。 - 第2の容量段は第1段の容量段の実質的に下方に位置し、第2のキャパシタービアの一部は多数の第1層のうちの1つおきの層と電気的に接触し、第2のキャパシタービアの他の部分は多数の第1層のうちの残りの層と電気的に接触する請求項1のキャパシター。
- 第1のキャパシタービアの第1の数は第2キャパシタービアの第2の数より大きい請求項2のキャパシター。
- 第2のキャパシタービアはキャパシターの底面へ延びるため、第2キャパシタービアへ底面で電気的に接続できる請求項2のキャパシター。
- 第1の容量段と第2の容量段との間に電気的に接続され、パターン形成された導電性材料の多数の別の層を含む少なくとも1つの別の容量段と、
多数の別の層を貫通し、一部が多数の別の層のうちの1つおきの層と電気的に接触し、他の部分が多数の別の層のうちの残りの層と電気的に接触する別のキャパシタービアとをさらに有する請求項1のキャパシター。 - キャパシターは個別デバイスである請求項1のキャパシター。
- 第1の容量段はキャパシターの中央領域に位置し、第2の容量段はキャパシターの周辺領域に位置する請求項6のキャパシター。
- キャパシターはセラミックキャパシターである請求項1のキャパシター。
- 第1の容量段と第2の容量段とはハウジング内に集積化されている請求項1のキャパシター。
- 第1の容量段はハウジングの中央領域に位置し、第2の容量段はハウジングの周辺領域に位置する請求項9のキャパシター。
- ハウジングであって、
パターン形成された導電性材料の多数の第1層が誘電性材料の層により分離された第1の容量段と、
キャパシターの上面から多数の第1層を貫通し、一部が多数の第1層のうちの1つおきの層と電気的に接触し、他の部分が多数の第1層のうちの残りの層と電気的に接触する第1の数の第1のキャパシタービアと、
第1の容量段に電気的に接続され、パターン形成された導電性材料の多数の第2層が誘電性材料の層で分離された第2の容量段と、
多数の第1層及び多数の第2層を貫通し、一部が多数の第2層のうちの1つおきの層と電気的に接触し、他の部分が多数の第2層のうちの残りの層と電気的に接触する第2の数の第2キャパシタービアとより成り、
第1のキャパシタービアは多数の第2層を貫通しないハウジング。 - 第1の容量段はハウジングの中央領域に位置し、第2の容量段はハウジングの周辺領域に位置する請求項11のハウジング。
- ハウジングは集積回路パッケージであり、集積回路が中央領域上に実装可能であり、その集積回路が周辺領域には実装可能でない請求項12のハウジング。
- 第1の容量段と第2の容量段とは、パターン形成された導電性材料の1またはそれ以上の別の層を介して電気的に接続されている請求項11のハウジング。
- パターン形成された導電性材料の1またはそれ以上の別の層は、第1の容量段及び第2の容量段の実質的下方に位置する請求項14のハウジング。
- 第1の容量段と第2の容量段との間に電気的に接続され、パターン形成された導電性材料の多数の別の層が誘電性材料の層で分離された少なくとも1つの別の容量段と、
多数の別の層を貫通し、一部が多数の別の層のうちの1つおきの層と電気的に接触し、他の部分が多数の別の層のうちの残りの層と電気的に接触する別のキャパシタービアとをさらに有する請求項11のハウジング。 - 第2の容量段は第1の容量段の実質的下方に位置し、第2キャパシタービアの一部は多数の第1層のうちの1つおきの層と電気的に接触し、第2キャパシタービアの他の部分は多数の第1層のうちの残りの層と電気的に接触する請求項11のハウジング。
- 第1の容量段、第2の容量段、第1の数の第1キャパシタービア及び第2の数の第2キャパシタービアは、ハウジング内に埋込まれた個別キャパシターに含まれる請求項17のハウジング。
- 第1の容量段、第2の容量段、第1の数の第1キャパシタービア及び第2の数の第2キャパシタービアは、ハウジング上に実装される個別キャパシターに含まれる請求項17のハウジング。
- 第1のキャパシタービアの第1のピッチは第2のキャパシタービアの第2のピッチより小さく、パワーとアースに対してピッチ変換を行う請求項17のハウジング。
- ハウジングは、集積回路パッケージ、インターポーザー、ソケット及びプリント回路板より成る群のうちの1つである請求項11のハウジング。
- ハウジングはセラミックハウジングである請求項11のハウジング。
- ハウジングは有機ハウジングである請求項11のハウジング。
- キャパシターの製造方法であって、
パターン形成された導電性材料の多数の第1層が誘電性材料の層により分離された第1の容量段と、パターン形成された多数の第2層が誘電性材料の層で分離された第2の容量 段とが互いに電気的に接続された多層構造を製造し、
キャパシターの上面から多数の第1層を貫通するが、多数の第2層は貫通せず、一部が多数の第1層のうちの1つおきの層と電気的に接触し、他の部分が多数の第1層のうちの残りの層と電気的に接触する第1の数の第1のキャパシタービアを形成し、
多数の第1層及び多数の第2層を貫通し、一部が多数の第2層のうちの1つおきの層と電気的に接触し、他の部分が多数の第2層のうちの残りの層と電気的に接触する第2の数の第2のキャパシタービアを形成するステップより成るキャパシターの製造方法。 - 多層構造を製造するステップは第2の容量段を第1段の容量の実質的に下方に形成するステップより成り、第2の数の第2のキャパシタービアを形成するステップは、多数の第1層を貫通する第2のキャパシタービアを形成するステップを含み、第2のキャパシタービアの一部は多数の第1層のうちの1つおきの層と電気的に接触し、第2のキャパシタービアの他の部分は多数の第1層のうちの残りの層と電気的に接触する請求項24の方法。
- 第2のキャパシタービアを形成するステップは、第2のキャパシタービアに底面で電気的に接続できるように第2のキャパシタービアをキャパシターの底面へ延伸させるステップより成る請求項25の方法。
- 多層構造を実装するステップをさらに含む請求項25の方法。
- 多層構造を製造するステップは、第1の容量段をキャパシターの中央領域に形成し、第2の容量段をキャパシターの周辺領域に形成するステップを含む請求項24の方法。
- 多層構造を製造するステップは、多層構造をハウジングの集積化部分として製造するステップを含む請求項28の方法。
- 多層構造をハウジングの集積化部分として形成するステップは多層構造を集積回路パッケージの集積化部分として製造するステップを含み、集積回路は中央領域上に実装可能であり、その集積回路は周辺領域上には実装可能でない請求項29の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/751,612 US6532143B2 (en) | 2000-12-29 | 2000-12-29 | Multiple tier array capacitor |
PCT/US2001/044878 WO2002054421A2 (en) | 2000-12-29 | 2001-11-28 | Multiple tier array capacitor and methods of fabrication therefor |
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JP2004534376A JP2004534376A (ja) | 2004-11-11 |
JP3995596B2 true JP3995596B2 (ja) | 2007-10-24 |
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US (1) | US6532143B2 (ja) |
EP (1) | EP1384237A2 (ja) |
JP (1) | JP3995596B2 (ja) |
KR (1) | KR100550480B1 (ja) |
CN (1) | CN1316524C (ja) |
AU (1) | AU2002219953A1 (ja) |
DE (1) | DE10197124B4 (ja) |
GB (1) | GB2384912B (ja) |
MY (1) | MY128533A (ja) |
WO (1) | WO2002054421A2 (ja) |
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2000
- 2000-12-29 US US09/751,612 patent/US6532143B2/en not_active Expired - Lifetime
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2001
- 2001-11-28 JP JP2002555429A patent/JP3995596B2/ja not_active Expired - Fee Related
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- 2001-11-28 KR KR1020037008753A patent/KR100550480B1/ko not_active IP Right Cessation
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AU2002219953A1 (en) | 2002-07-16 |
EP1384237A2 (en) | 2004-01-28 |
US6532143B2 (en) | 2003-03-11 |
CN1484840A (zh) | 2004-03-24 |
WO2002054421A3 (en) | 2003-11-06 |
US20020085334A1 (en) | 2002-07-04 |
JP2004534376A (ja) | 2004-11-11 |
DE10197124B4 (de) | 2006-10-26 |
GB2384912B (en) | 2004-12-22 |
WO2002054421A2 (en) | 2002-07-11 |
GB2384912A (en) | 2003-08-06 |
GB0311850D0 (en) | 2003-06-25 |
KR100550480B1 (ko) | 2006-02-09 |
CN1316524C (zh) | 2007-05-16 |
MY128533A (en) | 2007-02-28 |
DE10197124T1 (de) | 2003-11-13 |
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