CN102598263B - 采用导电贯穿基板通路的集成去耦电容器 - Google Patents

采用导电贯穿基板通路的集成去耦电容器 Download PDF

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CN102598263B
CN102598263B CN201080050627.8A CN201080050627A CN102598263B CN 102598263 B CN102598263 B CN 102598263B CN 201080050627 A CN201080050627 A CN 201080050627A CN 102598263 B CN102598263 B CN 102598263B
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substrate
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CN102598263A (zh
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M·F·麦卡利斯特
M·J·沙皮罗
金兑洪
E·J·斯普罗吉斯
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Adeia Semiconductor Solutions LLC
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Abstract

半导体基板（10）中的电容器（180）采用导电贯穿基板通路（TSV）（80）作为内部电极，并采用柱状掺杂半导体区域作为外部电极。电容器（80）在小的区域内提供大的去耦电容，并且不影响电路密度或Si 3D结构设计。附加的导电TSV可设置在半导体基板（10）中以提供对电源的电连接以及通过其的信号传输。与具有可比的电容的传统电容器阵列相比，电容器（180）具有更低的电感系数，从而能够减小堆叠的半导体芯片的电源系统中的高频噪声。

Description

采用导电贯穿基板通路的集成去耦电容器
技术领域
本发明涉及半导体结构的领域，特别是涉及采用导电贯穿基板通路的去耦电容器及其制造方法。
背景技术
近年来，已经提出了“三维硅”（3D Si）结构，其能够接合安装在封装或系统板上的多个硅芯片和/或晶片。3D Si结构提高了集成在给定空间内的有源电路的密度。
随着单元面积的电路密度的增加，每单位面积的开关活动量也增加。这导致参考电源上产生的噪声的增加。由于噪声增加，内部器件的性能以及片外驱动器（off-chip driver）的性能由于系统设计的可用的噪声容限减小而被不利地影响。
目前，通过在有源硅器件内埋设深沟槽电容器（DTC）来控制此噪声。为了获得足够程度的去耦，需要大阵列的DTC。随着3D Si结构中电路密度、开关活动和电源分配结构的改善，需要更多的DTC来控制噪声发生。此外，由于形成多个DTC阵列，有源电路和DTC阵列之间的电感系数增加，从而要求形成附加的DTC来存储能量，该能量用于平衡反向电磁力（backelectromagnetic force）噪声。
噪声的电压Vn由下式给出：
Vn=L×（dI/dt），
其中L是电感系数，I是电流，且t是时间。随着电感系数（L）增加，或者随着电流变化（dl/dt）的速率（与电路开关速率成正比）增加，噪声Vn成正比增加。
以上考虑显示需要一种具有低电感的电容结构以控制3D Si结构内产生的或者传送到3DSi结构中的电感噪声。
发明内容
根据本发明的实施例，半导体基板中的电容器采用作为内部电极的导电贯穿基板通路（TSV）和作为外部电极的柱状掺杂半导体区域。电容器在很小的区域中提供很大的去耦电容，并且不影响电路密度或Si 3D结构设计。附加的导电TSV可提供在半导体基板中以提供其中的电源线和信号传输的电连接。该电容器与具有可比电容的传统阵列电容器相比具有更低的电感系数，因此能减小堆叠的半导体芯片的电源系统上的高频噪声。
根据本发明的一个方面，半导体结构包括：半导体芯片，其包括半导体基板；至少一个电容器，埋设在半导体基板中；以及至少一个横向绝缘的导电贯穿基板连接结构。至少一个电容器的每一个都包括：内部电极，包括导电贯穿基板通路（TSV）结构；节点电介质，横向接触且横向包封内部电极；以及外部电极，横向接触且横向包封节点电介质的一部分。
根据本发明的另一个方面，半导体结构包括设置在半导体基板中的电容器和设置在半导体基板上的接触结构。该电容器包括内部电极、节点电介质和外部电极。内部电极包括导电贯穿基板通路（TSV）结构，其连续延伸至少从半导体基板的上表面到半导体基板的下表面。节点电介质横向接触且横向包封内部电极，并且连续延伸从上表面到下表面。外部电极横向接触且横向包封节点电介质的一部分。接触结构导电连接到外部电极。
根据本发明的再一个方面，提供形成半导体结构的方法。该方法包括在半导体基板中形成电容器且横向绝缘的导电贯穿基板连接结构。横向绝缘的导电贯穿基板连接结构通过在半导体基板中形成的第一贯穿基板空腔周围形成电介质管状结构而形成；并且用导电材料填充电介质管状结构内的空腔。电容器通过掺杂半导体基板的一部分形成外部电极而形成在第二贯穿基板空腔周围；在第二贯穿基板空腔的表面上形成节点电介质；并且通过用导电材料填充第二通过基板空腔而形成内部电极。
根据本发明的又一个方面，提供形成半导体结构的方法。该方法包括提供半导体芯片以及采用焊料球阵列电连接半导体芯片到安装结构。半导体芯片包括半导体基板；至少一个电容器，埋设在半导体基板中；以及至少一个横向绝缘的导电贯穿基板连接结构。至少一个电容器具有包括导电贯穿基板通路（TSV）结构的内部电极。
附图说明
图1-18是根据本发明第一实施例的第一示范性结构通过各种工艺步骤的顺序垂直截面图。
图19是根据本发明第二实施例的第二示范性结构的垂直截面图。
图20是根据本发明第三实施例的第三示范性结构的垂直截面图。
图21是示出模拟结果的曲线图，其示出了在根据本发明实施例的示范性结构提供的高频下的噪声减小。
具体实施方式
如上所述，本发明涉及半导体结构，具体涉及采用导电贯穿基板通路的去耦电容器及其制造方法，现在参考附图进行详细描述。在全部附图中，相同的参考标号或字母用于表示类似或等价的元件。附图不必按比例绘制。
如本文所用，“导电贯穿基板通路（TSV）结构”是延伸通过基板（即，至少从基板的顶表面到基板的底表面）的导电结构。
如本文所用，“横向绝缘的导电贯穿基板连接结构”是导电TSV结构与横向围绕导电TSV结构且电隔离导电TSV结构与基板的另一个结构的组件。
如本文所用，“安装结构”是半导体芯片通过制作电连接可安装至的任何结构。安装结构可为封装基板、插入结构或另一半导体芯片。
如本文所用，如果第一元件和第二元件之间在“横向方向”上存在直接物理接触，则第一元件“横向接触”第二元件，“横向方向”是垂直于基板的顶表面或底表面的任何方向。
如本文所用，如果第一元件的内边缘位于第二元件的外边缘上或其外侧，则第一元件“横向围绕”第二元件。
如本文所用，如果第二元件的所有外表面位于第一元件的内表面内，则第一元件“包封”第二元件。
如本文所用，如果两个元件之间存在允许电流导通的导电路径，则两个元件彼此“导电连接”。
参见图1，根据本发明第一实施例的第一示范性结构包括具有半导体材料的半导体基板10。半导体基板10的半导体材料可选自但不限于硅、锗、硅-锗合金、硅碳合金、硅-锗-碳合金、砷化镓、砷化铟、磷化铟、III-V化合物半导体材料、II-VI化合物半导体材料、有机半导体材料及其它化合物半导体材料。优选地，半导体基板10的半导体材料是单晶材料。例如，半导体基板10可为单晶硅层。半导体基板10可掺杂有第一导电类型的掺杂剂，第一导电类型可为p型或n型。半导体基板10的掺杂剂浓度可为1.0×1014/cm3至1.0×1017/cm3。
掺杂阱区域12通过将第二导电类型的掺杂剂注入通过半导体基板10的顶表面的一部分而形成在半导体基板10中。第二导电类型与第一导电类型相反。如果第一导电类型为p型，则第二导电类型为n型，反之亦然。掺杂阱区域12的掺杂剂浓度可为1.0×1018/cm3至1.0×1021/cm3以增加掺杂阱区域12的导电性。
参见图2，衬垫电介质层16和第一掩模层18形成在半导体基板10的顶表面上。衬垫电介质层16可形成或可不形成在半导体基板10的后侧上。衬垫电介质层16包括诸如氮化硅的电介质材料。第一掩模层18可由光致抗蚀剂或诸如氧化硅或氮化硅的电介质材料构成。
参见图3，第一掩模层18被光刻图案化，并且第一掩模层18中的图案通过采用第一掩模层18作为蚀刻掩模的各向异性蚀刻而转移至半导体基板10。第一贯穿基板空腔47形成在半导体基板10中。第一贯穿基板空腔47的横向尺寸，例如，直径、长轴、短轴、边长，可为1微米至100微米，且典型地为3微米至30微米，尽管也可采用更小或更大的横向尺寸。
参见图4，第一掩模层18可对半导体基板10选择性去除。例如，通过将第一贯穿基板空腔47的侧壁上半导体基板10的暴露部分转变成电介质材料，电介质管状结构20形成在第一贯穿基板空腔47周围。例如，半导体基板的暴露部分可通过热氧化转变成电介质氧化物。电介质管状结构20可包括半导体基板10的半导体材料的氧化物。例如，如果半导体基板10包括硅，则电介质管状结构20可包括氧化硅。衬垫电介质层16防止半导体基板10的其它部分转变成电介质材料。电介质管状结构20从半导体基板10的顶表面延伸到半导体基板10的底表面。电介质管状结构20的水平截面区域包括对应于第一贯穿基板空腔47的孔。电介质管状结构20的厚度，如在电介质管状结构20的内边缘与电介质管状结构20的外部周边之间横向测量的，可为100nm至1微米，尽管也可采用更小或更大的厚度。
参见图5，衬垫电介质层16可被去除。可选地，电介质衬垫30设置在电介质管状结构20的内部侧壁上。电介质衬垫30例如可包括氧化硅层和氮化硅层的堆叠。
参见图6，以第一可移除材料填充第一贯穿基板空腔47以形成第一可移除材料层49L。第一可移除材料层49L延伸穿过半导体基板10并且覆盖半导体基板10的两侧，因此包封半导体基板10。第一可移除材料例如可为诸如多晶硅的含多晶硅的材料或诸如非晶硅的含非晶硅的材料。
参见图7，从半导体基板10的前侧和后侧去除第一可移除材料层49L，例如通过回蚀刻工艺或化学机械抛光（CMP）。此外，第一可移除材料层49L的一部分凹陷在半导体基板10的顶表面下方凹陷深度rd，凹陷深度rd可为200nm至2,000nm，尽管也可采用更小和更大的凹陷深度rd。第一可移除材料层49L的剩余部分构成第一可移除材料部分49。
参见图8，通过用电介质材料填充第一可移除材料部分49上方的空腔并且去除电介质衬垫30的顶表面上方的多余电介质材料形成电介质帽部分50。可选地，氮化硅帽层（未示出）可沉积在电介质帽部分50的顶表面上以及电介质衬垫30位于半导体基板10的前侧上的部分上。
参见图9，第二掩模层51形成在半导体基板10的顶表面上方。第二掩模层51可由光致抗蚀剂或诸如氧化硅或氮化硅的电介质材料构成。第二掩模层51被光刻图案化以在没有放置可移除材料部分49和电介质管状结构20的区域中形成开口。在掺杂阱区域12上方或靠近掺杂阱区域12形成第二掩模层51中的开口。第二掩模层51中的图案通过采用第二掩模层51作为蚀刻掩模的各向异性蚀刻转移至半导体基板10。第二贯穿基板空腔67形成在半导体基板10中。第二贯穿基板空腔67的横向尺寸（例如，直径、长轴、短轴、边长）可为1微米至100微米，且典型地为3微米至30微米，尽管也可采用更小和更大的横向尺寸。
参见图10，掺杂材料层52沉积在第一示范性结构的暴露表面上，第一示范性结构的暴露表面包括第二贯穿基板空腔67的侧壁。掺杂材料层52包括第二导电类型的掺杂剂。掺杂材料层52例如可为砷硅酸盐玻璃（arsenosilicate，-ASG）层。掺杂材料层52的厚度小于第二贯穿基板空腔67的最小横向尺寸的一半以防止堵塞第二贯穿基板空腔67。可选地，电介质盖帽层（未示出）可沉积在掺杂材料层52上方以防止在随后的驱入退火（drive-in anneal）期间的掺杂剂损耗。
参见图11，执行驱入退火以诱导第二导电类型的掺杂剂外扩散进入半导体基板10的围绕第二贯穿基板空腔67的区域。通过掺杂半导体基板10在在第二贯穿基板空腔67周围的一部分形成外部电极。具体地，通过将管状区域（即管的形状的区域）转变成具有第二导电类型掺杂的掺杂半导体区域而形成外部电极60。例如，诸如砷硅酸盐玻璃层的含掺杂剂材料层可沉积在第二贯穿基板空腔67的侧壁上，并且掺杂剂可通过驱入退火被驱入半导体基板10中。外部电极60是包括掺杂半导体材料的掺杂管状部分，即，具有管的形状。外部电极60的外边缘与外部电极的内边缘（即与掺杂材料层52的边界）之间的横向距离可为150nm至1,000nm，尽管也可采用更小和更大的距离。外部电极60的掺杂剂浓度可为1.0×l018/cm3至1.0×1020/cm3，尽管也可采用更小和更大的掺杂剂浓度。掺杂材料层52随后被去除。在可替换的实施例中，可通过等离子体掺杂而不采用掺杂材料层52形成外部电极60。
参见图12，节点电介质70形成在第一示范性结构所有暴露表面上，该暴露表面包括外部电极60的内部侧壁和电介质衬垫30的暴露表面，外部电极60的内部侧壁为第二贯穿基板空腔67的表面。节点电介质70直接形成在掺杂管状部分的侧壁上，而可移除材料存在于半导体基板中。节点电介质70的厚度可为3nm至30nm，尽管也可采用更小或更大的厚度。
参见图13，以第二可移除材料填充第二贯穿基板空腔67以形成第二可移除材料层77L。第二可移除材料层77L延伸穿过半导体基板10并且覆盖半导体基板10的两侧，从而包封半导体基板10。第二可移除材料例如可为诸如多晶硅的含多晶硅的材料或诸如非晶硅的含非晶硅的材料。
参见图14，从半导体基板10的前侧和后侧去除第二可移除材料层77L，例如通过回蚀刻工艺或化学机械抛光（CMP）。第二可移除材料层77L的剩余部分构成第二可移除材料部分77。第二可移除材料部分77的顶表面可与半导体基板20的前侧上的节点电介质70的顶表面共平面。
硬掩模层72形成在半导体基板20的一侧上，其优选为电介质帽部分50位于其上的半导体基板的前侧。硬掩模层72包括电介质材料，诸如氧化硅、氮化硅、掺杂硅酸盐玻璃或其组合。硬掩模层72的厚度可为500nm至5,000nm，并且典型地为1,000nm至3,000nm，尽管也可采用更小或更大的厚度。
参见图15，硬掩模层72被光刻图案化以形成第二可移除材料部分77上方的开口和第一可移除材料部分49上方的开口。电介质帽部分50被去除以暴露第一可移除材料部分49的上表面。第二可移除材料部分77的上部可在去除电介质帽部分50期间被去除。
参见图16，第一可移除材料部分49的第一电介质材料和第二电介质材料部分77的第二电介质材料通过采用硬掩模层72作为蚀刻掩模的蚀刻去除。去除第一可移除材料部分49形成空腔，该空腔在体积上对应于前面的工艺步骤中的第一贯穿基板空腔47。此空腔这里称为再形成的第一贯穿基板空腔79，即第二次形成的第一贯穿基板空腔。同样，去除第二可移除材料部分77形成空腔，该空腔在体积上对应于前面的工艺步骤中的第二贯穿基板空腔67。此空腔这里称为再形成的第二贯穿基板空腔78，即第二次形成的第二贯穿基板空腔。再形成的第一贯穿基板空腔79形成在电介质管状结构20内。节点电介质70的表面暴露于再形成的第二贯穿基板空腔78周围，而电介质衬垫30的表面可暴露于再形成的第一贯穿基板空腔79周围。如果电介质衬垫30不存在，则电介质管状结构20的内表面可暴露于再形成的第一贯穿基板空腔79中。
参见图17，以导电材料填充再形成的第一贯穿基板空腔79和再形成的第二贯穿基板空腔78以分别形成第一导电贯穿基板通路（TSV）结构80和第二导电TSV结构82。第一导电TSV结构80和第二导电TSV结构82的导电材料可包括掺杂半导体材料、金属材料或其组合。第一导电TSV结构80和第二导电TSV结构82的导电材料可包括但不限于掺杂的多晶硅、掺杂的含硅合金、Cu、W、Ta、Ti、WN、TaN、TiN或其组合。导电材料例如可通过电镀、无电镀覆、物理气相沉积（PVD）、化学气相沉积（CVD）或其组合而沉积。
在沉积导电材料之后，通过采用回蚀刻工艺、化学机械抛光或其组合的平坦化，从半导体基板10的顶侧和底侧去除多余的导电材料。第一导电TSV结构80和第二导电TSV结构82的顶表面与硬掩模层72的顶表面共平面。导电TSV结构80和第二导电TSV结构82的底表面与第一示范性结构的其余部分的底表面共面。第一示范性结构的其余部分的底表面例如可为节点电介质70的暴露表面（如果节点电介质70的底部部分在平坦化后保留）或者第一示范性结构的底部的任何其它暴露的表面。第一导电TSV结构80和第二导电TSV结构82通过采用相同的沉积工艺和相同的平坦化工艺而同时形成。
参见图18，形成穿过硬掩模层72、节点电介质70和电介质衬垫30的沟槽并且用诸如掺杂半导体材料或金属材料的导电材料填充该沟槽而形成接触结构90。接触结构90通过掺杂阱区域12导电连接到外部电极60。第一导电TSV结构80、节点电介质70和外部电极60共同构成电容器180，其中第一导电TSV结构80是内部电极。第二导电TSV结构82、电介质衬垫接触第二导电TSV结构82的部分以及电介质管状结构20共同构成横向绝缘的导电贯穿基板连接结构182。第一导电TSV结构80的端表面、第二导电TSV结构82的端表面以及接触结构90的端表面可与硬掩模层72的暴露表面共平面。
第一示范性结构可并入半导体芯片中。例如，电容器180的多个示例和横向绝缘的导电贯穿基板连接结构182的多个示例可埋入半导体芯片的相同半导体基板10中。半导体芯片可包括或可不包括其它半导体器件，例如，场效晶体管、双极晶体管、闸流晶体管和二极管。
每个电容器180可包括内部电极、节点电介质70和外部电极60，内部电极包括第一导电贯穿基板通路（TSV）结构80。内部电极至少从半导体基板10的上表面到半导体基板10的下表面连续延伸。节点电介质70横向接触且横向围绕内部电极。节点电介质70从上表面到下表面连续延伸。外部电极60横向接触且横向围绕节点电介质70的一部分。外部电极60包括掺杂半导体材料。
横向绝缘的导电贯穿基板连接结构182包括位于半导体基板10中的第二导电TSV结构82和横向围绕第二导电TSV结构82且埋入半导体基板10中的电介质管状结构20。横向绝缘的导电贯穿基板连接结构182可包括电介质衬垫30的一部分。
参见图19，根据本发明第二实施例的第二示范性结构包括封装基板200、多个第一半导体芯片100、多个第二半导体芯片300、第一焊料球阵列199以及第二焊料球阵列299，第一焊料球阵列199电连接第一半导体芯片100的每一个到封装基板200，第二焊料球阵列299电连接第二半导体芯片300的每一个到第一半导体芯片100。第一半导体芯片100的每一个都包括至少一个电容器180和至少一个横向绝缘的导电贯穿基板连接结构182。第一半导体芯片100可包括或可不包括附加半导体器件，例如，场效晶体管、双极晶体管、闸流晶体管和二极管。第二半导体芯片300可包括任何类型的半导体器件。
电容器180可用作在电源系统中减小噪声的去耦电容器，该电源系统对第二半导体芯片300中的器件提供电源，并且如果存在，对第一半导体芯片100中的器件提供电源。每个电容器180可提供1pF至10nF数量级的电容，这相当于40-400000个典型沟槽电容器的电容。此外，与提供可比的总电容的沟槽电容器阵列相比，电容器180提供更低的电感系数。因此，尤其在高频操作期间，电容器180减小了电源系统中的噪声。
参见图20，根据本发明第三实施例的第三示范性结构包括封装基板200、插入结构400、多个第一半导体芯片100和多个第二半导体芯片300。第一焊料球阵列199电连接第一半导体芯片100的每一个到插入结构400。第二焊料球阵列299电连接第二半导体芯片300的每一个到第一半导体芯片100。第三焊料球阵列399连接插入结构400到封装基板200。
插入结构400可包括插入结构基板层410、下电介质材料层420和上电介质材料层430。插入结构基板层410包括以竖线示意性示出的多个贯穿基板通路结构。多个贯穿基板通路结构包括多个电容器180（见图18）和横向绝缘的导电贯穿基板连接结构182（见图18）。下电介质材料层420和上电介质材料层430可包括金属线，金属线在下电介质材料层420或上电介质材料层430内提供电布线。
通常，包括至少一个电容器180和至少一个横向绝缘的导电贯穿基板连接结构182的半导体芯片可被安装一安装结构，安装结构可为半导体芯片以电连接可安装到其上的任何结构。安装结构可为但不限于封装基板200、插入结构400、插入结构400与封装基板200的组件或诸如第二半导体芯片300的另一半导体芯片。
参见图21，曲线图示出了根据本发明实施例的示范性结构提供的高频下噪声减小的模拟结果。水平轴表示电源系统中噪声分量的频率，并且竖直轴表示包括根据本发明实施例的电容器180（见图18）或者包括根据现有技术的沟槽电容器阵列的去耦系统的等效阻抗。电源系统中的电噪声与等效阻抗成正比。标有“TSV w/582pF”的曲线表示具有582pF电容且根据本发明实施例构造的（例如如图18所示的）电容器180的等效阻抗。标有“DTC w/582pF”、“2nF”和“4nF”的曲线分别表示具有582pF、2nF和4nF总电容的沟槽电容器阵列的等效阻抗。
在0.1GHz下的频率范围，电源系统中的电压噪声由去耦电容器系统的总电容限制。然而，在1GHz之上，采用任何沟槽电容器阵列的去耦电容器系统中的电压噪声随着与去耦电容器系统的总电容无关的收敛曲线（converging curve）的频率而增加，这是因为去耦电容器系统的电感占优势。采用本发明实施例的电容器180的去耦电容器系统在1.2GHz以上的频率（除了4GHz和4.5GHz之间的小频率范围之外）提供较低的电压噪声，这是因为电容器180具有低的电感系数。因此，采用本发明实施例的电容器180的去耦电容器系统在噪声减小上提供优越的性能，而占据较小的器件区域。在第二或第三示范性结构中，如果第一半导体芯片100不包括半导体器件，则电容器180可不需要第三半导体芯片300中的任何区域而形成。在第三示范性结构中，与具有可比总电容的沟槽电容器阵列相比，电容器180可形成在较小的区域中，因此可为包括在第一半导体芯片100中的其它半导体器件提供更大区域。
尽管本发明已经相对于其优选实施例进行了具体示例和描述，但是本领域的技术人员可理解，在不脱离本发明的精神和范围的情况下，可作出形式和细节上的前述和其它改变。因此，本发明不旨在限于所描述和所示出的精确形式，而是旨在落入所附权利要求的范围内。

Claims (8)

1.一种形成半导体结构的方法，所述方法包括在半导体基板(10)中形成电容器(180)和横向绝缘的导电贯穿基板连接结构(182)，其中
所述横向绝缘的导电贯穿基板连接结构(182)如下形成：
围绕形成于所述半导体基板(10)中的第一贯穿基板空腔(47)形成电介质管状结构(20)；
以可移除材料填充所述第一贯穿基板空腔(47)；以及
去除所述可移除材料，以在所述电介质管状结构(20)内形成所述空腔；以及
以导电材料填充所述电介质管状结构(20)内的空腔，并且其中所述电容器(180)如下形成：
通过掺杂围绕第二贯穿基板空腔(67)的所述半导体基板(10)的一部分而形成外部电极(60)；
在所述第二贯穿基板空腔(67)的表面上形成节点电介质(70)；以及
通过以所述导电材料填充所述第二贯穿基板空腔(67)而形成内部电极。
2.如权利要求1所述的方法，其中所述内部电极构成第一导电贯穿基板通路(TSV)结构(80)，第二导电TSV结构(82)形成在由所述导电材料填充的所述空腔中，并且所述第一导电TSV结构(80)和所述第二导电TSV结构(82)同时形成。
3.如权利要求2所述的方法，还包括当所述可移除材料存在于所述半导体基板(10)中时，直接在所述掺杂的围绕第二贯穿基板空腔(67)的所述半导体基板(10)的一部分上形成所述节点电介质(70)。
4.如权利要求2所述的方法，还包括：
在形成所述外部电极(60)之后用第二可移除材料填充所述第二贯穿基板空腔(67)；
在所述半导体基板(10)的一侧上形成硬掩模层(72)；以及
采用所述硬掩模层(72)作为蚀刻掩模去除所述可移除材料和所述第二可移除材料。
5.一种形成半导体结构的方法，包括：
提供半导体芯片，该半导体芯片包括：
半导体基板(10)；
至少一个电容器(180)，埋入所述半导体基板(10)中，所述至少一个电容器(180)包括内部电极，该内部电极包括导电贯穿基板通路(TSV)结构(80)；以及
至少一个横向绝缘的导电贯穿基板连接结构(182)，其中所述至少一个横向绝缘的导电贯穿基板连接结构(182)如下形成：
围绕形成于所述半导体基板(10)中的第一贯穿基板空腔(47)形成电介质管状结构(20)；
以可移除材料填充所述第一贯穿基板空腔(47)；以及
去除所述可移除材料，以在所述电介质管状结构(20)内形成所述空腔；以及
以导电材料填充所述电介质管状结构(20)内的空腔；以及采用焊料球阵列电连接所述半导体芯片到安装结构。
6.如权利要求5所述的方法，其中所述阵列当中的第一焊料球(199)电连接到所述内部电极和所述安装结构上的第一导电结构，并且所述阵列当中的第二焊料球(299)电连接到所述至少一个横向绝缘的导电贯穿基板连接结构(182)内的导电TSV结构和所述安装结构上的第二导电结构。
7.如权利要求5所述的方法，其中所述安装结构选自封装基板(200)、插入结构(400)和另一半导体芯片。
8.如权利要求5所述的方法，其中所述至少一个电容器(180)的每一个都包括节点电介质(70)和外部电极(60)，所述节点电介质(70)横向接触且横向围绕所述内部电极，所述外部电极(60)横向接触且横向围绕所述节点电介质(70)的一部分，并且所述至少一个横向绝缘的导电贯穿基板连接结构(182)的每一个都包括导电TSV结构(80)和电介质管状结构(20)。
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