JPH0394452A - 半導体集積回路用パッケージ - Google Patents

半導体集積回路用パッケージ

Info

Publication number
JPH0394452A
JPH0394452A JP1231936A JP23193689A JPH0394452A JP H0394452 A JPH0394452 A JP H0394452A JP 1231936 A JP1231936 A JP 1231936A JP 23193689 A JP23193689 A JP 23193689A JP H0394452 A JPH0394452 A JP H0394452A
Authority
JP
Japan
Prior art keywords
conductor layers
semiconductor integrated
integrated circuit
package
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1231936A
Other languages
English (en)
Inventor
Teruo Matsuba
松葉　輝生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1231936A priority Critical patent/JPH0394452A/ja
Publication of JPH0394452A publication Critical patent/JPH0394452A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路用パッケージに関する． 〔従来の技術〕 従来、半導体集積回路用パッケージにおいては、電源線
および接地線の高周波インピーダンスをさげるためパッ
ケージ内にパイバスコンデンサを収容するための場所を
設ける、あるいは、パツケージ上にバイパスコンデンサ
接続用電極を配しバイパスコンデンサを付加することを
前提としていた． 〔発明が解決しようとする課題〕 上述した従来の半導体集積回路素子用パッケージは、電
源線および接地線の高周波インピーダンスをさげるため
バイパスコンデンサをハンダ付けその他の方法にて付加
する必要があり、また、たとえバイパスコンデンサを付
加したとしてもバイパスコンデンサの電極から半導体集
積回路素子の電源端子，接地端子までの配線によるイン
ピーダンスのため充分な効果が得られないという欠点が
ある． 〔課題を解決するための手段〕 本発明の半導体集積回路用パッケージは、電源端子に接
続した複数の第１の導体層と、これら第ｌの導体層と絶
縁材料を介して交互に積層し接地端子に接続した第２の
導体層とを備えている．〔実施例〕 次に、本発明について図面を参照して説明する． 第１図は本発明の一実施例の断面図である．電源端子１
に接続された導体層５はセラミックあるいはポリカーボ
ネート等で構成された絶縁層７をはさんで接地端子２に
接続された導体層６と交互に積層されている．信号端子
３および４はそれぞれ導体層８，９、ボンディングワイ
ヤ１０．１１を介して半導体集積回路素子１４に接続さ
れる．同様に、導体層５，６はそれぞれボンディングワ
イヤ１２．１３を介して半導体集積回路素子１４に接続
される． 上記の様に構成された導体層５と導体層６とは積層コン
デンサを構成し、半導体集積回路素子１４の直近に接続
されるため、外付のバイパスコンデンサに比較し電源の
高周波インピーダンスをさげる効果が著しい． 〔発明の効果〕 以上説明したように本発明は、電源端子に接続した導体
層と接地端子に接続した導体層とを絶縁層を介して交互
に積層することにより半導体集積回路用パッケージの電
源高周波インピーダンスを著しく低下できる効果がある
．
【図面の簡単な説明】 第１図は本発明の一実施例の断面図である．１・・・電
源端子、２・・・接地端子、３．４・・・信号端子、５
，６．８．９・・・導体層、７・・・絶縁層、１０，１
１，１２．１３・・・ボンディングワイヤ、１４・・・
半導体集積回路素子．

Claims (1)

    【特許請求の範囲】
  1. 電源端子に接続した複数の第１の導体層と、これら第１
    の導体層と絶縁材料を介して交互に積層し接地端子に接
    続した第２の導体層とを備えたことを特徴とする半導体
    集積回路用パッケージ。
JP1231936A 1989-09-06 1989-09-06 半導体集積回路用パッケージ Pending JPH0394452A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1231936A JPH0394452A (ja) 1989-09-06 1989-09-06 半導体集積回路用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1231936A JPH0394452A (ja) 1989-09-06 1989-09-06 半導体集積回路用パッケージ

Publications (1)

Publication Number Publication Date
JPH0394452A true JPH0394452A (ja) 1991-04-19

Family

ID=16931385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1231936A Pending JPH0394452A (ja) 1989-09-06 1989-09-06 半導体集積回路用パッケージ

Country Status (1)

Country Link
JP (1) JPH0394452A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0537208A (ja) * 1991-07-31 1993-02-12 Mitsubishi Electric Corp マイクロ波パツケージ
US6091144A (en) * 1996-09-09 2000-07-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US6701509B2 (en) * 1999-08-10 2004-03-02 Koninklijke Philips Electronics N.V. Integrated circuit power and ground routing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0537208A (ja) * 1991-07-31 1993-02-12 Mitsubishi Electric Corp マイクロ波パツケージ
US6091144A (en) * 1996-09-09 2000-07-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US6701509B2 (en) * 1999-08-10 2004-03-02 Koninklijke Philips Electronics N.V. Integrated circuit power and ground routing

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