SK7442002A3 - Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon - Google Patents
Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon Download PDFInfo
- Publication number
- SK7442002A3 SK7442002A3 SK744-2002A SK7442002A SK7442002A3 SK 7442002 A3 SK7442002 A3 SK 7442002A3 SK 7442002 A SK7442002 A SK 7442002A SK 7442002 A3 SK7442002 A3 SK 7442002A3
- Authority
- SK
- Slovakia
- Prior art keywords
- silicon
- ion
- relief
- blasting
- nano
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 137
- 239000010703 silicon Substances 0.000 title claims abstract description 137
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000012212 insulator Substances 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- 230000035515 penetration Effects 0.000 claims abstract description 12
- -1 nitrogen molecular ions Chemical class 0.000 claims abstract description 9
- 230000005693 optoelectronics Effects 0.000 claims abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 230000000737 periodic effect Effects 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 64
- 238000005422 blasting Methods 0.000 claims description 59
- 239000004020 conductor Substances 0.000 claims description 50
- 229920001296 polysiloxane Polymers 0.000 claims description 11
- 230000004907 flux Effects 0.000 claims description 7
- 239000002210 silicon-based material Substances 0.000 claims description 7
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 27
- 238000000137 annealing Methods 0.000 description 13
- 230000000873 masking effect Effects 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 13
- 239000000523 sample Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 229910021419 crystalline silicon Inorganic materials 0.000 description 7
- 238000010884 ion-beam technique Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000004049 embossing Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000004883 computer application Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000013213 extrapolation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000005211 surface analysis Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 235000014101 wine Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/125—Quantum wire structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Nanotechnology (AREA)
- Health & Medical Sciences (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Toxicology (AREA)
- Physical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU99124768/28A RU2173003C2 (ru) | 1999-11-25 | 1999-11-25 | Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств |
| PCT/IB2000/001397 WO2001039259A1 (en) | 1999-11-25 | 2000-10-02 | Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SK7442002A3 true SK7442002A3 (en) | 2003-05-02 |
Family
ID=20227346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SK744-2002A SK7442002A3 (en) | 1999-11-25 | 2000-10-02 | Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon |
Country Status (23)
| Country | Link |
|---|---|
| US (1) | US6274007B1 (cs) |
| EP (1) | EP1104011A1 (cs) |
| JP (1) | JP2001156050A (cs) |
| KR (1) | KR20020069195A (cs) |
| CN (1) | CN1399791A (cs) |
| AU (1) | AU7547400A (cs) |
| BG (1) | BG106739A (cs) |
| BR (1) | BR0016095A (cs) |
| CA (1) | CA2392307A1 (cs) |
| CZ (1) | CZ20021824A3 (cs) |
| EE (1) | EE200200261A (cs) |
| HR (1) | HRP20020459A2 (cs) |
| HU (1) | HUP0203517A2 (cs) |
| IL (1) | IL149832A0 (cs) |
| IS (1) | IS6393A (cs) |
| MX (1) | MXPA02005281A (cs) |
| NO (1) | NO20022427L (cs) |
| PL (1) | PL355890A1 (cs) |
| RU (1) | RU2173003C2 (cs) |
| SK (1) | SK7442002A3 (cs) |
| WO (1) | WO2001039259A1 (cs) |
| YU (1) | YU38202A (cs) |
| ZA (1) | ZA200204822B (cs) |
Families Citing this family (105)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2191444C1 (ru) * | 2001-10-09 | 2002-10-20 | Общество с ограниченной ответственностью "Агентство маркетинга научных разработок" | Способ изготовления полевого транзистора с периодически легированным каналом |
| US6872645B2 (en) * | 2002-04-02 | 2005-03-29 | Nanosys, Inc. | Methods of positioning and/or orienting nanostructures |
| US7619562B2 (en) * | 2002-09-30 | 2009-11-17 | Nanosys, Inc. | Phased array systems |
| US7067867B2 (en) * | 2002-09-30 | 2006-06-27 | Nanosys, Inc. | Large-area nonenabled macroelectronic substrates and uses therefor |
| KR101191632B1 (ko) | 2002-09-30 | 2012-10-17 | 나노시스, 인크. | 대형 나노 인에이블 매크로전자 기판 및 그 사용 |
| US7051945B2 (en) * | 2002-09-30 | 2006-05-30 | Nanosys, Inc | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
| US7135728B2 (en) * | 2002-09-30 | 2006-11-14 | Nanosys, Inc. | Large-area nanoenabled macroelectronic substrates and uses therefor |
| CA2499944A1 (en) * | 2002-09-30 | 2004-04-15 | Nanosys, Inc. | Integrated displays using nanowire transistors |
| US20060289049A1 (en) * | 2003-06-26 | 2006-12-28 | Rj Mears, Llc | Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer |
| US7535041B2 (en) * | 2003-06-26 | 2009-05-19 | Mears Technologies, Inc. | Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7045377B2 (en) * | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US20060231857A1 (en) * | 2003-06-26 | 2006-10-19 | Rj Mears, Llc | Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device |
| US20070020860A1 (en) * | 2003-06-26 | 2007-01-25 | Rj Mears, Llc | Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods |
| US20060292765A1 (en) * | 2003-06-26 | 2006-12-28 | Rj Mears, Llc | Method for Making a FINFET Including a Superlattice |
| US20060243964A1 (en) * | 2003-06-26 | 2006-11-02 | Rj Mears, Llc | Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
| US7202494B2 (en) * | 2003-06-26 | 2007-04-10 | Rj Mears, Llc | FINFET including a superlattice |
| WO2005018005A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Semiconductor device including mosfet having band-engineered superlattice |
| US7586165B2 (en) * | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Microelectromechanical systems (MEMS) device including a superlattice |
| US20040266116A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Methods of fabricating semiconductor structures having improved conductivity effective mass |
| US7531829B2 (en) * | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US20040262594A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Semiconductor structures having improved conductivity effective mass and methods for fabricating same |
| US7153763B2 (en) | 2003-06-26 | 2006-12-26 | Rj Mears, Llc | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing |
| US20060267130A1 (en) * | 2003-06-26 | 2006-11-30 | Rj Mears, Llc | Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween |
| US20060220118A1 (en) * | 2003-06-26 | 2006-10-05 | Rj Mears, Llc | Semiconductor device including a dopant blocking superlattice |
| US7612366B2 (en) * | 2003-06-26 | 2009-11-03 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice layer above a stress layer |
| US20060273299A1 (en) * | 2003-06-26 | 2006-12-07 | Rj Mears, Llc | Method for making a semiconductor device including a dopant blocking superlattice |
| US6958486B2 (en) * | 2003-06-26 | 2005-10-25 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
| US7659539B2 (en) | 2003-06-26 | 2010-02-09 | Mears Technologies, Inc. | Semiconductor device including a floating gate memory cell with a superlattice channel |
| US7514328B2 (en) * | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
| US20050279991A1 (en) * | 2003-06-26 | 2005-12-22 | Rj Mears, Llc | Semiconductor device including a superlattice having at least one group of substantially undoped layers |
| US7227174B2 (en) * | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7531828B2 (en) * | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
| US7586116B2 (en) * | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
| US20070015344A1 (en) * | 2003-06-26 | 2007-01-18 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions |
| US6833294B1 (en) | 2003-06-26 | 2004-12-21 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7531850B2 (en) * | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
| US20070010040A1 (en) * | 2003-06-26 | 2007-01-11 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer |
| US20050282330A1 (en) * | 2003-06-26 | 2005-12-22 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers |
| US7446002B2 (en) * | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
| US7229902B2 (en) * | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
| US20070063186A1 (en) * | 2003-06-26 | 2007-03-22 | Rj Mears, Llc | Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer |
| US20070063185A1 (en) * | 2003-06-26 | 2007-03-22 | Rj Mears, Llc | Semiconductor device including a front side strained superlattice layer and a back side stress layer |
| US7491587B2 (en) * | 2003-06-26 | 2009-02-17 | Mears Technologies, Inc. | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
| US7045813B2 (en) * | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
| US20070020833A1 (en) * | 2003-06-26 | 2007-01-25 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer |
| US20060011905A1 (en) * | 2003-06-26 | 2006-01-19 | Rj Mears, Llc | Semiconductor device comprising a superlattice dielectric interface layer |
| US7598515B2 (en) * | 2003-06-26 | 2009-10-06 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
| US7768018B2 (en) | 2003-10-10 | 2010-08-03 | Wostec, Inc. | Polarizer based on a nanowire grid |
| RU2240280C1 (ru) | 2003-10-10 | 2004-11-20 | Ворлд Бизнес Ассошиэйтс Лимитед | Способ формирования упорядоченных волнообразных наноструктур (варианты) |
| DE10351059B4 (de) * | 2003-10-31 | 2007-03-01 | Roth & Rau Ag | Verfahren und Vorrichtung zur Ionenstrahlbearbeitung von Oberflächen |
| US20110039690A1 (en) * | 2004-02-02 | 2011-02-17 | Nanosys, Inc. | Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production |
| US8025960B2 (en) * | 2004-02-02 | 2011-09-27 | Nanosys, Inc. | Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production |
| US7553371B2 (en) | 2004-02-02 | 2009-06-30 | Nanosys, Inc. | Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production |
| CN101010780B (zh) * | 2004-04-30 | 2012-07-25 | 纳米系统公司 | 纳米线生长和获取的体系和方法 |
| US7785922B2 (en) | 2004-04-30 | 2010-08-31 | Nanosys, Inc. | Methods for oriented growth of nanowires on patterned substrates |
| US20050279274A1 (en) * | 2004-04-30 | 2005-12-22 | Chunming Niu | Systems and methods for nanowire growth and manufacturing |
| WO2006078281A2 (en) * | 2004-07-07 | 2006-07-27 | Nanosys, Inc. | Systems and methods for harvesting and integrating nanowires |
| JP2008515654A (ja) * | 2004-10-12 | 2008-05-15 | ナノシス・インク． | 導電性ポリマー及び半導体ナノワイヤに基づいてプラスチック電子部品を製造するための完全に集積化された有機層プロセス |
| US7473943B2 (en) * | 2004-10-15 | 2009-01-06 | Nanosys, Inc. | Gate configuration for nanowire electronic devices |
| RU2267832C1 (ru) * | 2004-11-17 | 2006-01-10 | Александр Викторович Принц | Способ изготовления микро- и наноприборов на локальных подложках |
| US7569503B2 (en) | 2004-11-24 | 2009-08-04 | Nanosys, Inc. | Contact doping and annealing systems and processes for nanowire thin films |
| US7351346B2 (en) * | 2004-11-30 | 2008-04-01 | Agoura Technologies, Inc. | Non-photolithographic method for forming a wire grid polarizer for optical and infrared wavelengths |
| US7561332B2 (en) * | 2004-11-30 | 2009-07-14 | Agoura Technologies, Inc. | Applications and fabrication techniques for large scale wire grid polarizers |
| US7560366B1 (en) | 2004-12-02 | 2009-07-14 | Nanosys, Inc. | Nanowire horizontal growth and substrate removal |
| KR100624461B1 (ko) * | 2005-02-25 | 2006-09-19 | 삼성전자주식회사 | 나노 와이어 및 그 제조 방법 |
| US7604690B2 (en) * | 2005-04-05 | 2009-10-20 | Wostec, Inc. | Composite material for ultra thin membranes |
| JP2009513368A (ja) * | 2005-09-23 | 2009-04-02 | ナノシス・インコーポレイテッド | ナノ構造体のドーピング方法 |
| TWI316294B (en) * | 2005-12-22 | 2009-10-21 | Mears Technologies Inc | Method for making an electronic device including a selectively polable superlattice |
| US7517702B2 (en) * | 2005-12-22 | 2009-04-14 | Mears Technologies, Inc. | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
| US7741197B1 (en) | 2005-12-29 | 2010-06-22 | Nanosys, Inc. | Systems and methods for harvesting and reducing contamination in nanowires |
| JP2009522197A (ja) * | 2005-12-29 | 2009-06-11 | ナノシス・インコーポレイテッド | パターン形成された基板上のナノワイヤの配向した成長のための方法 |
| US7718996B2 (en) * | 2006-02-21 | 2010-05-18 | Mears Technologies, Inc. | Semiconductor device comprising a lattice matching layer |
| FI122010B (fi) * | 2006-08-09 | 2011-07-15 | Konstantin Arutyunov | Ionisuihkuetsausmenetelmä ja -laitteisto |
| CN101573778B (zh) * | 2006-11-07 | 2013-01-02 | 奈米系统股份有限公司 | 用于纳米线生长的系统与方法 |
| KR100836426B1 (ko) * | 2006-11-24 | 2008-06-09 | 삼성에스디아이 주식회사 | 비휘발성 메모리 소자 및 그 제조방법과 이를 포함한메모리 장치 |
| US7786024B2 (en) * | 2006-11-29 | 2010-08-31 | Nanosys, Inc. | Selective processing of semiconductor nanowires by polarized visible radiation |
| US20080129930A1 (en) * | 2006-12-01 | 2008-06-05 | Agoura Technologies | Reflective polarizer configuration for liquid crystal displays |
| US7781827B2 (en) | 2007-01-24 | 2010-08-24 | Mears Technologies, Inc. | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
| US7928425B2 (en) * | 2007-01-25 | 2011-04-19 | Mears Technologies, Inc. | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
| US7880161B2 (en) | 2007-02-16 | 2011-02-01 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
| US7863066B2 (en) * | 2007-02-16 | 2011-01-04 | Mears Technologies, Inc. | Method for making a multiple-wavelength opto-electronic device including a superlattice |
| US7812339B2 (en) * | 2007-04-23 | 2010-10-12 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
| US8668833B2 (en) * | 2008-05-21 | 2014-03-11 | Globalfoundries Singapore Pte. Ltd. | Method of forming a nanostructure |
| KR102067922B1 (ko) | 2009-05-19 | 2020-01-17 | 원드 매터리얼 엘엘씨 | 배터리 응용을 위한 나노구조화된 재료 |
| US8623288B1 (en) | 2009-06-29 | 2014-01-07 | Nanosys, Inc. | Apparatus and methods for high density nanowire growth |
| CN102386096A (zh) * | 2010-08-31 | 2012-03-21 | 上海华虹Nec电子有限公司 | 改善ldmos性能一致性和稳定性的方法 |
| WO2013006077A1 (en) * | 2011-07-06 | 2013-01-10 | Wostec, Inc. | Solar cell with nanostructured layer and methods of making and using |
| KR20140054183A (ko) | 2011-08-05 | 2014-05-08 | 워스텍, 인코포레이티드 | 나노구조 층을 갖는 발광 다이오드 및 그의 제조 및 사용 방법 |
| WO2013089578A1 (en) * | 2011-12-12 | 2013-06-20 | Wostec, Inc. | Sers-sensor with nanostructured surface and methods of making and using |
| WO2013109157A1 (en) | 2012-01-18 | 2013-07-25 | Wostec, Inc. | Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using |
| WO2013141740A1 (en) | 2012-03-23 | 2013-09-26 | Wostec, Inc. | Sers-sensor with nanostructured layer and methods of making and using |
| WO2014142700A1 (en) | 2013-03-13 | 2014-09-18 | Wostec Inc. | Polarizer based on a nanowire grid |
| WO2015077595A1 (en) | 2013-11-22 | 2015-05-28 | Mears Technologies, Inc. | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
| CN105900241B (zh) | 2013-11-22 | 2020-07-24 | 阿托梅拉公司 | 包括超晶格耗尽层堆叠的半导体装置和相关方法 |
| US9716147B2 (en) | 2014-06-09 | 2017-07-25 | Atomera Incorporated | Semiconductor devices with enhanced deterministic doping and related methods |
| US20170194167A1 (en) * | 2014-06-26 | 2017-07-06 | Wostec, Inc. | Wavelike hard nanomask on a topographic feature and methods of making and using |
| US9722046B2 (en) | 2014-11-25 | 2017-08-01 | Atomera Incorporated | Semiconductor device including a superlattice and replacement metal gate structure and related methods |
| EP3281231B1 (en) | 2015-05-15 | 2021-11-03 | Atomera Incorporated | Method of fabricating semiconductor devices with superlattice and punch-through stop (pts) layers at different depths |
| WO2016196600A1 (en) | 2015-06-02 | 2016-12-08 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
| US9558939B1 (en) | 2016-01-15 | 2017-01-31 | Atomera Incorporated | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
| WO2018093284A1 (en) | 2016-11-18 | 2018-05-24 | Wostec, Inc. | Optical memory devices using a silicon wire grid polarizer and methods of making and using |
| WO2018156042A1 (en) | 2017-02-27 | 2018-08-30 | Wostec, Inc. | Nanowire grid polarizer on a curved surface and methods of making and using |
| RU2671294C1 (ru) * | 2017-11-28 | 2018-10-30 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" | Способ изготовления полупроводникового прибора |
| CN110137254B (zh) * | 2019-04-30 | 2021-07-09 | 中国科学技术大学 | 半导体栅极电控量子点及其制备方法 |
| CN114497275A (zh) * | 2021-12-29 | 2022-05-13 | 昆明物理研究所 | 硅量子点光伏异质结制备方法 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2141699C1 (ru) | 1997-09-30 | 1999-11-20 | Закрытое акционерное общество Центр "Анализ Веществ" | Способ формирования твердотельных наноструктур |
-
1999
- 1999-11-25 RU RU99124768/28A patent/RU2173003C2/ru not_active IP Right Cessation
-
2000
- 2000-03-14 US US09/525,722 patent/US6274007B1/en not_active Expired - Fee Related
- 2000-03-21 EP EP00302277A patent/EP1104011A1/en not_active Withdrawn
- 2000-03-22 JP JP2000079824A patent/JP2001156050A/ja active Pending
- 2000-10-02 IL IL14983200A patent/IL149832A0/xx unknown
- 2000-10-02 CZ CZ20021824A patent/CZ20021824A3/cs unknown
- 2000-10-02 SK SK744-2002A patent/SK7442002A3/sk not_active Application Discontinuation
- 2000-10-02 AU AU75474/00A patent/AU7547400A/en not_active Abandoned
- 2000-10-02 WO PCT/IB2000/001397 patent/WO2001039259A1/en not_active Application Discontinuation
- 2000-10-02 EE EEP200200261A patent/EE200200261A/xx unknown
- 2000-10-02 KR KR1020027006725A patent/KR20020069195A/ko not_active Application Discontinuation
- 2000-10-02 PL PL00355890A patent/PL355890A1/xx not_active Application Discontinuation
- 2000-10-02 HU HU0203517A patent/HUP0203517A2/hu unknown
- 2000-10-02 CN CN00816289A patent/CN1399791A/zh active Pending
- 2000-10-02 MX MXPA02005281A patent/MXPA02005281A/es unknown
- 2000-10-02 CA CA002392307A patent/CA2392307A1/en not_active Abandoned
- 2000-10-02 BR BR0016095-4A patent/BR0016095A/pt not_active Application Discontinuation
-
2002
- 2002-05-22 NO NO20022427A patent/NO20022427L/no not_active Application Discontinuation
- 2002-05-24 IS IS6393A patent/IS6393A/is unknown
- 2002-05-24 YU YU38202A patent/YU38202A/sh unknown
- 2002-05-24 HR HR20020459A patent/HRP20020459A2/xx not_active Application Discontinuation
- 2002-05-27 BG BG106739A patent/BG106739A/xx unknown
- 2002-06-14 ZA ZA200204822A patent/ZA200204822B/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001039259A1 (en) | 2001-05-31 |
| AU7547400A (en) | 2001-06-04 |
| HRP20020459A2 (en) | 2005-10-31 |
| PL355890A1 (en) | 2004-05-31 |
| IL149832A0 (en) | 2002-11-10 |
| RU2173003C2 (ru) | 2001-08-27 |
| YU38202A (sh) | 2006-08-17 |
| BR0016095A (pt) | 2004-03-23 |
| ZA200204822B (en) | 2003-11-26 |
| NO20022427L (no) | 2002-06-25 |
| CN1399791A (zh) | 2003-02-26 |
| CZ20021824A3 (cs) | 2004-10-13 |
| MXPA02005281A (es) | 2006-02-10 |
| KR20020069195A (ko) | 2002-08-29 |
| JP2001156050A (ja) | 2001-06-08 |
| IS6393A (is) | 2002-05-24 |
| CA2392307A1 (en) | 2001-05-31 |
| EE200200261A (et) | 2003-08-15 |
| NO20022427D0 (no) | 2002-05-22 |
| HUP0203517A2 (en) | 2003-07-28 |
| BG106739A (en) | 2003-08-29 |
| EP1104011A1 (en) | 2001-05-30 |
| US6274007B1 (en) | 2001-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SK7442002A3 (en) | Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon | |
| US8536000B2 (en) | Method for producing a semiconductor device have fin-shaped semiconductor regions | |
| US5543342A (en) | Method of ion implantation | |
| US8048788B2 (en) | Method for treating non-planar structures using gas cluster ion beam processing | |
| US20110084215A1 (en) | Method and system for tilting a substrate during gas cluster ion beam processing | |
| TW201303994A (zh) | 鰭片場效電晶體結構的形成方法 | |
| US20110084214A1 (en) | Gas cluster ion beam processing method for preparing an isolation layer in non-planar gate structures | |
| EP0082640B1 (en) | Ion implantation method | |
| Smirnov et al. | Wave-ordered structures formed on SOI wafers by reactive ion beams | |
| US20150054059A1 (en) | Silicon Dot Formation by Direct Self-Assembly Method for Flash Memory | |
| JPH04211144A (ja) | カンチレバーにされた微細先端を製造する方法 | |
| TWI451534B (zh) | 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置 | |
| RU2632581C2 (ru) | Подложка для электронной литографии высокого разрешения и соответствующий способ литографии | |
| US8193525B2 (en) | Method for producing planar transporting resonance heterostructures | |
| TW478013B (en) | Method of formation of nano-structures on the surface of silicon | |
| US20050145896A1 (en) | Memory device and method of manufacturing the same | |
| Zarowin | Basis of macroscopic and microscopic surface shaping and smoothing by plasma assisted chemical etching | |
| EP1628908A4 (en) | FORMATION OF SILICON NANOSTRUCTURES | |
| GB2131748A (en) | Silicon etch process | |
| Sharp et al. | A Chemical Approach to 3-D Lithographic Patterning of Si and Ge Nanocrystals | |
| Arzikulov et al. | Investigations of the formation of nanosized objects in manganese implanted silicon single crystals by the methods of Raman scattering of light and atomic force microscopy | |
| JPH1174232A (ja) | 膜のパターニング方法 | |
| CN118151467A (zh) | 一种有聚焦能力的光波导制备方法、光波导及频率转换器 | |
| Amirov et al. | Implantation of low-energy boron ions into silicon from a low-temperature high-density Ar+ BF 3 plasma | |
| JPS61112324A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FC9A | Refused patent application |