JP2008515654A - 導電性ポリマー及び半導体ナノワイヤに基づいてプラスチック電子部品を製造するための完全に集積化された有機層プロセス - Google Patents
導電性ポリマー及び半導体ナノワイヤに基づいてプラスチック電子部品を製造するための完全に集積化された有機層プロセス Download PDFInfo
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- JP2008515654A JP2008515654A JP2007536710A JP2007536710A JP2008515654A JP 2008515654 A JP2008515654 A JP 2008515654A JP 2007536710 A JP2007536710 A JP 2007536710A JP 2007536710 A JP2007536710 A JP 2007536710A JP 2008515654 A JP2008515654 A JP 2008515654A
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- conductive polymer
- nanowires
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- nanowire
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/068—Nanowires or nanotubes comprising a junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
- H10K30/30—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
- H10K30/35—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains comprising inorganic nanostructures, e.g. CdSe nanoparticles
- H10K30/352—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains comprising inorganic nanostructures, e.g. CdSe nanoparticles the inorganic nanostructures being nanotubes or nanowires, e.g. CdTe nanotubes in P3HT polymer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
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Abstract
Description
この出願は米国仮特許出願第60/617,830号(2004年10月12日出願)の優先権を主張し、その全体をここに組み入れる。
適用なし。
本発明はナノワイヤ、ナノリボン又は他の適当なナノ構造体(例えば、ナノロッド、ナノチューブなど)を用いた薄膜トランジスタ、及びマクロ電子部品の生産に有用な導電性ポリマー物質(例えば、ポリアニリン(PANI)又はポリピロール(PPY))を用いたこのようなトランジスタを製造する生産規模拡張自在の方法に関する。特に、導電性ポリマー薄膜の中、上又は内に組み込まれた方向付き半導体ナノワイヤ、ナノリボンなど用いて、キャリヤー移動度が高くかつ導電チャンネルがワイヤ/リボン軸に平行な薄膜トランジスタ(TFT)を製造することによって、マクロ電子部品の全く新しい概念が発展してきた。導電性ポリマーは、金属又は半導体と同様の電気的、磁気的及び光学的特性を示す一方で、柔軟性、加工の容易さ、導電率の可変性はそのままであるので、ナノワイヤなどのナノ構造体を用いるマクロ電子部品の用途に特に魅力的である。これらのポリマーの導電率は絶縁体からほぼ金属状態まで変えることができ、その大きさはドーパントの種類及びレベルを制御することにより10〜15のオーダーだけ可逆的に調節できる。導電性ポリマーはまた、大型基板(例えば、プラスチック基板)上のデバイスの特徴(例えば、ゲート、ソース及び/又はドレインコンタクト領域)を相対的に低コストでパターン化できるように、例えば導電性ポリマーに光エネルギー(例えば深紫外線エネルギーなど)を当てることによって簡単にパターン化することができる。
添付図面に関して本発明を説明する。図中、同じ参照番号は同じ要素又は機能上類似の要素を示す。要素が最初に現れる図面は対応する参照番号中の最も左の数字により示される。
ここに記載の特定の実装は本発明の例であり、本発明の範囲を決して限定するものではないことを理解すべきである。実際、簡潔さのために、従来の電子部品、製造、半導体デバイス並びにナノチューブ、ナノロッド、ナノワイヤ及びナノリボン技術や、システム(システムの個々の作業部品の構成要素)の他の機能面については、ここで詳細に説明しない。さらに、簡潔さのため、ここではしばしば本発明をナノワイヤを含んだ半導体トランジスタデバイスに属するものとして説明する。しかし、本発明はナノワイヤに限定されるものではなく、ナノチューブ、ナノロッド、ナノウィスカー、ナノリボンなどのその他のナノ構造体も使用できる。また、ここに記載の特定の実装についてナノワイヤの数及びそれらのナノワイヤの間隔が与えられているが、実装を限定するものではなく、広範囲のナノワイヤ数及び間隔が使用できる。ここに記載の製造技術を用いて任意の半導体デバイス型や他の電子コンポーネント型を作ることができることを理解すべきである。さらに、これらの技術は、電気システム、光学システム、コンシューマ用電子部品、産業用電子部品、無線システム、宇宙用途、又は他の任意の用途に適用するのに適している。
図1A及び1Bは高移動度ナノワイヤTFTの基になる概念を示す。図1Aはアモルファス又は多結晶Si TFTを表す。図1Aから分かるように、電気キャリヤーが複数の粒界を横断しなければならないので、キャリヤー移動度が低下する。キャリヤーが複数の粒界を横断しなければならないことで移動度が低下するSi又はポリSi TFTとは違って、本発明の態様によると、NW−TFTは、(丸木橋のように)平行な複数の単結晶NW経路により形成された導電チャンネルを有し、よって、ソース10を横断してドレイン電極20までずっと単結晶内を進ませるので、高いキャリヤー移動度を保証する。図1Bは代表的なNW−TFTであり、ソース10のコンタクト領域とドレイン20のコンタクト領域との間のチャンネル長にわたって張られたナノワイヤ30を示す。
図2A−Jは本発明の態様によるNW−TFTの製造方法を説明する。本方法は図2Aに示されるデバイス基板100から開始する。このデバイス基板100は、様々な材料、例えば柔軟な基板や硬い基板、小面積の基板や大面積の基板を含めて、例えばプラスチック、セラミック、金属又は半金属、半導体、ガラス、石英などから作ることができる。図2Bに示された最初のプロセス工程では、導電性ポリマー層102を基板100上にデポジットする。導電性ポリマー層は、例えば、スピンコーティング、キャスティング、印刷(例えばインクジェット印刷)、ワイヤロッディング、吹き付け、ダイナミック・ブラシ・ペインティングなどを含めた種々のデポジション技術を用い、例えばロールツーロール法などの技術を用いてデポジットさせることができる。
ここに記載の態様は、NW−TFT技術に適用された場合、非常に大きく柔軟な基板上に従来の単結晶シリコンから製造されたトランジスタの性能特性に匹敵するかそれを超える性能特性を有するトランジスタを製造できる。これにより、超大規模高密度の電気的集積化が可能になり、真のシリコン・オン・プラスチック技術が得られる。この技術の潜在的な用途は軍事用途を含めて非常に広い。NW−TFT技術は、RF通信、太陽電池、スマートカード、無線周波識別タグ、検出器、センサーアレイ、X線イメージャー、柔軟な表示装置(例えば、アクティブマトリックス液晶ディスプレイ)、電子部品などを含めて様々なユニークな用途の開発を可能にする。
20 ドレイン
30 ナノワイヤ
100 デバイス基板
102 導電性ポリマー層
104 ゲートマスク
108 ゲートコンタクト領域
110 誘電体層
111 バイア
112 ナノワイヤ
114 第2の導電性ポリマー層
116 ソースコンタクト領域
118 ドレインコンタクト領域
Claims (39)
- 導電性ポリマー物質とその中に組み込まれた1又は複数のナノワイヤとを含んだ複合材料。
- 前記導電性ポリマー物質がポリアニリン(PANI)又はポリピロール(PPY)を含む請求項1に記載の複合材料。
- 請求項1に記載の複合材料を含んだLED、レーザー、導波路、又はLCDバックプレーン。
- 請求項1に記載の複合材料を含んだフラットパネルディスプレイ(FPD)、太陽電池、画像センサーアレイ又はデジタルX線イメージャー。
- a.基板と;
b.前記基板上にデポジットされた導電性ポリマー層であって、動作電流レベルに達するのに十分なナノワイヤの密度にて複数のナノワイヤを含んだ前記導電性ポリマー層と;
c.前記導電性ポリマー層中に形成されたソース及びドレイン領域と;
d.前記導電性ポリマー層上に形成されたゲートと;
を備えたトランジスタデバイス。 - 前記複数のナノワイヤがそれらの長軸にほぼ平行に方向付けられた請求項5に記載のデバイス。
- 前記ナノワイヤが該ナノワイヤの少なくとも一部の上にデポジットさせた酸化物の層を備える請求項5に記載のデバイス。
- 前記ナノワイヤと前記ソース及びドレイン領域との間のオーム接触を改善するためにナノワイヤの両端の上には実質的に酸化物層を有さない請求項7に記載のデバイス。
- 前記ナノワイヤが単層薄膜、サブ単層薄膜、又は多層薄膜として形成される請求項5に記載のデバイス。
- 前記基板がプラスチック物質から作られる請求項5に記載のデバイス。
- a.デバイス基板を設け;
b.前記デバイス基板上に第1の導電性ポリマー層をデポジットし;
c.1又は複数のゲートコンタクト領域を前記導電性ポリマー層中に形成し;
d.動作電流レベルに達するのに十分なナノワイヤの密度にて前記導電性ポリマー層上に複数のナノワイヤをデポジットし;
e.前記複数のナノワイヤ上に第2の導電性ポリマー層をデポジットし;そして
f.前記第2の導電性ポリマー層中にソース及びドレインコンタクト領域を形成することで前記複数のナノワイヤと電気的に接続し、それにより前記ナノワイヤが前記ソース及びドレイン領域の夫々の領域間の長さを有するチャンネルを形成する;
ことをからなるトランジスタデバイスの製造方法。 - 前記ナノワイヤをそれらの長軸にほぼ平行に整列させることを更に含む請求項11に記載の方法。
- 1又は複数のゲートコンタクト領域を形成することが、前記第1の導電性ポリマー層の1又は複数の部分をマスクし、マスクしていない部分に紫外線エネルギーを当てて該マスクしていない部分の抵抗性を高めることから成る請求項11に記載の方法。
- 前記第1の導電性ポリマー層上にゲート誘電体層を形成することを更に含む請求項11に記載の方法。
- 前記複数のナノワイヤを前記ゲート誘電体層上にデポジットする請求項14に記載の方法。
- 前記ソース及びドレイン領域を前記第2の導電性ポリマー層中に形成することが、前記第2の導電性ポリマー層の少なくとも2又はそれより多くの部分をマスクし、マスクしていない部分に紫外線エネルギーを当てて該マスクしていない部分の抵抗性を高めることから成る請求項11に記載の方法。
- 前記第1及び/又は第2の導電性ポリマー層をデポジットすることが、スピンコーティング、キャスティング、印刷、ワイヤロッディング、吹き付け、又はブラシ塗装から選択した方法を用いることから成る請求項11に記載の方法。
- 金属又はドープシリコンを前記ソース及びドレインコンタクト領域中にデポジットすることを更に含む請求項11に記載の方法。
- ゲート電極を前記ゲートコンタクト領域中に形成することを更に含む請求項11に記載の方法。
- a.基板を設け;
b.複数のナノワイヤを組み込んだ導電性ポリマー層を前記基板上にデポジットし;
c.ソース及びドレインコンタクト領域を前記導電性ポリマー層中に形成することで前記複数のナノワイヤと電気的に接続し、それにより前記ナノワイヤが前記ソース及びドレインコンタクト領域のそれぞれの領域間の長さを有するチャンネルを形成し;そして
d.ゲートを前記導電性ポリマー層上に形成する;
ことから成るトランジスタデバイスの製造方法。 - 前記ナノワイヤをそれらの長軸にほぼ平行に整列させることを更に含む請求項20に記載の方法。
- 前記ソース及びドレインコンタクト領域を形成することが、前記第1の導電性ポリマー層の2又はそれより多くの部分をマスクし、マスクしていない部分に紫外線エネルギーを当てて該マスクしていない部分の抵抗性を高めることから成る請求項20に記載の方法。
- 前記導電性ポリマー層をデポジットすることが、スピンコーティング、キャスティング、印刷、ワイヤロッディング、吹き付け、又はブラシ塗装から選択されたコーティング方法を用いることから成る請求項20に記載の方法。
- 金属又はドープシリコンを前記ソース及びドレインコンタクト領域中にデポジットすることを更に含む請求項20に記載の方法。
- 前記ゲートを形成することが金属を前記導電性ポリマー層の一部の上にデポジットすることから成る請求項20に記載の方法。
- 前記ナノワイヤが該ナノワイヤの少なくとも一部の上にデポジットさせた酸化物の層を備える請求項20に記載の方法。
- 前記ナノワイヤと前記ソース及びドレインコンタクト領域との間のオーム接触を向上させるため、前記デバイスの前記ソース及びドレインコンタクト領域の近くにて前記ナノワイヤの両端の前記酸化物層の一部を除去することを更に含む請求項26に記載の方法。
- 前記ナノワイヤを単層薄膜、サブ単層薄膜、又は多層薄膜として形成する請求項20に記載の方法。
- 前記基板がプラスチック物質から作られる請求項20に記載の方法。
- a.基板を設け;
b.前記基板上に第1の導電性ポリマー層をデポジットし;
c.1又は複数のゲートコンタクト領域を前記第1の導電性ポリマー層中に形成し;
d.複数のナノワイヤを中に組み込んだ第2の導電性ポリマー層を前記第1の導電性ポリマー層の上にデポジットし;そして
e.ソース及びドレインコンタクト領域を前記第2の導電性ポリマー層中に形成することで前記複数のナノワイヤと電気的に接続し、それにより前記ナノワイヤが前記ソース及びドレイン領域のそれぞれの領域間の長さを有するチャンネルを形成すること;
から成るトランジスタデバイスの製造方法。 - 前記ナノワイヤをそれらの長軸にほぼ平行に整列させることを更に含む請求項30に記載の方法。
- 前記ゲートコンタクト領域を形成することが、前記第1の導電性ポリマー層の1又は複数の部分をマスクし、マスクしていない部分に紫外線エネルギーを当てて該マスクしていない部分の抵抗性を高めることから成る請求項30に記載の方法。
- 前記第1及び/又は第2の導電性ポリマー層をデポジットすることが、スピンコーティング、キャスティング、印刷、ワイヤロッディング、吹き付け、又はブラシ塗装から選択されたコーティング方法を用いることから成る請求項30に記載の方法。
- 金属又はドープシリコンを前記ゲート、ソース及び/又はドレインコンタクト領域中にデポジットすることを更に含む請求項30に記載の方法。
- ゲート電極を前記ゲートコンタクト領域中に形成することを更に含む請求項30に記載の方法。
- 前記ナノワイヤが該ナノワイヤの少なくとも一部の上にデポジットさせた酸化物の層を備える請求項30に記載の方法。
- 前記ナノワイヤと前記ソース及びドレインコンタクト領域との間のオーム接触を向上させるために、前記デバイスの前記ソース及びドレインコンタクト領域の近くにて前記ナノワイヤの両端の前記酸化物層の一部を除去することを更に含む請求項36に記載の方法。
- 前記ナノワイヤを単層薄膜、サブ単層薄膜、又は多層薄膜として形成する請求項30に記載の方法。
- 前記基板がプラスチック物質から作られる請求項30に記載の方法。
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Also Published As
Publication number | Publication date |
---|---|
EP1805823A2 (en) | 2007-07-11 |
US20060214156A1 (en) | 2006-09-28 |
WO2006124055A3 (en) | 2007-04-19 |
WO2006124055A2 (en) | 2006-11-23 |
US7345307B2 (en) | 2008-03-18 |
US20080128688A1 (en) | 2008-06-05 |
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