US20080128688A1 - Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires - Google Patents

Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires Download PDF

Info

Publication number
US20080128688A1
US20080128688A1 US12/016,701 US1670108A US2008128688A1 US 20080128688 A1 US20080128688 A1 US 20080128688A1 US 1670108 A US1670108 A US 1670108A US 2008128688 A1 US2008128688 A1 US 2008128688A1
Authority
US
United States
Prior art keywords
nanowires
conductive polymer
process
polymer layer
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/016,701
Inventor
Yaoling Pan
Francisco Leon
David P. Stumbo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanosys Inc
Original Assignee
Nanosys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US61783004P priority Critical
Priority to US11/233,503 priority patent/US7345307B2/en
Application filed by Nanosys Inc filed Critical Nanosys Inc
Priority to US12/016,701 priority patent/US20080128688A1/en
Publication of US20080128688A1 publication Critical patent/US20080128688A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
    • H01L51/0504Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or swiched, e.g. three-terminal devices
    • H01L51/0508Field-effect devices, e.g. TFTs
    • H01L51/0512Field-effect devices, e.g. TFTs insulated gate field effect transistors
    • H01L51/0545Lateral single gate single channel transistors with inverted structure, i.e. the organic semiconductor layer is formed after the gate electrode
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/068Nanowires or nanotubes comprising a junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
    • H01L51/0504Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or swiched, e.g. three-terminal devices
    • H01L51/0508Field-effect devices, e.g. TFTs
    • H01L51/0512Field-effect devices, e.g. TFTs insulated gate field effect transistors
    • H01L51/0541Lateral single gate single channel transistors with non inverted structure, i.e. the organic semiconductor layer is formed before the gate electode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/42Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture
    • H01L51/4253Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture comprising bulk hetero-junctions, e.g. interpenetrating networks
    • H01L51/426Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture comprising bulk hetero-junctions, e.g. interpenetrating networks comprising inorganic nanostructures, e.g. CdSe nanoparticles
    • H01L51/4266Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture comprising bulk hetero-junctions, e.g. interpenetrating networks comprising inorganic nanostructures, e.g. CdSe nanoparticles the inorganic nanostructures being nanotubes or nanowires, e.g. CdTe nanotubes in P3HT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
    • H01L51/0034Organic polymers or oligomers
    • H01L51/0035Organic polymers or oligomers comprising aromatic, heteroaromatic, or arrylic chains, e.g. polyaniline, polyphenylene, polyphenylene vinylene
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
    • H01L51/0034Organic polymers or oligomers
    • H01L51/0035Organic polymers or oligomers comprising aromatic, heteroaromatic, or arrylic chains, e.g. polyaniline, polyphenylene, polyphenylene vinylene
    • H01L51/0036Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
    • H01L51/0037Polyethylene dioxythiophene [PEDOT] and derivatives
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
    • H01L51/0045Carbon containing materials, e.g. carbon nanotubes, fullerenes
    • H01L51/0048Carbon nanotubes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
    • H01L51/0045Carbon containing materials, e.g. carbon nanotubes, fullerenes
    • H01L51/0048Carbon nanotubes
    • H01L51/0049Carbon nanotubes comprising substituents
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
    • H01L51/0504Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or swiched, e.g. three-terminal devices
    • H01L51/0508Field-effect devices, e.g. TFTs
    • H01L51/0512Field-effect devices, e.g. TFTs insulated gate field effect transistors
    • H01L51/0558Field-effect devices, e.g. TFTs insulated gate field effect transistors characterised by the channel of the transistor
    • H01L51/0566Field-effect devices, e.g. TFTs insulated gate field effect transistors characterised by the channel of the transistor the channel comprising a composite layer, e.g. a mixture of donor and acceptor moieties, forming pn - bulk hetero junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/42Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture
    • H01L51/4253Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for sensing infra-red radiation, light, electro-magnetic radiation of shorter wavelength or corpuscular radiation and adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation using organic materials as the active part, or using a combination of organic materials with other material as the active part; Multistep processes for their manufacture comprising bulk hetero-junctions, e.g. interpenetrating networks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/54Material technologies
    • Y02E10/549Material technologies organic PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/52Manufacturing of products or systems for producing renewable energy
    • Y02P70/521Photovoltaic generators
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/762Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/762Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y10S977/763Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less formed along or from crystallographic terraces or ridges
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/762Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y10S977/764Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less with specified packing density

Abstract

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 11/233,503, filed Sep. 22, 2005, which claims priority to U.S. Provisional Patent Application No. 60/617,830, filed Oct. 12, 2004, the entirety of each is incorporated herein.
  • STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
  • Not applicable.
  • BACKGROUND OF THE INVENTION
  • The present invention relates to semiconductor devices, and more particularly, to the fabrication and use of novel electronic devices made using conductive polymer materials having nanowires (or other nanostructures) incorporated therein and/or thereon.
  • The advancement of electronics has been moving towards two extremes in terms of physical scale. Rapid miniaturization of microelectronics according to Moore's law has led to remarkable increases in computing power while at the same time enabling reductions in cost. In parallel, extraordinary progress has been made in the other, relatively less noticed, area of macroelectronics, where electronic devices are integrated over large area substrates with sizes measured in square meters. Current macroelectronics are primarily based on amorphous silicon (a-Si) or polycrystalline silicon (p-Si) thin film transistors (TFTs) on glass, and are finding important applications in areas, including flat panel display (FPD), solar cells, smart cards, radiofrequency identification tags, image sensor arrays and digital x-ray imagers.
  • While the current technology is successful in many perspectives, it is limited in what applications it can address. For example, there has been growing interest in the use of plastic as the substrate for macroelectronics due to plastic's light weight, flexibility, shock resistance and low cost. However, the fabrication of high performance TFTs on plastics has been extremely challenging because all process steps must be carried out below the glass transition temperature of the plastic. Significant efforts have been devoted to search for new materials (such as organics and organic-inorganic hybrids) or new fabrication strategies suitable for TFTs on plastics, but only with limited success. Organic TFTs promise the potential of roll-to-roll fabrication process on plastic substrates, but with only a limited carrier mobility of about <1 cm2/V·s. The limitations posed by materials and/or substrate process temperature (particularly on plastic) lead to low device performance, restricting devices to low-frequency applications. Therefore, applications that require even modest computation, control, or communication functions cannot be addressed by the existing TFT technology.
  • Individual semiconductor nanowires (NWs) and single walled carbon nanotubes can be used to fabricate nanoscale field effect transistors (FETs) with electronic performance comparable to and in some case exceeding that of the highest-quality single-crystal materials. In particular, carrier mobility of 300 cm2/V·s has been demonstrated for p-Si NWs, 2000-4000 cm2/V·s for n-indium InP NWs and up to 20,000 cm2/V·s for single walled carbon nanotubes. These nanoFETs promise to push Moore's law to the ultimate limit—molecular level—with unprecedented performance. They are, however, currently hard to implement for production-scale nanoelectronics due to the complicated and limited scalability of the device fabrication processes.
  • What are needed are high performance TFTs that can be applied to plastics and other substrates requiring low process temperatures. What is also needed is a production scalable method for fabrication of nanoscale semiconductor devices than can be used as high performance TFTs on plastics and other substrates requiring low-process temperatures.
  • BRIEF SUMMARY OF THE INVENTION
  • The present invention is directed to thin film transistors using nanowires, nanoribbons or other suitable nanostructures (e.g., nanorods, nanotubes and the like), and production scalable methods to produce such transistors using conductive polymer materials (e.g., polyaniline (PANI) or polypyrrole (PPY)) useful in the production of macroelectronics. In particular, an entirely new concept of macroelectronics has been developed by using oriented semiconductor nanowires, nanoribbons etc. incorporated in, on or within conductive polymer films to produce thin film transistors (TFTs) having high carrier mobility, with the conducting channel parallel to the wire/ribbon axis. Conducting polymers are particularly appealing for macroelectronic applications using nanostructures such as nanowires because they exhibit electrical, magnetic and optical properties similar to metals or semiconductors, while retaining their flexibility, ease of processing, and modifiable electrical conductivity. The electrical conductivity of these polymers can vary from an insulator to almost the metallic state and can be reversibly modulated over 10 to 15 orders of magnitude by controlling the dopant type and level. The conductive polymers can also be patterned simply, e.g., by exposing the polymer to light energy (e.g., such as deep ultraviolet light energy) such that device features (e.g., gate, source and/or drain contact regions) on large area substrates (e.g., plastic substrates) may be patterned at relatively low cost.
  • A NW-TFT fabrication method is also provided in which the high-temperature active semiconductor materials synthesis process, that is creating the NWs or nanoribbons, is carried out before application of the active semiconductor materials to the device substrate. Subsequently, the NW-TFTs are incorporated into (or onto) conductive polymer films and applied to the device substrate via a solution assembly process or other methods like mechanic shearing, spin coating, deposition, etc. All of the electrodes and interconnects can be patterned, for example, simply by exposing the conductive polymer film(s) to deep ultraviolet light. The conducting path for all electrical interconnections as well as electrical insulation can be formed on the same substrate layer. All fabrication processes are additive, which is important for, e.g., roll to roll processing with plastic substrates. As a result, all the nanowires (or other nanostructure elements) in and/or on the conductive polymer film(s) are conformally contacted, which allows stacked wires to improve the current drive capability to create high current mobilities. Embodiments of NW-TFTs as described herein can be potentially deposited from solution onto large area substrates with low-cost, low-temperature processes including micro-contact, ink-jet printing technology and/or roll-to-roll processing techniques, for example.
  • Therefore, the present invention provides a facile technique for fabrication of transistor devices incorporating nanowire, nanoribbon, nanotube etc. conductive polymer thin films, which opens an entirely new paradigm for electronics, enabling a variety of new capabilities including, moving microelectronics from single crystal substrates to plastic substrates, integrating macroelectronics, microelectronics and potentially nanoelectronics at the device level, and integrating different semiconductor materials on a single substrate. This can impact a broad range of existing applications from flat-panel displays to image sensor arrays, and enable a whole new range of universal flexible, wearable, disposable electronics for computing, storage or communication.
  • In a first exemplary embodiment of the present invention, a composite material comprising a conductive polymeric material and one or more nanowires incorporated therein is disclosed. The composite material may be deposited on a device substrate using a variety of deposition techniques including, for example, spin coating, casting, printing, wire roding, spraying, dynamic brush-painting etc. The electrical properties of the conductive polymer material can be reversibly changed over the full range of conductivity from insulators to metallic conductors (e.g., the resistivity of the conductive polymer material can be increased by a magnitude of 10× or more, e.g., about 15× or more), e.g., simply by exposing the conductive polymer to light energy such as deep ultraviolet light energy. The conductive polymer may include polymeric material selected from the group comprising polyacytelenes, polydiacytelenes, polyaniline (PANI), polypyrrole (PPY), polythiophenes, poly (phenyl-quinoline) and other types of conductive polymers including polyphenylene vinylene (PPV), polyfluorenes, polyphenylene sulfide (PPS), polynaphthalene and the like. The conductive polymer may be undoped or doped with either the addition of acceptor or p-doping agents (e.g., AsF5, Br2, I2, HClO4, etc.), or the addition of donor or n-doping agents such as by dipping the conductive polymer in THF solution of alkali metal naphthalide or by electrochemical methods. The conductive polymer can be used neat, or as blends and compounds with other conductive polymers or with commodity polymers such as polyethylene, polypropylene, polystyrene, soft PVC, poly-(methylmetacrylate), phenol-formaldehyde resins, melamineformaldehyde resins, epoxies, and thermoplastic elastomers. The composite material, following deposition on a device substrate, may be patterned (e.g., upon exposure to light energy such as ultraviolet light energy) to form gate, source, and/or drain contact regions to provide transistor structures for new LED, laser, waveguide, or LCD backplane devices incorporating the composite material. Conductive materials such as metals, doped semiconductors, or conductive polymers optionally may be deposited into or onto the gate, drain, and/or source contact regions, e.g., to improve the ohmic contact between the source and drain regions and the nanowires and/or to form a gate contact electrode in the gate contact region.
  • In another exemplary embodiment of the invention, a NW-TFT device is disclosed which generally comprises a substrate; a conductive polymer layer deposited on the substrate, the conductive polymer layer including a plurality of nanowires at a sufficient density of nanowires to achieve an operational current level; a source and drain contact region defined in the conductive polymer layer; and a gate contact formed over the conductive polymer layer. The plurality of nanowires may be oriented substantially parallel to their long axis, or may be unaligned (e.g., randomly oriented). The nanowires may comprise a layer of oxide deposited on at least a portion of the nanowires. The oxide layer at the ends of the nanowires may be removed (e.g., by etching or laser ablation) to improve ohmic contact between the nanowires and the source and drain contact regions. A conductive material such as a metal or doped silicon may optionally be deposited in the gate, source and/or drain contact regions, e.g., to improve ohmic contact to the nanowires. The nanowires may be formed as a monolayer film, a sub monolayer film, or a multi-layer film. The device substrate may be made from a variety of materials including low-temperature materials such as glass or plastics.
  • In another embodiment of the invention, a process for making a transistor device is disclosed which generally comprises: providing a device substrate; depositing a first conductive polymer layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions. The process may comprise, for example, aligning the nanowires substantially parallel to their long axis. The step of defining one or more gate contact regions may comprise, for example, masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet light energy to render the unmasked portions highly resistive. The process may further comprise forming a gate dielectric layer on the first conductive polymer layer, wherein the plurality of nanowires are then deposited on the gate dielectric layer. The step of defining the source and drain contact regions in the second conductive polymer layer may comprise, for example, masking at least two or more portions of the second conductive polymer layer, and exposing the unmasked portions to ultraviolet light energy to render the unmasked portions highly resistive. The step of depositing the first and/or second conductive polymer layers may comprise, for example, using a process selected from spin coating, casting, printing (e.g., ink-jet printing), wire roding, spraying, or brush-painting. A conductive material such as a metal or doped silicon may optionally be deposited in the source and drain contact regions to improve ohmic contact to the nanowires.
  • In another embodiment of the invention, a process for making a transistor device is disclosed which generally comprises: providing a substrate; depositing a conductive polymer layer incorporating a plurality of nanowires on the substrate; defining source and drain contact regions in the conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain contact regions; and forming a gate on the conductive polymer layer. The nanowires may be aligned substantially parallel to their long axis. The step of defining the source and drain contact regions may comprise, for example, masking two or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet light energy to render the unmasked portions highly resistive. The step of depositing the conductive polymer layer may comprise, for example, using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting. A metal or doped silicon, for example, may optionally be deposited in the source and drain contact regions to improve ohmic contact to the nanowires. The nanowires may comprise a layer of oxide deposited on at least a portion of the nanowires, and the process may further comprise removing (e.g., by etching or laser ablation) a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions. The nanowires may be formed as a monolayer film, a sub monolayer film, or a multi-layer film. The device substrate may be made from a variety of materials including low-temperature materials such as plastics.
  • In another embodiment of the invention, a process for making a transistor device is disclosed which generally comprises: providing a substrate; depositing a first conductive polymer layer on the substrate; defining one or more gate contact regions in the first conductive polymer layer; depositing a second conductive polymer layer having a plurality of nanowires incorporated therein over the first conductive polymer layer; and forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain contact regions. The process may comprise aligning the nanowires substantially parallel to their long axis. The step of defining the gate contact region may comprise, for example, masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet light energy to render the unmasked portions highly resistive. The step of depositing the first and/or second conductive polymer layers may comprise, for example, using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting. A conductive material such as a metal or doped silicon may optionally be deposited in the gate, source and/or drain contact regions to improve ohmic contact to the nanowires. The nanowires may comprise a layer of oxide deposited on at least a portion of the nanowires, and the process may further comprise removing a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions.
  • Further embodiments, features, and advantages of the invention, as well as the structure and operation of the various embodiments of the invention are described in detail below with reference to accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. The drawing in which an element first appears is indicated by the left-most digit in the corresponding reference number.
  • FIG. 1A is a diagram of amorphous or polycrystalline Si TFTs.
  • FIG. 1B is a diagram of a NW-TFT, according to an embodiment of the invention.
  • FIG. 2A is schematic of a device substrate used in a method for NW-TFT fabrication, according to an embodiment of the invention.
  • FIG. 2B is a schematic showing deposition of a conductive polymer layer on the device substrate of FIG. 2A.
  • FIG. 2C is a schematic showing patterning of the conductive polymer layer of FIG. 2B and exposure of selected region(s) (e.g., unmasked regions) of the conductive polymer layer to ultraviolet light energy.
  • FIG. 2D is a schematic showing formation of a gate contact region in the conductive polymer layer following exposure of the selected region(s) of the conductive polymer layer to ultraviolet light energy.
  • FIG. 2E is a top view of the device substrate and conductive polymer layer of FIG. 2D following deposition of a gate dielectric layer on the conductive polymer layer and formation of a small via through the dielectric layer to the underlying gate contact region.
  • FIG. 2F is a side view of the device substrate, conductive polymer layer and gate dielectric layer of FIG. 2E.
  • FIG. 2G is a schematic showing deposition of a thin film of nanowires on the gate dielectric layer of FIG. 2F.
  • FIG. 2H is a schematic showing deposition of a second conductive polymer layer on the plurality of nanowires of FIG. 2G.
  • FIG. 2I is a schematic showing formation of a source and drain contact region in the second conductive polymer layer following exposure of selected (unmasked) regions of the second conductive polymer layer to ultraviolet light energy.
  • FIG. 2J is a schematic showing the NW-TFT device following formation of source and drain contact regions in the second conductive polymer layer following exposure of the selected regions of the second conductive polymer layer to ultraviolet light energy.
  • FIG. 3A is a schematic side view of another embodiment of a NW-TFT device made according to the teachings of the present invention in which a composite film including a conductive polymer material having a plurality of nanowires embedded therein is used to form the active layer of the device.
  • FIG. 3B is a top view of the NW-TFT device of FIG. 3A.
  • FIG. 3C is a schematic showing formation of a source and drain contact region in the composite film layer of the NW-TFT device of FIG. 3A following exposure of selected (unmasked) regions of the conductive polymer to ultraviolet light energy.
  • FIG. 3D is schematic showing the NW-TFT device following formation of source and drain contact regions in the composite film layer following exposure of the conductive polymer to ultraviolet light energy.
  • FIG. 4A a schematic of another embodiment of a NW-TFT device made according to the teachings of the present invention in which a composite film including a conductive polymer material having a plurality of nanowires embedded therein is deposited directly on a device substrate to form the active layer of the device.
  • FIG. 4B is a close-up view of a plurality of core-shell nanowires which are incorporated in the composite film layer of FIG. 4A
  • FIG. 4C is a cross-sectional view of a core-shell nanowire of FIG. 4B.
  • FIG. 4D is schematic showing formation of a source and drain contact region in the composite film layer of the NW-TFT device of FIG. 4A following exposure of selected (unmasked) regions of the conductive polymer to ultraviolet light energy.
  • FIG. 5A is an optical micrograph showing nanowires embedded in a conductive polymer film which are coated on a plastic substrate using a wire roding deposition process.
  • FIG. 5B is an optical micrograph showing nanowires embedded in a conductive polymer film which are coated on a plastic substrate using a dynamic paint brushing deposition process.
  • DETAILED DESCRIPTION OF THE INVENTION
  • It should be appreciated that the particular implementations shown and described herein are examples of the invention and are not intended to otherwise limit the scope of the present invention in any way. Indeed, for the sake of brevity, conventional electronics, manufacturing, semiconductor devices, and nanotube, nanorod, nanowire and nanoribbon technologies and other functional aspects of the systems (and components of the individual operating components of the systems) may not be described in detail herein. Furthermore, for purposes of brevity, the invention is frequently described herein as pertaining to a semiconductor transistor device including nanowires. However, the present invention is not limited to nanowires, and other nanostructures such as nanotubes, nanorods, nanowhiskers, nanoribbons and the like may be used. Moreover, while the number of nanowires and spacing of those nanowires are provided for the specific implementations discussed, the implementations are not intended to be limiting and a wide range of the number of nanowires and spacing can also be used. It should be appreciated that the manufacturing techniques described herein could be used to create any semiconductor device type, and other electronic component types. Further, the techniques would be suitable for application in electrical systems, optical systems, consumer electronics, industrial electronics, wireless systems, space applications, or any other application.
  • As used herein, the term “nanowire” generally refers to any elongated conductive or semiconductive material that includes at least one cross sectional dimension that is less than 500 nm, and preferably, less than 100 nm, and has an aspect ratio (length:width) of greater than 10, preferably, greater than 50, and more preferably, greater than 100. Examples of such nanowires include semiconductor nanowires as described in Published International Patent Application Nos. WO 02/17362, WO 02/48701, and 01/03208, carbon nanotubes, and other elongated conductive or semiconductive structures of like dimensions.
  • While the example implementations described herein principally use Si, other types of nanowires (and other nanostructures such as nanoribbons, nanotubes, nanorods and the like) can be used including semiconductive nanowires, that are comprised of semiconductor material selected from, e.g., Si, Ge, Sn, Se, Te, B, C (including diamond), P, B—C, B—P(BP6), B—Si, Si—C, Si—Ge, Si—Sn and Ge—Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu,Ag)(Al,Ga,In,Ti,Fe)(S,Se,Te)2, Si3N4, Ge3N4, Al2O3, (Al,Ga,In)2 (S,Se,Te)3, Al2CO, and an appropriate combination of two or more such semiconductors.
  • In certain aspects, the semiconductor may comprise a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si; or an n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
  • Additionally, the nanowires can include carbon nanotubes, or conductive or semiconductive organic polymer materials, (e.g., pentacene, and transition metal oxides).
  • Hence, although the term “nanowire” is referred to throughout the description herein for illustrative purposes, it is intended that the description herein also encompass the use of nanotubes. Nanotubes can be formed in combinations/thin films of nanotubes as is described herein for nanowires, alone or in combination with nanowires, to provide the properties and advantages described herein.
  • Furthermore, it is noted that thin film of nanowires of the present invention can be a “heterogeneous” film, which incorporates semiconductor nanowires and/or nanotubes, and/or any combination thereof of different composition and/or structural characteristics. For example, a “heterogeneous film” can includes nanowires/nanotubes with varying diameters and lengths, and nanowires and/or nanotubes that are “heterostructures” having varying characteristics including core-shell nanowire/nanotube structures and nanowires/nanotubes having different compositions along the length of the nanowire/nanotube as is described, for example, in U.S. Pat. No. 6,882,051, the entire contents of which are incorporated by reference herein.
  • In the context of the invention, although the focus of the detailed description relates to use of nanowire thin films on plastic substrates, the substrate to which nanowires are attached may comprise other materials, including, but not limited to: a uniform substrate, e.g., a wafer of solid material, such as silicon, glass, quartz, polymerics, etc.; a large rigid sheet of solid materials, e.g., glass, quartz, plastics such as polycarbonate, polystyrene, etc., or can comprise additional elements, e.g., structural, compositional, etc. A flexible substrate, such as a roll of plastic such as polyolefins, polyamide, and others, a transparent substrate, or combinations of these features can be employed. In addition, the substrate may include other circuit or structural elements that are part of the ultimately desired device. Particular examples of such elements include electrical circuit elements such as electrical contacts, other wires or conductive paths, including nanowires or other nanoscale conducting elements, optical and/or optoelectrical elements (e.g., lasers, LEDs, etc.), and structural elements (e.g., microcantilevers, pits, wells, posts, etc.).
  • By substantially “aligned” or “oriented” is meant that the longitudinal axes of a majority of nanowires in a collection or population of nanowires is oriented within 30 degrees of a single direction. Although the majority can be considered to be a number of nanowires greater than 50%, in various embodiments, 60%, 75%, 80%, 90%, or other percentage of nanowires can be considered to be a majority that are so oriented. In certain preferred aspects, the majority of nanowires are oriented within 10 degrees of the desired direction. In additional embodiments, the majority of nanowires may be oriented within other numbers or ranges of degrees of the desired direction.
  • It should be understood that the spatial descriptions (e.g., “above”, “below”, “up”, “down”, “top”, “bottom”, etc.) made herein are for purposes of illustration only, and that devices of the present invention can be spatially arranged in any orientation or manner.
  • I. NANOWIRE THIN FILM TRANSISTORS (NW-TFTS)
  • FIGS. 1A and 1B illustrate the underlying concept for high mobility nanowire TFTs. FIG. 1A represents amorphous or polycrystalline Si TFTs. As can be seen from FIG. 1A, electrical carriers have to travel across multiple grain boundaries resulting in low carrier mobility. Unlike a-Si or poly-Si TFTs in which carriers have to travel across multiple grain boundaries resulting in low mobility, according to an embodiment of the invention, NW-TFTs have conducting channels formed by multiple single crystal NW paths (like a log bridge) in parallel and thus charges travel within single crystals all the way across the source 10 to drain electrode 20 which ensures high carrier mobility. FIG. 1B illustrates an exemplary NW-TFT showing nanowires 30 which span the channel length between source 10 and drain 20 contact regions.
  • II. NW-TFT DEVICE FABRICATION
  • FIGS. 2A-J illustrate a method for NW-TFT fabrication, according to an embodiment of the invention. The method begins with a device substrate 100 shown in FIG. 2A which can be made from a variety of materials, e.g., including flexible and rigid substrates, and small area and large area substrates, e.g., plastics, ceramics, metals or semimetals, semiconductors, glass, quartz, etc. In the first process step shown in FIG. 2B, a conductive polymer layer 102 is deposited on the substrate 100. The conductive polymer layer may be deposited using a variety of deposition techniques including, for example, spin coating, casting, printing (e.g., ink-jet printing), wire roding, spraying, dynamic brush-painting etc. using techniques such as roll-to-roll processing, for example.
  • The electrical properties of conductive polymers can be reversibly changed over the full range of conductivity from insulators to metallic conductors, e.g., the resistivity of the conductive polymer material may be increased by an order of magnitude of about 10 or more times, for example, about 15 or more times. For example, the conductive polymer may include a material that is photosensitive such that the resistivity of the material may be altered by photochemical reactions (e.g., by exposing the material to ultraviolet light energy), or the electrical conductivity of the material can be altered by other means such as by physical, chemical or thermal means such as e-beam irradiation, plasma immersion, ion beam irradiation, thermal exposure, etc. The conductive polymer may include polymeric material selected from the group comprising polyacytelenes, polydiacytelenes, polyaniline (PANI), polypyrrole (PPY), polythiophenes, poly (phenyl-quinoline) and other types of conductive polymers including polyphenylene vinylene (PPV), polyfluorenes, polyphenylene sulfide (PPS), polynaphthalene and the like. Currently, polypyrrole and polyaniline are preferred and are the most commonly used conducting polymers because of their relatively superior stability. Polypyrrole may be deposited in film form by electrochemical means. Polyaniline is made soluble through the use of soluble counter-ions that associate with the dopant ions on the polymer backbone. Current commercial applications utilize intermediate conductivity levels of between about 10−2 and 102 S/cm.
  • The doping of semiconducting conjugated polymers such as polyaniline and polpyrrole leads to the presence of states in the bandgap (e.g., hopping states) and at sufficient dopant concentrations the band-gap effectively disappears and the polymer acts as a metal with high conductivities. Intrinsic conductivities of materials such as PANI or PPV are on the order of about 10−12 S/cm; doped conjugated polymers have achieved conductivities of >105 S/cm, which is close to that of copper. The conductive polymer may be undoped, or doped with either the addition of acceptor or p-doping agents (e.g., AsF5, Br2, I2, HClO4, etc.), or the addition of donor or n-doping agents such as by dipping the conductive polymer in THF solution of alkali metal naphthalide or by electrochemical methods. The conductive polymers can be used neat, or as blends and compounds with other conductive polymers or with commodity polymers such as polyethylene, polypropylene, polystyrene, soft PVC, poly-(methylmetacrylate), phenol-formaldehyde resins, melamineformaldehyde resins, epoxies, and thermoplastic elastomers.
  • In the next step of the process shown in FIGS. 2C-D, the conductive polymer layer is patterned using a gate mask 104 to mask selected portions of the conductive polymer layer, while exposing other portions that are subject to ultraviolet light energy exposure (shown by the downward directed arrows in FIG. 2C) from an ultraviolet energy source (not shown). The masking process can also be done with energetic electronic beam, ion beam, plasma immersion, or other processes like thermal or chemical means. Those portions 106 of the conductive polymer layer which are exposed to UV light energy or other energy are reduced to a resistive polymer (e.g., the resistivity increases by a factor of about 10 or 15 or more orders of magnitude), while the masked portion(s) 108 of the conductive polymer layer, which serve as the gate contact region, remain substantially conductive (e.g., Rs is approximately on the order of between about 10−2 to about 102 S/cm for PANI). Optionally, a conductive material such as a metal, a doped semiconductor, or a conductive polymer can be formed (e.g., deposited) in the gate contact region 108 to improve ohmic contact to the nanowires (which are described further below).
  • Subsequently, as shown in FIGS. 2E-F, a dielectric material layer 110 is applied to the conductive polymer layer. Dielectric material layer 110 functions as a gate dielectric, and can be any type of dielectric material, including organic or inorganic materials such as silicon nitride, silicon dioxide, aluminum oxide, an insulating polymer film or the like, and can be spun on, sputtered, or applied in any other manner described or referenced elsewhere herein, or otherwise known, including using ink-jet printing or micro-contact printing methods. In an embodiment, the dielectric material can be recessed in the channel area to give better coupling efficiency in the channel area. In another embodiment, dielectric material layer 110 can be a shell layer of nanowires 112 as described further below in connection with the embodiment of FIGS. 4A-C.
  • A small via 111 can be formed through the dielectric coating layer 110 to the underlying gate contact region 108 to provide electrical connectivity to the nanowires which are deposited on the dielectric coating layer. The via 111 can be formed by conventional via processing techniques such as etching, laser ablation or photochemical reaction.
  • Alternatively, the process steps described above in connection with FIGS. 2B-F can be substituted by replacing the first conductive polymer layer 102 with a gate contact or electrode (e.g., made from a metal, semiconductor, metal alloy etc.) which is patterned or formed directly onto the device substrate using standard photolithography and metal deposition methods like e-beam evaporation, sputtering, chemical vapor deposition (CVD) techniques to form a metal or semiconductor gate electrode having a thickness of between about 500 angstroms and 1 micron, for example. The gate electrode can then be coated with a suitable organic or inorganic dielectric layer and a via can be formed through the dielectric using standard via processing techniques such as etching or laser ablation. The remaining process steps can then proceed as described below in connection with the description of FIGS. 2G-J.
  • Single crystal NWs 112 which have been synthesized on a separate growth substrate are then deposited, e.g., from solution on the dielectric layer 110. In one example, p-type silicon NWs with controlled diameters were synthesized by decomposition of SiH4 and B2H6 using gold colloid particles (available through British Biocell International Ltd.) as the catalyst in a pilot production scale reactor. The growth is typically carried out at a temperature between 420-480 degrees Celsius, with a total pressure of 30 torr, a silane partial pressure of approximately 2 torr, for a period of 40 minutes. The SiH4 and B2H6 ratio can be varied to control the doping level. For example, A ratio of 6400:1 can be used in synthesizing the NWs. The resulting NWs typically had lengths of 5 um to about 100 um with a nearly mono-disperse diameter in the range from about 5 nm to about 100 nm as determined by the Au colloid catalytic particle. As synthesized the NWs have a core shell structure with a single crystalline silicon core surrounded by an amorphous silicon oxide shell of thickness of about 2 nm to about 20 nm.
  • The nanowires, after being dispersed into solution (e.g., ethanol), are assembled onto the dielectric coating layer using, for example, a fluidic flow directed alignment method to obtain an oriented NW thin film. The NW suspension is allowed to pass through a fluidic channel structure formed between a poly-dimethlysiloxane (PDMS) mold and a flat substrate surface to obtain NW arrays on the surface. The average NW space in the thin film can be controlled by varying the NW concentration in the solution and/or the total flow time. With this approach, the alignment can be readily extended over a 4-inch wafer or even larger areas by using a longer or larger flow channel mold. The nanowires may also be deposited and aligned/oriented on the dielectric layer by a variety of other means such as are disclosed in Lieber et al. U.S. Patent Application Pub. No. U.S. 2002/0130311, filed Aug. 22, 2001, and in U.S. Pat. No. 6,872,645 the entire contents of which are each incorporated by reference herein. FIG. 5A is an optical micrograph showing nanowires embedded in a conductive polymer film which are coated on a plastic substrate using a wire roding deposition process. FIG. 5B is an optical micrograph showing nanowires embedded in a conductive polymer film which are coated on a plastic substrate using a dynamic paint brushing deposition process.
  • Following nanowire deposition, a second conductive polymer layer 114 is deposited on the nanowires 112 as shown in FIG. 2H using any of the deposition methods described previously. Next, as shown with respect to FIGS. 2I-J, the second conductive polymer layer 114 is patterned to form source and drain contact regions 116, 118, respectively, in the conductive polymer layer 114 which contact regions are each in contact with at least one or more of nanowires 112. Similar to formation of gate contact region 108 in the first conductive polymer layer 102, selected regions 116, 118 of the second conductive polymer layer where the source and drain contacts are to be formed, are masked and the unexposed portions of the conductive polymer layer are exposed to UV light energy to render them highly resistive. The source and drain contact regions 116, 118 are defined by the masked portions which are shielded from UV light exposure and thus remain conductive. The source and drain regions 116, 118 optionally can then be subjected to standard photolithography or e-beam lithography processes to define metal (e.g., gold (Au)) or semiconductor contact electrodes to yield functional TFTs. Such gate, drain, or source contacts can be painted, electroplated, evaporated, sputtered, spun on, printed (e.g., using ink-jet printing methods) or applied as described or referenced elsewhere herein, or otherwise known. Although the previous embodiment disclosed the formation of a single gate contact, in other embodiments, one or more additional gate contacts, global or local, can be formed in and/or on one or more of the conductive polymer layers to enhance performance. The one or more second gates (not shown) can be coupled to, or isolated from, first gate contact region 108.
  • In an alternative embodiment of the process of NW-TFT fabrication described above, the nanowire deposition step can be modified by incorporating the nanowires into a conductive polymer film as shown with respect to FIGS. 3A-D. The nanowires may be formed as a monolayer film, a sub monolayer film, or a multi-layer film 120 as shown in FIG. 3A. The conductive polymer film 120 having the nanowires incorporated therein is then deposited on a dielectric coating layer 110′ which is applied onto the first conductive polymer layer 102′. Subsequently, as shown with respect to FIGS. 3C-D, the second conductive polymer layer having nanowires 112′ embedded therein is patterned to form source and drain contact regions 116′, 118′, respectively, in the conductive polymer layer 120. Similar to formation of gate contact region 108′ in the first conductive polymer layer 102′, source and drain regions 116′, 118′ of the second conductive polymer layer 120 are masked and the unexposed portions of the conductive polymer layer are exposed to UV light energy to render them highly resistive. The source and drain contact regions 116′, 118′ are defined by the masked portions which are shielded from UV light exposure and thus remain conductive.
  • The performance of NW-TFTs can be further improved in a number of ways by exploiting various NW core-shell structures. For example, a core-shell NW structure consisting of a single crystal semiconductor core and a high quality gate dielectric shell will greatly enhance the quality of interface between Si and oxide to improve the device performance like low leakage, low sub-threshold swing, and high surface carrier mobility, etc. Although Si NWs naturally have a core-shell structure, the thin native oxide layer is not of enough quality to withstand a high electric field. The native oxide can be replaced with a high quality silicon oxide shell generated by either controlled thermal oxidation or chemical vapor deposition. Core-shell NW structures are likely to be ideally suited for making high performance NW-TFTs on plastic since it separates all the high temperature processes, including semiconductor material synthesis and high quality gate dielectric formation, from the final device substrate. In addition, such core-shell structure can also lead to passivation of surface trapping states, resulting in further performance enhancement.
  • Second, the current back-gated NW-TFTs are relatively limited in performance due to a geometrical effect. Such a geometrical effect can be overcome by developing a more complex NW core-shell structure to include a core of single crystal semiconductor, an inner-shell of gate dielectric, and an outer-shell of conformal gate. This can be realized by depositing a layer of highly-doped amorphous silicon or other metals deposited by CVD or atomic layer deposition (ALD) around the Si/SiOx core-shell structure (described above) as the outer-gate shell.
  • Third, the performance of NW-TFTs can potentially be further improved to exceed that of single crystal materials by exploiting the quantum electronic effect in small diameter NWs. In analogy to conventional two dimensional semiconductor superlattices and 2D electron/hole gas, multi-core-shell NW structure can be envisioned to separate the dopants from the active conducting channel to achieve ultra-high mobility TFTs.
  • FIGS. 4A-D show an alternative embodiment of the invention in which NW-TFT devices are fabricated using nanowire core-shell structures. In this embodiment, a conductive polymer film 202 incorporating a plurality of core-shell nanowires 204 (shown in detail in the schematics of FIG. 4B-C) is deposited on a device substrate 200. The nanowires each comprise a nanowire core 205 made from a semiconductor (or other material, e.g., metal, conductive polymer, ceramic etc.) surrounded by a dielectric shell 207 such as an oxide layer as shown in the cross-sectional view of a single nanowire in FIG. 4C. The conductive polymer layer is then patterned as described previously to form source and drain contact regions 206, 208 respectively in the conductive layer as shown in FIG. 4C. A conformal gate electrode (not shown) can then be formed over the conductive layer above the channel region between the source and drain contacts. The oxide shell covering the ends of the nanowires optionally can be removed proximal both the source and drain contact regions of the device to improve the ohmic contact between the core-shell nanowires and the contact conductor, which can be made of metal, a doped semiconductor, or the conductive polymer material itself. The oxide shell layer can be selectively etched from the nanowires in any manner. If necessary, a photoresist material can be patterned on the nanowires to protect portions of the oxide layer on the nanowires that are not to be removed. A photolithography process can be used, for example. The nanowires can be exposed or treated with an etching source (e.g., chemical etching material, laser light, etc.) to remove unprotected portions of the oxide layer. Any type of suitable material removal process can be used. For example, reactive ion etching or other etching technique can be used. For example, the plasma power, pressure, and/or the substrate bias can be tuned such that the ion beam will be more direct towards the surface.
  • An important aspect of the as-described NW thin film concept is that the entire NW-TFT fabrication process can be performed essentially at room temperature, except for the NW synthesis step which is separate from the device fabrication. Therefore, the assembly of high performance NW-TFTs can be readily applied to low cost glass and plastic substrates. Note that in embodiments, electronic devices can be formed having any number of one or more nanowires. For example, pluralities of nanowires can be formed into a thin film, and used in electronic devices. When a plurality of nanowires are used, the nanowires can be aligned or non-aligned (e.g., randomly oriented).
  • II. EXAMPLE APPLICATIONS
  • The embodiments described herein, when applied to NW-TFT technology, enable the manufacturing of transistors with performance characteristics comparable or exceeding that of transistors fabricated from traditional single-crystal silicon on very large flexible substrates. This enables ultra-large scale, high-density electrical integration, and provides a true silicon-on-plastic technology. The potential applications of this technology, including military applications, are very broad. The NW-TFT technology described herein enables the development of a variety of unique applications, including RF communications, solar cells, smart cards, radiofrequency identification tags, detectors, sensor arrays, X-ray imagers, flexible displays (e.g., active matrix liquid crystal displays), electronics and more.
  • For example, incorporating NW-TFTs into Large Area Electronic Reflectors (LAER) enables the electronically morphing of “any” surface into a parabolic antenna for directed high gain RF transmission or reception. This is similar to making a roof top physically shaped to optimally protect a house from water while the electronic shape of the roof top would operate as a very large satellite dish. Convex shapes could be made to be electronically concave and thus increase the efficiency of the transceivers, thus reducing the power required to operate them or increase their life or range. Furthermore, the bladder of an airship (such as a blimp) can be made to operate as a very large morphing antenna aperture. Such an airship is a low cost solution for launching a high altitude electronic surveillance/communicator. Embedded TFTs that operate in RF frequencies on the surface of an airship bladder reduce the weight and increase the performance of the air ship.
  • Exemplary embodiments of the present invention have been presented. The invention is not limited to these examples. These examples are presented herein for purposes of illustration, and not limitation. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the invention.

Claims (29)

1. A process for making a transistor device, comprising:
a. providing a device substrate;
b. depositing a first conductive polymer layer on the device substrate;
c. defining one or more gate contact regions in the conductive polymer layer;
d. depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level;
e. depositing a second conductive polymer layer on the plurality of nanowires; and
f. forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.
2. The process of claim 1, further comprising aligning the nanowires substantially parallel to their long axis.
3. The process of claim 1, wherein defining one or more gate contact regions comprises masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive.
4. The process of claim 1, further comprising forming a gate dielectric layer on the first conductive polymer layer.
5. The process of claim 4, wherein the plurality of nanowires is deposited on the gate dielectric layer.
6. The process of claim 1, wherein defining the source and drain regions in the second conductive polymer layer comprises masking at least two or more portions of the second conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive.
7. The process of claim 1, wherein depositing the first and/or second conductive polymer layers comprises using a process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting.
8. The process of claim 1, further comprising depositing a metal or doped silicon in the source and drain contact regions.
9. The process of claim 1, further comprising forming a gate electrode in the gate contact region.
10. A process for making a transistor device, comprising:
a. providing a substrate;
b. depositing a conductive polymer layer incorporating a plurality of nanowires on the substrate;
c. defining source and drain contact regions in the conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain contact regions; and
d. forming a gate on the conductive polymer layer.
11. The process of claim 10, further comprising aligning the nanowires substantially parallel to their long axis.
12. The process of claim 10, wherein defining the source and drain contact regions comprises masking two or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive.
13. The process of claim 10, wherein depositing the conductive polymer layer comprises using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting.
14. The process of claim 10, further comprising depositing a metal or doped silicon in the source and drain contact regions.
15. The process of claim 10, wherein forming said gate comprises depositing a metal on a portion of said conductive polymer layer.
16. The process of claim 10, wherein the nanowires comprise a layer of oxide deposited on at least a portion of the nanowires.
17. The process of claim 16, further comprising removing a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions.
18. The process of claim 10, wherein said nanowires are formed as a monolayer film, a sub monolayer film, or a multi-layer film.
19. The process of claim 10, wherein the substrate is made from a plastic material.
20. A process for making a transistor device, comprising:
a. providing a substrate;
b. depositing a first conductive polymer layer on the substrate;
c. defining one or more gate contact regions in the first conductive polymer layer;
d. depositing a second conductive polymer layer having a plurality of nanowires incorporated therein over the first conductive polymer layer; and
e. forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.
21. The process of claim 20, further comprising aligning the nanowires substantially parallel to their long axis.
22. The process of claim 20, wherein defining the gate contact region comprises masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive.
23. The process of claim 20, wherein depositing the first and/or second conductive polymer layers comprises using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting.
24. The process of claim 20, further comprising depositing a metal or doped silicon in the gate, source and/or drain contact regions.
25. The process of claim 20, further comprising forming a gate electrode in the gate contact region.
26. The process of claim 20, wherein the nanowires comprise a layer of oxide deposited on at least a portion of the nanowires.
27. The process of claim 26, further comprising removing a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions.
28. The process of claim 20, wherein said nanowires are formed as a monolayer film, a sub monolayer film, or a multi-layer film.
29. The process of claim 20, wherein the substrate is made from a plastic material.
US12/016,701 2004-10-12 2008-01-18 Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires Abandoned US20080128688A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US61783004P true 2004-10-12 2004-10-12
US11/233,503 US7345307B2 (en) 2004-10-12 2005-09-22 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
US12/016,701 US20080128688A1 (en) 2004-10-12 2008-01-18 Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/016,701 US20080128688A1 (en) 2004-10-12 2008-01-18 Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/233,503 Division US7345307B2 (en) 2004-10-12 2005-09-22 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires

Publications (1)

Publication Number Publication Date
US20080128688A1 true US20080128688A1 (en) 2008-06-05

Family

ID=37431705

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/233,503 Expired - Fee Related US7345307B2 (en) 2004-10-12 2005-09-22 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
US12/016,701 Abandoned US20080128688A1 (en) 2004-10-12 2008-01-18 Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/233,503 Expired - Fee Related US7345307B2 (en) 2004-10-12 2005-09-22 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires

Country Status (4)

Country Link
US (2) US7345307B2 (en)
EP (1) EP1805823A2 (en)
JP (1) JP2008515654A (en)
WO (1) WO2006124055A2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080259262A1 (en) * 2007-04-20 2008-10-23 Cambrios Technologies Corporation Composite transparent conductors and methods of forming the same
US20090114541A1 (en) * 2007-10-31 2009-05-07 Postech Academy-Industry Foundation Method for Manufacturing Micro Wire, and Sensor Including the Micro Wire and Method for manufacturing the Sensor
WO2010147860A1 (en) * 2009-06-15 2010-12-23 William Marsh Rice University Graphene nanoribbons prepared from carbon nanotubes via alkali metal exposure
US20110229073A1 (en) * 2008-12-02 2011-09-22 Henning Sirringhaus Optoelectronic Devices
WO2011149991A1 (en) * 2010-05-24 2011-12-01 The Regents Of The University Of California Inorganic nanostructure-organic polymer heterostructures useful for thermoelectric devices
US8199045B1 (en) * 2009-04-13 2012-06-12 Exelis Inc. Nickel nanostrand ESD/conductive coating or composite
WO2014079532A1 (en) 2012-11-20 2014-05-30 Merck Patent Gmbh Formulation in high-purity solvent for producing electronic devices
US9449743B2 (en) 2012-01-27 2016-09-20 William Marsh Rice University Synthesis of magnetic carbon nanoribbons and magnetic functionalized carbon nanoribbons
US9493355B2 (en) 2011-09-14 2016-11-15 William Marsh Rice University Solvent-based methods for production of graphene nanoribbons
US9840418B2 (en) 2014-06-16 2017-12-12 William Marsh Rice University Production of graphene nanoplatelets by oxidative anhydrous acidic media

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110125412A1 (en) * 1998-12-17 2011-05-26 Hach Company Remote monitoring of carbon nanotube sensor
US9056783B2 (en) * 1998-12-17 2015-06-16 Hach Company System for monitoring discharges into a waste water collection system
US7454295B2 (en) 1998-12-17 2008-11-18 The Watereye Corporation Anti-terrorism water quality monitoring system
US8958917B2 (en) * 1998-12-17 2015-02-17 Hach Company Method and system for remote monitoring of fluid quality and treatment
US8920619B2 (en) 2003-03-19 2014-12-30 Hach Company Carbon nanotube sensor
AU6531600A (en) 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US7981325B2 (en) 2006-07-29 2011-07-19 Shocking Technologies, Inc. Electronic device for voltage switchable dielectric material having high aspect ratio particles
US20100038121A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US20100038119A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
KR100708644B1 (en) * 2004-02-26 2007-04-17 삼성에스디아이 주식회사 TFT, flat panel display device therewith, manufacturing method of TFT, manufacturing method of flat panel display, and manufacturing method of donor sheet
US7557433B2 (en) 2004-10-25 2009-07-07 Mccain Joseph H Microelectronic device with integrated energy source
JP4856900B2 (en) * 2005-06-13 2012-01-18 パナソニック株式会社 A method of manufacturing a field effect transistor
JP2009513368A (en) * 2005-09-23 2009-04-02 ナノシス・インコーポレイテッドNanosys, Inc. A method of doping nanostructures
US7492015B2 (en) * 2005-11-10 2009-02-17 International Business Machines Corporation Complementary carbon nanotube triple gate technology
US7923844B2 (en) 2005-11-22 2011-04-12 Shocking Technologies, Inc. Semiconductor devices including voltage switchable materials for over-voltage protection
US20100264225A1 (en) * 2005-11-22 2010-10-21 Lex Kosowsky Wireless communication device using voltage switchable dielectric material
US7692610B2 (en) * 2005-11-30 2010-04-06 Semiconductor Energy Laboratory Co., Ltd. Display device
KR20070079744A (en) * 2006-02-03 2007-08-08 삼성전자주식회사 Organic semiconductor materials using cnts enhanced their semiconducting properties, organic semiconductor thin film using the materials and organic semiconductor device employing the thin film
JP4574634B2 (en) * 2006-04-03 2010-11-04 キヤノン株式会社 Method of manufacturing a formed article comprising a silicon wire
KR101206661B1 (en) * 2006-06-02 2012-11-30 삼성전자주식회사 Organic electronic device comprising semiconductor layer and source/drain electrodes which are formed from materials of same series
TWI412079B (en) * 2006-07-28 2013-10-11 Semiconductor Energy Lab Method for manufacturing display device
US7943287B2 (en) * 2006-07-28 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device
US20080029405A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having conductive or semi-conductive organic material
WO2008023630A1 (en) * 2006-08-24 2008-02-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device
US8563431B2 (en) * 2006-08-25 2013-10-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8148259B2 (en) 2006-08-30 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP2010521058A (en) 2006-09-24 2010-06-17 ショッキング テクノロジーズ,インコーポレイテッド Step voltage method for producing a composition and dielectric material of the voltage switchable dielectric material having a response
CN101595535A (en) * 2006-09-24 2009-12-02 肖克科技有限公司 Technique for plating substrate devices using voltage switchable dielectric material and light assistance
US8018568B2 (en) 2006-10-12 2011-09-13 Cambrios Technologies Corporation Nanowire-based transparent conductors and applications thereof
US8094247B2 (en) * 2006-10-12 2012-01-10 Cambrios Technologies Corporation Nanowire-based transparent conductors and applications thereof
JP2013522814A (en) * 2010-02-24 2013-06-13 カンブリオス テクノロジーズ コーポレイション Methods for nanowire-based transparent conductors and it patterning
US20080210929A1 (en) * 2007-03-01 2008-09-04 Motorola, Inc. Organic Thin Film Transistor
KR101356238B1 (en) * 2007-03-26 2014-01-28 삼성전자주식회사 Method of manufacturing uv pattenable conductive polymer film and conductive polymer film made therefrom
WO2008144762A2 (en) * 2007-05-21 2008-11-27 Plextronics, Inc. Organic electrodes and electronic devices
WO2008144759A2 (en) * 2007-05-21 2008-11-27 Plextronics, Inc. Organic electrodes and electronic devices
KR100861131B1 (en) * 2007-05-23 2008-09-30 삼성전자주식회사 Image forming element using a conductive polymer, manufacturing method thereof, and image forming apparatus having the same
WO2009023643A1 (en) * 2007-08-13 2009-02-19 Smart Nanomaterials, Llc Nano-enhanced modularly constructed composite panel
US20090050856A1 (en) * 2007-08-20 2009-02-26 Lex Kosowsky Voltage switchable dielectric material incorporating modified high aspect ratio particles
WO2009031525A1 (en) * 2007-09-07 2009-03-12 Nec Corporation Carbon nanotube structure, and thin film transistor
JP2011500184A (en) * 2007-10-15 2011-01-06 ユニヴァルシテ カソリック デ ルーバン Drug eluting nanowire arrays
FR2925226A1 (en) * 2007-12-12 2009-06-19 Commissariat Energie Atomique Organic transistor i.e. organic FET, has nano-scale objects parallely aligned to axis connecting source and drain electrodes in organic matrix, where nano-scale objects have length lower than distance separating electrodes
US8206614B2 (en) 2008-01-18 2012-06-26 Shocking Technologies, Inc. Voltage switchable dielectric material having bonded particle constituents
JP5063500B2 (en) 2008-02-08 2012-10-31 富士通コンポーネント株式会社 Panel-type input device, a method of manufacturing a panel-type input device electronic apparatus comprising, and panel-type input device
US20090220771A1 (en) * 2008-02-12 2009-09-03 Robert Fleming Voltage switchable dielectric material with superior physical properties for structural applications
CN104282360B (en) * 2008-08-22 2017-11-03 日立化成株式会社 Photosensitive conductive film, a method of forming method, a conductive pattern of the conductive film and a conductive film substrate
KR20100035380A (en) * 2008-09-26 2010-04-05 삼성전자주식회사 Chemical sensor using thin film sensing member
CN102246246A (en) 2008-09-30 2011-11-16 肖克科技有限公司 Voltage switchable dielectric material containing conductive core shelled particles
US9208931B2 (en) 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductor-on-conductor core shelled particles
US8272123B2 (en) 2009-01-27 2012-09-25 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US9226391B2 (en) 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
US8399773B2 (en) 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
EP2412212A1 (en) 2009-03-26 2012-02-01 Shocking Technologies Inc Components having voltage switchable dielectric materials
KR20120102489A (en) 2009-04-10 2012-09-18 스미또모 가가꾸 가부시키가이샤 Metal complex and composition containing same
US9304132B2 (en) 2009-04-16 2016-04-05 President And Fellows Of Harvard College Molecular delivery with nanowires
US9224728B2 (en) 2010-02-26 2015-12-29 Littelfuse, Inc. Embedded protection against spurious electrical events
US9320135B2 (en) 2010-02-26 2016-04-19 Littelfuse, Inc. Electric discharge protection for surface mounted and embedded components
US9082622B2 (en) 2010-02-26 2015-07-14 Littelfuse, Inc. Circuit elements comprising ferroic materials
WO2012050881A2 (en) * 2010-09-29 2012-04-19 President And Fellows Of Harvard College Molecular delivery with nanowires
US8785909B2 (en) * 2012-09-27 2014-07-22 Intel Corporation Non-planar semiconductor device having channel region with low band-gap cladding layer
US8710490B2 (en) * 2012-09-27 2014-04-29 Intel Corporation Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer
US8735869B2 (en) 2012-09-27 2014-05-27 Intel Corporation Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
KR20140062570A (en) * 2012-11-12 2014-05-26 삼성전자주식회사 Channel layer for stretchable transistors
US8768271B1 (en) 2012-12-19 2014-07-01 Intel Corporation Group III-N transistors on nanoscale template structures
US9748113B2 (en) * 2015-07-30 2017-08-29 Veeco Intruments Inc. Method and apparatus for controlled dopant incorporation and activation in a chemical vapor deposition system
CN106744669B (en) * 2016-11-23 2019-01-04 宁波大学 A kind of transfer method of the single nano-wire based on waveguide device

Citations (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920078A (en) * 1996-06-20 1999-07-06 Frey; Jeffrey Optoelectronic device using indirect-bandgap semiconductor material
US5962863A (en) * 1993-09-09 1999-10-05 The United States Of America As Represented By The Secretary Of The Navy Laterally disposed nanostructures of silicon on an insulating substrate
US6256767B1 (en) * 1999-03-29 2001-07-03 Hewlett-Packard Company Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
US6274007B1 (en) * 1999-11-25 2001-08-14 Sceptre Electronics Limited Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon
US6438025B1 (en) * 1999-09-08 2002-08-20 Sergei Skarupo Magnetic memory device
US20020117659A1 (en) * 2000-12-11 2002-08-29 Lieber Charles M. Nanosensors
US6447663B1 (en) * 2000-08-01 2002-09-10 Ut-Battelle, Llc Programmable nanometer-scale electrolytic metal deposition and depletion
US20020127495A1 (en) * 2001-03-12 2002-09-12 Axel Scherer Method of fabricating nanometer-scale flowchannels and trenches with self-aligned electrodes and the structures formed by the same
US20020130311A1 (en) * 2000-08-22 2002-09-19 Lieber Charles M. Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
US20020130353A1 (en) * 1999-07-02 2002-09-19 Lieber Charles M. Nanoscopic wire-based devices, arrays, and methods of their manufacture
US6465813B2 (en) * 1998-06-16 2002-10-15 Hyundai Electronics Industries Co., Ltd. Carbon nanotube device
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
US20020173083A1 (en) * 2001-01-03 2002-11-21 International Business Machines Corporation Methodology for electrically induced selective breakdown of nanotubes
US20020175408A1 (en) * 2001-03-30 2002-11-28 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
US20030012723A1 (en) * 2001-07-10 2003-01-16 Clarke Mark S.F. Spatial localization of dispersed single walled carbon nanotubes into useful structures
US20030042562A1 (en) * 2001-08-30 2003-03-06 Carsten Giebeler Magnetoresistive device and electronic device
US20030089899A1 (en) * 2000-08-22 2003-05-15 Lieber Charles M. Nanoscale wires and related devices
US6566704B2 (en) * 2000-06-27 2003-05-20 Samsung Electronics Co., Ltd. Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US6586785B2 (en) * 2000-06-29 2003-07-01 California Institute Of Technology Aerosol silicon nanoparticles for use in semiconductor device fabrication
US20030186522A1 (en) * 2002-04-02 2003-10-02 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US20030189202A1 (en) * 2002-04-05 2003-10-09 Jun Li Nanowire devices and methods of fabrication
US6672925B2 (en) * 2001-08-17 2004-01-06 Motorola, Inc. Vacuum microelectronic device and method
US20040005258A1 (en) * 2001-12-12 2004-01-08 Fonash Stephen J. Chemical reactor templates: sacrificial layer fabrication and template use
US20040031975A1 (en) * 2002-03-18 2004-02-19 Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V., A German Corporation Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell
US20040036128A1 (en) * 2002-08-23 2004-02-26 Yuegang Zhang Multi-gate carbon nano-tube transistors
US20040061422A1 (en) * 2002-09-26 2004-04-01 International Business Machines Corporation System and method for molecular optical emission
US6740900B2 (en) * 2002-02-27 2004-05-25 Konica Corporation Organic thin-film transistor and manufacturing method for the same
US6760245B2 (en) * 2002-05-01 2004-07-06 Hewlett-Packard Development Company, L.P. Molecular wire crossbar flash memory
US6790425B1 (en) * 1999-10-27 2004-09-14 Wiliam Marsh Rice University Macroscopic ordered assembly of carbon nanotubes
US6798000B2 (en) * 2000-07-04 2004-09-28 Infineon Technologies Ag Field effect transistor
US20040213307A1 (en) * 2002-07-19 2004-10-28 President And Fellows Of Harvard College Nanoscale coherent optical components
US6815218B1 (en) * 1999-06-09 2004-11-09 Massachusetts Institute Of Technology Methods for manufacturing bioelectronic devices
US20040238887A1 (en) * 2001-07-05 2004-12-02 Fumiyuki Nihey Field-effect transistor constituting channel by carbon nano tubes
US20050064618A1 (en) * 2001-08-20 2005-03-24 Brown Simon Anthony Nanoscale electronic devices & frabrication methods
US6903717B2 (en) * 2001-09-28 2005-06-07 Hitachi, Ltd. Display device having driving circuit
US20050184641A1 (en) * 2003-05-16 2005-08-25 Armitage N. P. Flexible nanostructure electronic devices
US7051945B2 (en) * 2002-09-30 2006-05-30 Nanosys, Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US20060118768A1 (en) * 2004-12-03 2006-06-08 The Regents Of The University Of California Carbon nanotube polymer composition and devices
US7068868B1 (en) * 2002-11-12 2006-06-27 Ifos, Inc. Sensing devices based on evanescent optical coupling
US20070158642A1 (en) * 2003-12-19 2007-07-12 Regents Of The University Of California Active electronic devices with nanowire composite components
US20090146134A1 (en) * 2004-08-27 2009-06-11 Xiang-Zheng Bo Semiconductive percolating networks

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004016511A1 (en) * 2002-08-14 2004-02-26 International Molded Packaging Corporation Latchable container system
AU2003268487A1 (en) * 2002-09-05 2004-03-29 Nanosys, Inc. Nanocomposites
CA2499377A1 (en) * 2002-09-24 2004-04-08 E. I. Du Pont De Nemours And Company Water dispersible polythiophenes made with polymeric acid colloids
WO2004032191A2 (en) * 2002-09-30 2004-04-15 Nanosys, Inc. Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
TWI309845B (en) * 2002-09-30 2009-05-11 Nanosys Inc Large-area nanoenabled macroelectronic substrates and uses therefor
JP2004247716A (en) * 2003-01-23 2004-09-02 Mitsubishi Chemicals Corp Method for manufacturing laminated body
CN1863954B (en) * 2003-08-04 2013-07-31 纳米系统公司 System and process for producing nanowire composites and electronic substrates therefrom

Patent Citations (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5962863A (en) * 1993-09-09 1999-10-05 The United States Of America As Represented By The Secretary Of The Navy Laterally disposed nanostructures of silicon on an insulating substrate
US5920078A (en) * 1996-06-20 1999-07-06 Frey; Jeffrey Optoelectronic device using indirect-bandgap semiconductor material
US6465813B2 (en) * 1998-06-16 2002-10-15 Hyundai Electronics Industries Co., Ltd. Carbon nanotube device
US6256767B1 (en) * 1999-03-29 2001-07-03 Hewlett-Packard Company Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
US6815218B1 (en) * 1999-06-09 2004-11-09 Massachusetts Institute Of Technology Methods for manufacturing bioelectronic devices
US20020130353A1 (en) * 1999-07-02 2002-09-19 Lieber Charles M. Nanoscopic wire-based devices, arrays, and methods of their manufacture
US6438025B1 (en) * 1999-09-08 2002-08-20 Sergei Skarupo Magnetic memory device
US6790425B1 (en) * 1999-10-27 2004-09-14 Wiliam Marsh Rice University Macroscopic ordered assembly of carbon nanotubes
US6274007B1 (en) * 1999-11-25 2001-08-14 Sceptre Electronics Limited Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon
US6566704B2 (en) * 2000-06-27 2003-05-20 Samsung Electronics Co., Ltd. Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US6586785B2 (en) * 2000-06-29 2003-07-01 California Institute Of Technology Aerosol silicon nanoparticles for use in semiconductor device fabrication
US6798000B2 (en) * 2000-07-04 2004-09-28 Infineon Technologies Ag Field effect transistor
US6447663B1 (en) * 2000-08-01 2002-09-10 Ut-Battelle, Llc Programmable nanometer-scale electrolytic metal deposition and depletion
US20020130311A1 (en) * 2000-08-22 2002-09-19 Lieber Charles M. Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
US20030089899A1 (en) * 2000-08-22 2003-05-15 Lieber Charles M. Nanoscale wires and related devices
US20020117659A1 (en) * 2000-12-11 2002-08-29 Lieber Charles M. Nanosensors
US20020173083A1 (en) * 2001-01-03 2002-11-21 International Business Machines Corporation Methodology for electrically induced selective breakdown of nanotubes
US6706566B2 (en) * 2001-01-03 2004-03-16 International Business Machines Corporation Methodology for electrically induced selective breakdown of nanotubes
US20020127495A1 (en) * 2001-03-12 2002-09-12 Axel Scherer Method of fabricating nanometer-scale flowchannels and trenches with self-aligned electrodes and the structures formed by the same
US20020175408A1 (en) * 2001-03-30 2002-11-28 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
US6882051B2 (en) * 2001-03-30 2005-04-19 The Regents Of The University Of California Nanowires, nanostructures and devices fabricated therefrom
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
US20040238887A1 (en) * 2001-07-05 2004-12-02 Fumiyuki Nihey Field-effect transistor constituting channel by carbon nano tubes
US20030012723A1 (en) * 2001-07-10 2003-01-16 Clarke Mark S.F. Spatial localization of dispersed single walled carbon nanotubes into useful structures
US6672925B2 (en) * 2001-08-17 2004-01-06 Motorola, Inc. Vacuum microelectronic device and method
US20050064618A1 (en) * 2001-08-20 2005-03-24 Brown Simon Anthony Nanoscale electronic devices & frabrication methods
US20030042562A1 (en) * 2001-08-30 2003-03-06 Carsten Giebeler Magnetoresistive device and electronic device
US6903717B2 (en) * 2001-09-28 2005-06-07 Hitachi, Ltd. Display device having driving circuit
US20040005258A1 (en) * 2001-12-12 2004-01-08 Fonash Stephen J. Chemical reactor templates: sacrificial layer fabrication and template use
US6740900B2 (en) * 2002-02-27 2004-05-25 Konica Corporation Organic thin-film transistor and manufacturing method for the same
US20040031975A1 (en) * 2002-03-18 2004-02-19 Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V., A German Corporation Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US20030186522A1 (en) * 2002-04-02 2003-10-02 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US20030189202A1 (en) * 2002-04-05 2003-10-09 Jun Li Nanowire devices and methods of fabrication
US6760245B2 (en) * 2002-05-01 2004-07-06 Hewlett-Packard Development Company, L.P. Molecular wire crossbar flash memory
US20040213307A1 (en) * 2002-07-19 2004-10-28 President And Fellows Of Harvard College Nanoscale coherent optical components
US20040036128A1 (en) * 2002-08-23 2004-02-26 Yuegang Zhang Multi-gate carbon nano-tube transistors
US20040036126A1 (en) * 2002-08-23 2004-02-26 Chau Robert S. Tri-gate devices and methods of fabrication
US20040061422A1 (en) * 2002-09-26 2004-04-01 International Business Machines Corporation System and method for molecular optical emission
US7051945B2 (en) * 2002-09-30 2006-05-30 Nanosys, Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US7068868B1 (en) * 2002-11-12 2006-06-27 Ifos, Inc. Sensing devices based on evanescent optical coupling
US20050184641A1 (en) * 2003-05-16 2005-08-25 Armitage N. P. Flexible nanostructure electronic devices
US20070158642A1 (en) * 2003-12-19 2007-07-12 Regents Of The University Of California Active electronic devices with nanowire composite components
US20090146134A1 (en) * 2004-08-27 2009-06-11 Xiang-Zheng Bo Semiconductive percolating networks
US20060118768A1 (en) * 2004-12-03 2006-06-08 The Regents Of The University Of California Carbon nanotube polymer composition and devices

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018563B2 (en) * 2007-04-20 2011-09-13 Cambrios Technologies Corporation Composite transparent conductors and methods of forming the same
US20080259262A1 (en) * 2007-04-20 2008-10-23 Cambrios Technologies Corporation Composite transparent conductors and methods of forming the same
US20120033367A1 (en) * 2007-04-20 2012-02-09 Cambrios Technologies Corporation Composite transparent conductors and methods of forming the same
US10244637B2 (en) * 2007-04-20 2019-03-26 Cambrios Film Solutions Corporation Composite transparent conductors and methods of forming the same
US20090114541A1 (en) * 2007-10-31 2009-05-07 Postech Academy-Industry Foundation Method for Manufacturing Micro Wire, and Sensor Including the Micro Wire and Method for manufacturing the Sensor
US8647490B2 (en) * 2007-10-31 2014-02-11 Postech Academy-Industry Foundation Method for manufacturing carbon nanotube containing conductive micro wire and sensor including the micro wire
US9257666B2 (en) * 2008-12-02 2016-02-09 Cambridge Enterprise Limited Optoelectronic devices
US20110229073A1 (en) * 2008-12-02 2011-09-22 Henning Sirringhaus Optoelectronic Devices
US8199045B1 (en) * 2009-04-13 2012-06-12 Exelis Inc. Nickel nanostrand ESD/conductive coating or composite
WO2010147860A1 (en) * 2009-06-15 2010-12-23 William Marsh Rice University Graphene nanoribbons prepared from carbon nanotubes via alkali metal exposure
US8992881B2 (en) 2009-06-15 2015-03-31 William Marsh Rice University Graphene nanoribbons prepared from carbon nanotubes via alkali metal exposure
US20130084464A1 (en) * 2010-05-24 2013-04-04 The Regents Of The University Of California Inorganic Nanostructure-Organic Polymer Heterostructures Useful for Thermoelectric Devices
WO2011149991A1 (en) * 2010-05-24 2011-12-01 The Regents Of The University Of California Inorganic nanostructure-organic polymer heterostructures useful for thermoelectric devices
US9831008B2 (en) * 2010-05-24 2017-11-28 The Regents Of The University Of California Inorganic nanostructure-organic polymer heterostructures useful for thermoelectric devices
US9493355B2 (en) 2011-09-14 2016-11-15 William Marsh Rice University Solvent-based methods for production of graphene nanoribbons
US9449743B2 (en) 2012-01-27 2016-09-20 William Marsh Rice University Synthesis of magnetic carbon nanoribbons and magnetic functionalized carbon nanoribbons
WO2014079532A1 (en) 2012-11-20 2014-05-30 Merck Patent Gmbh Formulation in high-purity solvent for producing electronic devices
US9840418B2 (en) 2014-06-16 2017-12-12 William Marsh Rice University Production of graphene nanoplatelets by oxidative anhydrous acidic media

Also Published As

Publication number Publication date
WO2006124055A3 (en) 2007-04-19
EP1805823A2 (en) 2007-07-11
US7345307B2 (en) 2008-03-18
JP2008515654A (en) 2008-05-15
WO2006124055A2 (en) 2006-11-23
US20060214156A1 (en) 2006-09-28

Similar Documents

Publication Publication Date Title
Briseno et al. Introducing organic nanowire transistors
US7897960B2 (en) Self-aligned nanotube field effect transistor
KR101182883B1 (en) Field-effect transistor
Duan et al. High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Jariwala et al. Mixed-dimensional van der Waals heterostructures
US7105428B2 (en) Systems and methods for nanowire growth and harvesting
US8242025B2 (en) Method for producing semiconductor chip, and field effect transistor and method for manufacturing same
US8003453B2 (en) Self-aligned process for nanotube/nanowire FETs
US7691666B2 (en) Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US6891191B2 (en) Organic semiconductor devices and methods of fabrication
US6770905B1 (en) Implantation for the formation of CuX layer in an organic memory device
EP1487028A1 (en) Field effect transistor and method for manufacturing the same
US7517718B2 (en) Method for fabricating an inorganic nanocomposite
EP1411554A1 (en) Field-effect transistor constituting channel by carbon nano tubes
US20110248315A1 (en) Structured pillar electrodes
US7582534B2 (en) Chemical doping of nano-components
US6913984B2 (en) Method of manufacturing memory with nano dots
US7405129B2 (en) Device comprising doped nano-component and method of forming the device
US7517719B2 (en) Method for fabricating a semiconductor element from a dispersion of semiconductor particles
CN1863954B (en) System and process for producing nanowire composites and electronic substrates therefrom
US7586130B2 (en) Vertical field effect transistor using linear structure as a channel region and method for fabricating the same
US7361929B2 (en) Field-effect transistors with weakly coupled layered inorganic semiconductors
US7132678B2 (en) Electronic device including a self-assembled monolayer, and a method of fabricating the same
JP5095068B2 (en) Manufacturing method of a thin film transistor device active layer
US8168964B2 (en) Semiconductor device using graphene and method of manufacturing the same