YU38202A - Metode obrazovanja silikonske nanostrukture, snopa silikonskih kvantnih žica i uređaja zasnovanih na njima - Google Patents
Metode obrazovanja silikonske nanostrukture, snopa silikonskih kvantnih žica i uređaja zasnovanih na njimaInfo
- Publication number
- YU38202A YU38202A YU38202A YUP38202A YU38202A YU 38202 A YU38202 A YU 38202A YU 38202 A YU38202 A YU 38202A YU P38202 A YUP38202 A YU P38202A YU 38202 A YU38202 A YU 38202A
- Authority
- YU
- Yugoslavia
- Prior art keywords
- silicon
- relief
- wave
- ion
- quantum wire
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract 12
- 229910052710 silicon Inorganic materials 0.000 title abstract 12
- 239000010703 silicon Substances 0.000 title abstract 12
- 230000015572 biosynthetic process Effects 0.000 title abstract 3
- 239000002086 nanomaterial Substances 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 2
- 239000012212 insulator Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 2
- 230000035515 penetration Effects 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 1
- -1 nitrogen molecular ions Chemical class 0.000 abstract 1
- 230000005693 optoelectronics Effects 0.000 abstract 1
- 230000000737 periodic effect Effects 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/125—Quantum wire structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Nanotechnology (AREA)
- Health & Medical Sciences (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Toxicology (AREA)
- Physical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Metoda obrazovanja silikonske nanostrukture, snopa silikonskih kvantnih zica i uredaja zasnovanih na njima imaju za novost to sto se silikonska povrsina spateruje ujednacenim tokom jona molekulskog zaota u ultra visokom vakuumu tako da se obrazuje periodicni talasasti reljef, gde je talasni front pomenutog reljefa orijentisan u pravcu upadne ravni jonskog snopa. Energije jona, upadnog ugla jonskog snopa u odnosu na povrsinu materijala, temperature pomenutog silikonskog sloja, dubine obrazovanja talasastog reljefa, visine talasastog reljefa i dometa jonskog prodiranja u silikon se utvrduju na osnovu odabrane talasne duzine periodicnog talasastog reljefa u opsegu od 9 nm do 120 nm. Pozicioniranje maske od nitrida sadrzi prozor sa visecim ivicama, koje vise iznad silikonske povrsine preko oblasti za spaterovanje i spaterovanje silikonske povrsine kroz pomenuti prozor. Pre spaterovanja se uklanjaju bilo kakve necistoce iz povrsine silikonskog sloja na kojoj treba da se obrazuje talastasti reljef. Odabir debljine silikonskog sloja se vrsi tako da bude veci od zbira dubine obrazovanja talasastog reljefa, visine talastastog reljefa i dometa jonskog prodiranja. Za vreme spaterovanja dolazi do detektovanja signala sekundarne jonske emisije iz izolatorskog sloja materijala silikon-na-izolatoru i zaustavljanje spaterovanja kad vrednost detektovanog signala dostigne prethodno odredenu granicnu vrednost. Nanostrukture mogu biti upotrrebljene u optoelektronskim i nanoelektronskim uredajima, kao sto je FET.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU99124768/28A RU2173003C2 (ru) | 1999-11-25 | 1999-11-25 | Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств |
Publications (1)
Publication Number | Publication Date |
---|---|
YU38202A true YU38202A (sh) | 2006-08-17 |
Family
ID=20227346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
YU38202A YU38202A (sh) | 1999-11-25 | 2002-05-24 | Metode obrazovanja silikonske nanostrukture, snopa silikonskih kvantnih žica i uređaja zasnovanih na njima |
Country Status (23)
Country | Link |
---|---|
US (1) | US6274007B1 (sh) |
EP (1) | EP1104011A1 (sh) |
JP (1) | JP2001156050A (sh) |
KR (1) | KR20020069195A (sh) |
CN (1) | CN1399791A (sh) |
AU (1) | AU7547400A (sh) |
BG (1) | BG106739A (sh) |
BR (1) | BR0016095A (sh) |
CA (1) | CA2392307A1 (sh) |
CZ (1) | CZ20021824A3 (sh) |
EE (1) | EE200200261A (sh) |
HR (1) | HRP20020459A2 (sh) |
HU (1) | HUP0203517A2 (sh) |
IL (1) | IL149832A0 (sh) |
IS (1) | IS6393A (sh) |
MX (1) | MXPA02005281A (sh) |
NO (1) | NO20022427L (sh) |
PL (1) | PL355890A1 (sh) |
RU (1) | RU2173003C2 (sh) |
SK (1) | SK7442002A3 (sh) |
WO (1) | WO2001039259A1 (sh) |
YU (1) | YU38202A (sh) |
ZA (1) | ZA200204822B (sh) |
Families Citing this family (105)
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RU2141699C1 (ru) | 1997-09-30 | 1999-11-20 | Закрытое акционерное общество Центр "Анализ Веществ" | Способ формирования твердотельных наноструктур |
-
1999
- 1999-11-25 RU RU99124768/28A patent/RU2173003C2/ru not_active IP Right Cessation
-
2000
- 2000-03-14 US US09/525,722 patent/US6274007B1/en not_active Expired - Fee Related
- 2000-03-21 EP EP00302277A patent/EP1104011A1/en not_active Withdrawn
- 2000-03-22 JP JP2000079824A patent/JP2001156050A/ja active Pending
- 2000-10-02 IL IL14983200A patent/IL149832A0/xx unknown
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- 2000-10-02 SK SK744-2002A patent/SK7442002A3/sk not_active Application Discontinuation
- 2000-10-02 AU AU75474/00A patent/AU7547400A/en not_active Abandoned
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- 2000-10-02 KR KR1020027006725A patent/KR20020069195A/ko not_active Application Discontinuation
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- 2000-10-02 CN CN00816289A patent/CN1399791A/zh active Pending
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- 2000-10-02 CA CA002392307A patent/CA2392307A1/en not_active Abandoned
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-
2002
- 2002-05-22 NO NO20022427A patent/NO20022427L/no not_active Application Discontinuation
- 2002-05-24 IS IS6393A patent/IS6393A/is unknown
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Also Published As
Publication number | Publication date |
---|---|
WO2001039259A1 (en) | 2001-05-31 |
AU7547400A (en) | 2001-06-04 |
HRP20020459A2 (en) | 2005-10-31 |
PL355890A1 (en) | 2004-05-31 |
IL149832A0 (en) | 2002-11-10 |
RU2173003C2 (ru) | 2001-08-27 |
BR0016095A (pt) | 2004-03-23 |
ZA200204822B (en) | 2003-11-26 |
NO20022427L (no) | 2002-06-25 |
SK7442002A3 (en) | 2003-05-02 |
CN1399791A (zh) | 2003-02-26 |
CZ20021824A3 (cs) | 2004-10-13 |
MXPA02005281A (es) | 2006-02-10 |
KR20020069195A (ko) | 2002-08-29 |
JP2001156050A (ja) | 2001-06-08 |
IS6393A (is) | 2002-05-24 |
CA2392307A1 (en) | 2001-05-31 |
EE200200261A (et) | 2003-08-15 |
NO20022427D0 (no) | 2002-05-22 |
HUP0203517A2 (en) | 2003-07-28 |
BG106739A (en) | 2003-08-29 |
EP1104011A1 (en) | 2001-05-30 |
US6274007B1 (en) | 2001-08-14 |
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