SK7442002A3 - Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon - Google Patents

Abstract

A process for controllably forming silicon nanostructures such as a silicon quantum wire array. A silicon surface is sputtered by a uniform flow of nitrogen molecular ions in an ultrahigh vacuum so as to form a periodic wave-like relief in which the troughs of said relief are level with the silicon-insulator border of the SOI material. The ion energy, the ion incidence angle to the surface of said material, the temperature of the silicon layer, the formation depth of the wave-like relief, the height of said wave-like relief and the ion penetration range into silicon are all determined on the basis of a selected wavelength of the wave-like relief in the range 9 nm to 120 nm. A silicon nitride mask having pendant edges is used to define the area of the silicon surface on which the array is formed. Impurities are removed from the silicon surface within the mask window prior to sputtering. For the purpose of forming a silicon quantum wire array, the thickness of the SOI silicon layer is selected to be greater than the sum of said formation depth, said height and said ion penetration range, the fabrication of the silicon wires being controlled by a threshold value of a secondary ion emission signal from the SOI insulator. The nanostructure may be employed in optoelectronic and nanoelectonic devices such as a FET. <IMAGE>

Description

A method of forming a silicon nano-structure and an apparatus for performing the method.

Technical field

The invention relates to a method of forming a silicon nanostructure and to an apparatus for carrying out the method.

BACKGROUND OF THE INVENTION

According to the known method of forming silicon quantum wires with a cross-section of 10x15 nm ² embedded in silicon dioxide, implantation of low energy oxygen ions into silicon, electron beam lithography and chemical wet etching followed by high temperature annealing in an inert environment are utilized. The result is the formation of silicon quantum conductors embedded in silica in the middle of the lower V-grooves, such as those disclosed in Y. Ishikawa, N. Shibata, F. Fukatsu; "Fabrication of [110] -aligned Si quantum wires embedded in _SiO2 by low-energy oxygen implantation" Preparation of [110] silicon quantum wires -usporiadaných stored into _SiO2 by implantation of oxygen at low energy, Nuclear Instruments and Methods in Physics Research B, 1999, V. 147, p. 304-309, Elsevier Science Ltd.) [1]. However, this known method has some disadvantages. The use of electron beam lithography and chemical wet etching in forming V-grooves on a silicon surface limits the density of the element in the building and reduces wire yield. The absence of in situ process control further reduces the yield

-2vodičov. The low conductor density prevents the use of conductors for nano-electronic devices of a type where charged particle interaction in adjacent conductors is important. The previously published work, co-authored by the present inventors, is the basis for the method of creating wave-ordered-structures (WOS) on silicon and especially SOI. The method includes the steps of sputtering a SOI silicon layer with a molecular nitrogen ion probe, and scanning to a raster pattern under very high vacuum to form a periodic wavelength relief in a nano-scale (WOS). The wave front of the relief in the nanometer is in the direction of the ion impact. The method includes detecting the secondary ion emission signal from the SOI isolator and terminating the blasting when the signal reaches a predetermined value. This work also reports the dependence of WOS formation on the energy of ions E, the angle of incidence of ions versus the normal surface and temperature T of the SOI sample. The work also identifies the characteristics of the embossing process, especially the depth of blasting D _m , corresponding to the onset of intense growth of WOS, and discusses the dependence of D _m on E, Θ, T and WOS wavelength λ. The work further indicates that the thickness of the silicon SOI D _B should not be less than the blasting depth at which a stable WOS of the desired wavelength is formed (this depth being equal to the embossing depth, hereinafter referred to as _DF ). (VK Smirnov,

D.S. Kibalov, S.A. Krivelevich, P.A. Lepshin, E.V. Potapov,

R.A. Yankov, W. Skorupa, V.V. Makarov, A.B. Danilin; Waveformed structures formed by SOI wafers by reactive ion beams

Wave-like structures formed on SOI plates by reactive ion beams, Nuclear Instruments and Methods in Physics Research B, 1999, V. 147, p. Elsevier, 310-315

Science Ltd.) [2]. Another work in which one was involved

-3 of the present inventors, describes a process of annealing material of the type described in [2] in an inert environment at a temperature of 1000 ° C for one hour and the resulting internal WOS structure at the silicon-SOI insulator interface (VK Smirnov, AB) Danilin; Nano-scale wave-ordered structures on SOI nano-scale, Proceedings of the NATO Advanced Research Workshop Perspective, science and technology for novel silicon on insulator devices, edited by PIF Hemment, 1999, Elsevier Science (3). Another work, in which one of the authors of the present invention, describes the dependence of the thickness of the silicon nitride (Si 3 _{N 4} ) D _N layer on the ions energy E, the angle of impact of the ions on the surface and annealing at high temperature (900 - 1100 ° C for one hour) . Annealing has no effect on D _N , but maximizes the sharpness of the Si / Si ₃ N ₄ interface. As shown in this work, D _N is consistent with the ions penetration of ions into silicon R, which, as determined, is a linear function of E for the same energy range as that used for WOS formation. Based on the data given in the paper, the dependence of R on E can be expressed as:

R (nm) = 1.5 E (keV) + 4 (1) (VI Bachurin, AB Churilov, EV Potapov, VK Smirnov, VV Makarov and AB Danilin; Formation of Thin Silicon Nitride Layers on Si by Low Energy N ₂ ⁺ Ion Bombardment of thin silicon layers on the Si ion bombardment N ⁺ ₂ low energy, Nuclear Instruments and Methods in Physics Research B, 1999, v 147, pp. 316-319) [4]. The above work [2], [3] and [4] together describe the basic method for creating a silicon quantum wire array. The basic advantage of using a silicon quantum array of conductors lies in the comparison with the use of separate conductors in nano-electronic

-4a optoelectronic devices, in particular in increasing the gain and amplification of the signal-to-noise ratio in the current characteristic, and also in providing the potential for new field-based device capabilities due to the interaction of charged particles in adjacent quantum conductors. There are a number of drawbacks to the basic method outlined in [2], [3] and [4]. The work [2] does not deal with the question whether the wavelength WOS λ changes with increasing the blasting depth from D _m to D _F or whether there is any internal relation between D _m and D _F. The present invention recognizes that the process characteristics should be related to the final WOS structure developed at a depth D _F rather than a depth D _m as discussed in the work [2]. In addition, the work [2] does not address the question of whether there are domain limits at the plane (E, θ) at which WOS formation occurs. These working limitations, described in [2], [3] and [4], mean that the desired thickness of the silicon SOI layer cannot generally be predetermined from the relationships between the various parameters discussed in these works. In addition, it is not possible to predetermine the basic parameters for controlling the blasting process (ion energy E, ion impact angle Θ and SOI temperature T). For the isolation of adjacent silicon wires in the WOS formed in the SOI, it is also important to ensure that the WOS relief grooves coincide exactly with the edge between the silicon SOI layer and the SOI insulator layer. Work [2] states that the secondary ion emission signal can be used to terminate the blasting process, but it does not find any way to predetermine the signal value that corresponds to the insulation of the silicon conductors. Thus, the previously published work does not provide a general method that would allow for a sufficiently reliable creation of WOS so that the WOS grooves coincide with the SOI boundary between the silicon and the insulator, thereby creating an array of insulated silicon conductors. In addition, it is

For practical reasons when using this process together with silicon-based nano-electronic and optoelectronic technology, it is necessary to ensure the formation of a nano-structure field on a specified micro-surface area in order to obtain a suitable structure, for example in the form of two insulated silicon pads . However, the work previously published does not address the question of whether procedures such as lithography can be used for this purpose or, if possible, masking layers, or whatever, could be used. The present inventors have also determined that the WOS formation process is highly sensitive to the presence of impurities on the surface of the SOI, particularly the presence of silica, which disrupts the flat area of the WOS relief. As is known, a thin layer of silica is always present on the surface of the exposed silicon. All of the above disadvantages are one way or another associated with the possibility of controlling the WOS creation process for practical purposes. It is known that nano-electronic devices contain silicon inserts connected by a 20 nm diameter silicon channel (the so-called "quantum point"), a 40 nm thick insulating layer that covers the inserts surface and channel, and an electrode located on the surface of the insulator layer. Silicon contact inserts and channel are formed in a silicon layer of SOI material (E. Leobandung, L. Guo, Y. Wang, S. Chou; "Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperature over 100K -" Observation quantum effects and coulomb blockade in quantum-point transistors at temperatures above 100K, Applied Physics Letters, V. 67, no.

7, 1995, p. 938-940, American Institute of Physics, 1995) [5]. The disadvantages of this known device lie in the absence of a channel array and low device gain, since the small dimensions of the device are close to the limitations of micro-lithography

-6postupov; this means that there is a low reproducibility of operating results. There is also another quantum-wire based FET device containing silicon inserts connected by seven linear silicon channels with a rectangular diameter of 86x100 nm ² . The silicon channels are coated with a 30 nm layer of silica. Above the group of these channels is located the electrode input. This device is prepared using SOI material (JP Colinge, X. Baie, V. Bayot, E. Grivei; &quot; A Silicon-On-Insulator Quantum Wire - &quot; No. 1, 1996, pp. 49-51, Elsevier Science Ltd. 1996) [6].

A disadvantage of this known device is that it is impossible to form silicon channels at a distance equal to the channel size due to the limitation of the known lithographic methods used to prepare the device. References to the various works above illustrate how a silicon quantum conductor field can be prepared in special experimental cases. It is an object of the present invention to overcome the shortcomings of the prior art and, by generalizing particular experimental processes, to create quantum wires with predetermined dimensions, efficiently control the process and integrate a silicon quantum wire array into useful devices, e.g. to create a channel array in FET.

SUMMARY OF THE INVENTION

The drawbacks of the prior art are substantially eliminated and the object of the invention is met by the method of forming the silicon nano-structure according to the invention, which is based on the fact that the silicon surface is blasted by a uniform ion flux

-7molecular nitrogen in a very high vacuum to form a periodic wavy relief whose wave face is oriented in the direction of the ion impact plane, wherein the desired wavelength of the periodic wavelength in the range of 9 nm to 120 nm is selected before blasting and determined according to the wavelength chosen ion energy, the angle of incidence of ions on the surface of said material, the temperature of said silicone layer, the depth of formation of said corrugated relief, the height of said corrugated relief, and the ions penetration of ions into the silicon. According to a preferred embodiment, the ion energy, the angle of incidence of the ions, the temperature of the silicon, the depth and height of the wavy relief are determined based on the relation of the ion energy, the angle of incidence of the ions, the temperature of the silicon, the depth and the height of the wavelength. ions are determined from ion energy. Preferably, prior to blasting, a silicon nitride mask comprising a hinge edge window is deposited on the blasting surface onto the silicon surface, and blasting of said silicon surface is performed through said window. Likewise, preferably before deburring, all impurities are removed from the surface of said silicon layer to form said corrugated relief. According to preferred embodiments, after blasting, the material with said relief is annealed in an inert environment, preferably the material is annealed at a temperature of between 1000 and 1200 C for at least one hour, blasting with a uniform molecular nitrogen ion flux is preferably applied to a silicone nano-structure containing silicon quantum conductor array, silicon includes a silicon layer of insulating silicon material, wherein the thickness of the silicon layer is selected to be greater than the sum of the wavy embossed depth, the wavy embossed height

Preferably, during the blasting, the secondary ion emission signal is sensed from the layer of insulating silicon material, and the blasting is terminated when the sensed signal reaches a predetermined threshold, preferably the secondary ion emission signal threshold is selected, at which the signal exceeds the average background value by a difference equal to the height between the peaks of the noise component of the signal. The apparatus for performing a method of forming a silicon nano-structure comprises a quantum conductor array formed in an optoelectronic device by blasting a silicone nano-structure comprising a silicon quantum conductor array with a uniform molecular nitrogen ion flux, the silicon comprising a silicon layer of silicon insulating material the sum of the generated wavelength, wave height and ion penetration range, or preferably comprises a quantum conductor field formed in an electronic device by blasting a silicone nano-structure containing a silicon quantum conductor field with a uniform molecular nitrogen ion flux, the silicon including silicon material the thickness of the silicon layer is greater than the sum of the depth of the wavy relief formed, the height of the wavy relief and the ion penetration range. Preferably, the apparatus for performing the silicon nanostructure forming method of the silicon substrate, joined by a silicon quantum conductor array, includes an insulator layer disposed on the quantum conductor array and an electrode disposed on the insulator. The apparatus for introducing the method consists of a very high vacuum vacuum chamber, a connected sample introduction device, an ion micro-beam column with adjustable ion energy and an ion probe position on the sample surface, an electron

-9the handle, the sample holder, which can be adjusted, rotated and rotated, and equipped with a temperature change and control device, a secondary electron detector and a secondary ion mass analyzer. A suitable instrument is known in the art as a high performance surface analysis instrument based on a number of methods. The invention overcomes the drawbacks of the prior art by allowing process control on the basis of a single parameter, namely the desired field period (wavelength), which then controls all the relevant process parameters.

BRIEF DESCRIPTION OF THE DRAWINGS

The method of forming a silicon nano-structure and apparatus for carrying out the method according to the invention are further explained in the drawings, in which Fig. 1A shows a schematic perspective view of an initial SOI structure including a silicon nitride mask for use in the invention; Fig. 1B shows a schematic perspective view of the final SOI structure after applying the method of the invention to the original structure of Fig. 1A; FIG. 1C is a graph illustrating the manner in which the secondary ion emission signal is used to control the method of the present invention; Fig. 1D shows a cross-sectional view of a substantially enlarged portion of the shot-blasted structure of Fig. 1B (detail A of Fig. 1B); FIG. 1E is a graph illustrating the relationship between ion incidence angle, ion energy, and WOS wavelength constructed in accordance with the present invention; FIG. 1F is a graph illustrating how the WOS wavelength produced according to the invention varies with the temperature of the SOI material for different ion energies; 2A to 2D

- 10 are schematic plan views of a SOI structure illustrating an embodiment of a FET device according to the present invention; and Fig. 3 is a schematic perspective view illustrating a FET channel structure in the form of a silicon nano-structural array formed in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Fig. 1A shows an example of an initial SOI structure for use according to the invention comprising a silicon substrate 5, a silicon dioxide insulating layer 4, a silicon layer 3 in which quantum conductors are to be formed, a silicon dioxide thin layer formed on top of the silicon layer 3, and a silicon nitride masking layer formed on top of a thin layer of silicon dioxide 2. FIG. IB shows a blasting structure according to the invention, comprising a silicon substrate 5 and an insulating layer of silica 4 as in Figure 1A, and in which the silicon layer 3 in Figure 1A has been modified by blasting so as to mask the masking layer 1 of FIG. 1A has left the silicon layer 6 and, by means of the blasting process, to form a field of silicon nano-structure 7 in the area left for exposure by the masking layer 7. The arrows indicate the flow direction of the N ₂ ⁺ ions during the blasting. The basic blasting process to create WOS is described in [2]. As shown in this work, the focused ion beam is scanned in the form of a grid on the surface of the SOI material. Fig. 1D shows an example of a cross-section of a silicon nano-structure formed by the blasting process of the present invention comprising regions of amorphous silicon nitride 8, regions of a mixture of amorphous silicon and silicon nitride 9, regions of silicon oxynitride 10

Figure 11 refers to the following parameters relating to the SOI material, the WOS structure, and the WOS formation process:

Db is the initial thickness of the silicon layer 3 of the SOI material.

- D _F is the embossing depth (ie, the minimum depth of the material which is blasted from the original surface of the silicon layer 4 to the WOS ridge to obtain a stable WOS, where the "blasted depth is the vertical distance from the original silicon surface to the WOS top).

- H is the height of the stabilized relief WOS, i. the vertical distance between the ridge of the wave and the nearest lowest point of the wave (twice the wave amplitude).

- R is the ions penetration of ions into silicon for a given ion energy.

In particular, the present invention is concerned with the control of the blasting process to allow reliable formation of the desired nano-structure of silicon with predetermined parameters. Further investigation of the WOS formation process by the inventors led to the following conclusions:

a) The wavelength WOS λ remains constant from the initial onset of WOS formation at the blasting depth D _{m to} the stabilization of the WOS structure at the blasting depth D _F (embossing depth) and then to continued blasting to depths several times D _F.

b) The height of the relief increases linearly with time from depth D _m to depth D _{F /,} whereby the value of H reaches at depth D _F and remains constant during the blasting. This means that the shape and dimensions of the WOS remain substantially constant under continued sputtering beyond D _F, however the position of the WOS on the SOI material migrates in a direction opposite to the direction of ion incidence (dashed line 13 in Fig. 1D shows the position of the WOS at the time when the the blasting depth is equal to D _F , while the main drawing shows the structure later, after the blasting).

c) Df is connected to D _m according to the equation: D _F = 1.5 D _m

d) D _F is associated with the wavelength λ WOS according to the equation:

D _f (nm) = 1.316 (λ (nm) - 9) (2) for λ in the range of 9 nm to 120 nm.

(e) H is proportional to λ, and this relationship varies with the angle of incidence of the ion beam Θ, eg:

H = 0.26 λ for 41 = 41 ’ H = 0.25 λ for = 43 ° H = 0.23 λ for = 45 ° H = 0.22 λ for = 55 ° H = 0.22 λ for = 58 ° (3)

f) The behavior of "true emission of secondary electrons from the ion-blasted silicon surface area reflects the appearance of WOS at the blasting depth D _m and the formation of stabilized WOS at the blasting depth D _F. The onset of the emission increase refers to the blasting depth.

The determination of the manner in which λ depends on the ion beam energy E, the angle of incidence of the ion beam Θ and the temperature of the SOI T material (or more precisely, the temperature of the silicon SOI layer) has also been investigated. Figure 1E shows how λ changes with E and Θ at room temperature. Curve 15 defines the domain limit at which WOS is created. Curves 15, 16 and 120 limit the portion of the WOS domain in which the wavy relief has a more coherent structure with a linear relationship between λ and D _F according to equation (2). Figure IF shows how λ changes with T at different E and hodnot values. Curve 22 corresponds to E = 9 keV, θ = 45 °, curve 24 corresponds to E = 5 keV, θ = 45 °, curve 26 corresponds to E = 9 keV, Θ = 55 °. From these data is possible

It can be concluded that at room temperature λ may vary over the preferred range of values from 30 to 120 nm. Changing the sample temperature from room temperature to 550 K has no significant effect. Heating the sample to temperatures between 550 K and 850 K reduces the λ value by a factor of 3.3 compared to the equivalent value at room temperature. The inventors have further found that the depth D _{B of the} silicone layer 3 of the SOI material necessary for a particular WOS can be expressed by the equation:

D _b > Dr + H + R

It is known that the depth D _B = D _F + H is sufficient to form a stable WOS. However, the inventors have discovered that for calculating the minimum depth DB it is important to consider the impact of the ions penetration R to ensure reliable formation of mutually isolated quantum silicon conductors by the blasting process and / or subsequent annealing of the blasted article at high temperatures. Research by the inventors has also confirmed that secondary ion emission from the SOI isolator begins when the lowest WOSs reach a distance of approximately R from the silicon-SOI isolator boundary (this effect of previous hidden boundary detection is known in the art blast depth profiling). These discoveries provide the basis for regulating the formation of desired silicon nano-structures based on a predetermined WOS wavelength value. The data shown in FIG. IEs allow E and hodnoty values to be set for the desired λ value in the range of 30 to 120 nm at room temperature where 30 nm is the minimum λ obtainable at room temperature (with E = 2 keV and Θ = 58 ° ). Lower λ values can be obtained by heating the SOI material to temperatures above 550 K, as can be seen in Figure 1F. Accordingly, suitable values for E, Θ and T can be determined for the selected value λ

- 14 ion intersection and formation depth D _F can be calculated from equations (1) and (2) and empirical data (3), and the desired depth D _{f of the} silicon SOI layer can then be calculated from equation (4). Thus, if it is necessary to create a silicon quantum conductor field with a conductor period (λ) of 30 nm, it can be determined (by extrapolation) that for λ = 30 nm E = 2 keV and Θ = 58 °. From these values it can be determined that R = 7 nm, H = 6.6 nm, D _F = 27.6 nm and thus D _B = 41.2 nm. In another example, if it is necessary to create a silicon quantum conductor field with a conductor period (λ) of 9 nm, the sample should be heated to obtain a 3.3-fold reduction of λ so that λ = 9 nm at 850 K corresponds to λ = 30 nm at room temperature. From Figure IE it can be determined (by extrapolation) that for λ = 9 nm at 850

K is E = 2 keV and Θ = 58 °. From these values it can be determined that R = 7 nm, H = 1.98 nm, DF = 0 nm and therefore DB = 8.98 nm. In another example, if it is necessary to create a silicon quantum conductor field with a conductor period (λ) of 120 nm, it can be determined from Figure IE that for λ = 120 nm E = 8 keV and Θ = 45 °.

From these values it can be determined that R = 16 nm, H = 27.6 nm, D _F = 146 nm and therefore D _B = 189.6 nm. Alternative parameters may be established for the same λ; for example, for λ = 120 nm, E = 5.5 keV and Θ = 43 °. From these values it can be determined that R = 12.25 nm, H = 30 nm, D _F = 146 nm and therefore D _B = 188.3 nm. Thus, as shown above, the parameters governing the process can be predetermined based on the desired period of the quantum conductor field λ in the range from 9 nm to 120 nm. A wide range of SOI materials can be used for the process; for example, SOI obtained by SIMOX technology (Separation by IMplanted OXygen) with the desired thickness of the silicon layer can be used. For those skilled in the art, other options are obvious, for example

- 15 SOI prepared by Smart Cut or single crystal silicon films on either quartz or glass membranes. Fig. 1 refers to an example of the use of SOI prepared by SIMOX technology. The thickness of the silicone layer 3 should be. highly uniform (suitable SIMOX membranes are available from Ibis, USA). After selecting the SOI material, a silicon nitride masking layer can be prepared as shown in Figure 1A. The silicon nitride layer 1 is applied to the top of the silicon dioxide thin layer 2. In the silicon nitride layer 1, a masking window is formed by lithography and plasma-chemical etching, the silicon dioxide layer acting as a finishing layer for plasmachemical etching. The thin oxide layer 2 in the region of the window is then removed by chemical wet etching to form a hinge edge around the peripheral portion of the mask window. The masking layer is sufficiently thick to prevent the formation of any wave-like relief on the surface of the silicon layer 3 in the region of the masking window. Creating a hinge edge around the mask window is advantageous in obtaining a uniform WOS surrounded by a flat silicon surface around the edge of the mask window. The silicon layer 6 is grounded during the blasting process, as indicated under no. 11 in FIG. 1A to prevent charge damage from the field 7 produced by the blasting process. As shown in Figures ΙΑ, IB and 2, the masking window is preferably oriented with respect to the ion beam direction so that the ion impact plane, defined by the surface normal and the ion flow direction, is oriented parallel to the other sides of the rectangular mask window. This maximizes the effect of the hinge edge of the mask window. The thickness of the mask can be selected such that the mask material is removed by a blasting process because the mask material and the silicon surface below

The masking windows are shot-blasted at approximately the same degree. The blasting process is performed based on predetermined parameters E, Θ and T. Blasting can be performed in a very high vacuum chamber of a surface analysis apparatus (e.g., PHI 660 type from Perkin Elmer, USA). During blasting, the secondary ion emission signal from the SOI insulator layer 4 is monitored and blasting is terminated when the signal exceeds a predetermined threshold, indicating that the lowest point of the wave has reached the silicon-insulator boundary. As can be seen from FIG. The IC, the threshold value S can be appropriately defined as the value at which the signal exceeds the average background value B by a value equal to the height between the peaks of the noise signal N (i.e., S = B + N). A low energy electron gun (not shown) can be used to compensate for the charge of the ions, by which the blasting region (as known from the deep profiling of the insulators) is irradiated by electrons. These steps lead to the formation of a quantum conductor pole 7 in the region of the mask window. Figure 1D shows the internal structure of the pole 7 when it is formed at room temperature as described above. When the formation of the field at 850 K takes place, the internal structure of the field 7 differs from that obtained at room temperature. When preparing at 850 K, the inventors found that the WOS wavelength was reduced by a factor of 3.3 compared to the wavelength obtained by similar process parameters at room temperature. However, the thickness of the layers and the slope of the sides of the wines remain the same as at room temperature. The structure obtained at 850 K does not contain regions of crystalline silicon 12. The horizontal dimension of the regions of amorphous silicon nitride 8 is shortened by a factor of 3.3 compared to the regions formed by

- 17 room temperature and regions of silicon oxynitride 10 are not separated. In this case, the regions 9 can be considered as quantum conductors after annealing as described below, isolated from each other by regions 8. After the blasting process, the product is annealed in an inert environment, preferably at a temperature of 1000 to 1200 ° C for at least one hour. , followed by oxidation at high temperature. The annealing process forms regions of a mixture of inclusions of amorphous silicon and silicon nitride 9, which are effectively depleted of nitrogen, resulting in clearly defined boundaries of nitride around regions 9. In addition, regions 9 are converted to crystalline silicon. The step involving high temperature oxidation may be similar to the oxidation processes used to prepare the oxide gating layers as known in the semiconductor manufacturing art. From the foregoing, it can be concluded that the silicon quantum pole conductors obtained according to the present invention can be formed in one of three basic ways. Firstly, the blast-blasted structure at room temperature comprises crystalline silicon regions 12, which can be considered quantum conductors isolated from each other by regions 8. Secondly, if the blast-blasted structure at room temperature is subsequently annealed, the regions 9 become crystalline silicon and can also be considered as quantum conductors. In this case, the regions 12 also increase in volume and merge with the regions 9, the quantum conductors being again isolated from each other by regions 8. Thirdly, if the field is blasted at 850 K, the blasted structure contains no crystalline silicon regions and subsequent annealing transforms the region 9 to crystalline silicon to form quantum field conductors isolated from each other by regions 8. Annealing also extends the lowest corner portions of regions 8, thereby improving the isolation of regions 9 in all regions.

-18 cases described above. From the foregoing, it is apparent that quantum conductor fields with a wavelength in the range of 30 to 120 nm can be produced by blasting at room temperature and that shorter wavelengths of up to 9 nm can also be achieved by increasing the material temperature during blasting above 550 K. wavelengths are reached at about 850 K. Depending on the process parameters, the WOS obtained by blasting may comprise regions 12 of crystalline silicon, which may form useful quantum conductors isolated from each other.

Where the blasted structure itself does not contain these regions 12, they are formed in the regions 9 by subsequent annealing of the blasted product, which annealing is preferred whether the blasted product comprises regions 12 or not. Figures 2 and 3 illustrate the process of preparing a device (in this example FET) by incorporating a quantum wire array 7, generated by the process described herein. Fig. 2A shows a masking layer 1 defining a masking window on the SOI material prior to blasting, as described above. Fig. 2B shows the quantum conductor field 7 formed in the silicone layer 6 as described above. Figure 2C shows the first step in the formation of FET by incorporating a quantum conductor array 7. The high temperature oxidation step described above creates a thin insulating layer 28 on the surface of the blasted product. Using known lithographic techniques, a poly-silicon rectangle 30 extending over the entire width of the field 7 is deposited on top of the insulator layer. The length L of the field 7 may be greater than the width W of the poly-silicon region 30. The region surrounding the poly-silicon 30 may be back etched into the insulator layer 4. They are then etched by lithographing the ends of the poly-silicon region 30, leaving silicon pads 36 and 38 at either end of the array 7 and coating the pads 36 and 38, such as

FIG. 2D, where the figure 17 denotes an etching field 7 whose length has been reduced from L to W. It is understood that, after preparing the quantum conductor array, devices can be prepared by embedding the field using any of a variety of conventional semiconductor manufacturing technologies. Figures 2D and 3 illustrate a FET device constructed as described above. In FIG. 2D and 3, the numeral 32 indicates the oxide insulator layer and 34 the poly-silicon layer that remains after etching the respective layers 28 and 30 in FIG. 2C. In FIG. 3, the layers 32 and 34 are shown partially removed to expose the quantum conductor array 7 lying underneath for viewing purposes. 2D, layers 32 and 34 can be seen extending beyond the washers 36 and 38. The invention allows the preparation of apparatus of this type with smaller dimensions than hitherto possible and / or apparatus with improved reproducibility of results and product qualities. To date, the invention has been described with particular reference to the formation of quantum conductor fields based on wave-ordered structures formed by blasting. However, WOS, created by the basic blasting process, can also be used as a mask for ion implantation (e.g., high-energy phosphorous ion implantation) in silicon for quantum computer applications. Ion implantation is the basic technique for introducing doping atoms into semiconductor materials for VLSI applications. Window masking layers are commonly used to create a two-dimensional distribution of a dopant. Ion implantation is usually followed by annealing to electrically activate the dopant and to restore the crystalline structure of the semiconductor. For example, if an OWS is provided, as shown in FIG. ID, then regions 8 can serve as masks for high temperature annealing to allow implantation of the selected ion into the

The right side of the region 9 (the direction of flow of the low-energy ions is perpendicular to the surface of the material). Such an ion implantation process would result in a structure of alternating doped lanes of the same period as the WOS. When a WOS period of 10 nm or less is used, the phosphor-doped bands formed in this way are very close to allow interaction of the type required for quantum computer applications. Ion implantation can also be used as an alternative method of generating quantum wire fields using WOS as a mask. Solid-state one-dimensional silicon nano-structures can form the basis of nano-scale electronics and optoelectronics manufacturing processes, in particular, but not exclusively, silicon quantum wire arrays, and can be used to manufacture silicon-based optoelectronic and nano-electronic devices. Silicon-quantum conductors are formed by ion irradiation and, in an even closer sense, the blasting process of the silicon-on-insulator (SOI) surface with high purity by a uniform flow of molecular nitrogen ions to form a wave-like relief providing an array of silicon "quantum conductors in nano-scale. The quantum conductor array can be used as a light source in optoelectronic devices by pole guiding or in nano-electronic devices, for example, as a channel in a field-effect transistor (FET). The invention may be improved and modified without departing from the scope of the invention as defined in the appended claims.

Claims (12)

PATENT CLAIMS A method of forming a silicon nano-structure, characterized in that the silicon surface is shot blasted by a uniform flow of molecular nitrogen ions under very high vacuum to form a periodic wavy relief whose wave face is oriented in the direction of the ion impact plane, The wavelength of the periodic wavelength in the range of 9 nm to 120 nm and the selected wavelength determines the ion energy, the angle of incidence of ions on the surface of the material, the temperature of said silicone layer, the depth of formation of said wavy relief. into silicon. 2. The method of forming a silicon nano-structure according to claim 1, wherein the ion energy, the angle of incidence of the ions, the temperature of the silicon, the depth formed and the height of the wavy relief are determined based on the relation of the ion energy. and the height of the corrugated relief to the wavelength of the periodic corrugated relief, wherein the ion penetration range is determined from the ion energy. 3. A method of forming a silicon nano-structure according to claim 1, wherein prior to blasting, a silicon nitride mask comprising a hinge edge window is deposited on the blasting surface onto the silicon surface, and blasting of said silicon surface is performed through said window. The method of forming a silicon nano-structure according to claim 1, characterized in that, prior to blasting, all impurities are removed from the surface of said silicon layer to form said corrugated relief. A process for forming a silicon nano-structure according to claim 1, characterized in that after blasting the material with said relief is annealed in an inert environment. The method of forming a silicon nano-structure according to claim 1, characterized in that the material is annealed at a temperature of between 1000 and 1200 ° C for at least one hour. A method of forming a silicon nano-structure according to any one of claims 1 to 6, characterized in that the uniform nitrogen flux blasting is applied to a silicone nano-structure comprising a silicon quantum conductor field, the silicon comprising a silicon layer of insulating silicon material. the thickness of the silicon layer is selected to be greater than the sum of the generated depth of the corrugated relief, the height of the corrugated relief and the ion penetration range. A method for forming a silicon nano-structure according to claim 7, characterized in that during the blasting the secondary ion emission signal is sensed from the layer of insulating silicon material and the blasting is terminated when the sensed signal value reaches a predetermined threshold. 9. The method of forming a silicon nano-structure according to claim 8, wherein the threshold value of the secondary ion emission signal is a value at which the signal exceeds the average background value by a difference equal to the height between the peaks of the noise component of the signal. Apparatus for performing a method of forming a silicon nano-structure according to claims 1 to 9, characterized in that it comprises a quantum conductor field formed in an optoelectronic device by blasting a silicone nano-structure comprising a silicon quantum conductor field with a uniform molecular nitrogen ion flux, a silicon layer of insulating silicon material, the thickness of the silicon layer being greater than the sum of the wavy relief depth formed, the wavy relief height and the ion penetration range formed. Apparatus for carrying out a method of forming a silicon nano-structure according to claims 1 to 9, characterized in that it comprises a quantum conductor field formed in an electronic device by blasting a silicone nano-structure comprising a silicon quantum conductor field by uniform ion flux -24-molecular nitrogen, wherein the silicon comprises a silicon layer of insulating silicon material, the thickness of the silicon layer is greater than the sum of the wavelength of the embossed depth, the height of the wavy emboss, and the extent of ion penetration formed. An apparatus for performing a method of forming a silicon silicon nano-structure according to claim 11, comprising silicon pads joined by a silicon quantum conductor array, an insulator layer disposed on the quantum conductor array, and an electrode disposed on the insulator.