TW478013B - Method of formation of nano-structures on the surface of silicon - Google Patents

Abstract

A process for controllably forming silicon nanostructures such as a silicon quantum wire array. A silicon surface is sputtered by a uniform flow of nitrogen molecular ions in an ultrahigh vacuum so as to form a periodic wave-like relief in which the troughs of said relief are level with the silicon-insulator border of the SOL material. The ion energy, the ion incidence angle to the surface of said material, the temperature of the silicon layer, the formation depth of the wave-like relief, the height of said wave-like relief and the ion penetration range into silicon are all determined on the basis of a selected wavelength of the wave-like relief in the range 9 nm to 120 nm. A silicon nitride mask having pendant is used to define the area of the silicon surface on which the array is formed. Impurities are removed from the silicon surface within the mask window prior to sputtering. For the purpose of forming a silicon quantum wire array, the thickness of the SOI silicon layer is selected to be greater than the sum of said formation depth, said height and said ion penetration range, the fabrication of the silicon wires being controlled by a threshold value of a secondary ion emission signal from the SOI insulator. The nanostructure may be employed in optoelectronic and nanoelectronic devices such as a FET.

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 478013 A7 _B7 _ V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method for forming a microstructure on the surface of a silicon crystal. These nanostructures can become The foundation of microelectronics and optoelectronics production technology, especially the display of silicon quantum wires, but not limited to, it can be used to manufacture silicon-based optoelectronics and microelectronic components. The invention particularly relates to a method for forming a silicon quantum wire by ion irradiation, and particularly relates to spraying a high-purity silicon-on-insulator SOI surface with a uniform nitrogen molecular ion fluid. Method to form wavy undulations and make a micro-silicon "quantum wire" display. This quantum display can be used as a light source for optoelectronic devices or microelectronic components; for example, as a field effect crystal channel. [Background of the present invention] In a known molding method of cross-section 10x1 5nm2 embedded in sand crystal quantum wire oxidized chopping, it uses low-energy oxygen ions to implant silicon crystals, and then uses electron beam lithography, and wet Chemical etching, and finally annealing in an inert environment at high temperature. This method forms silicon crystal quantum wires buried in the central V-groove of the bottom end of silicon oxide (see Y · Ishikawa, N · Shibata, P · Fukatsu "Fabrication of [ll〇] -aligned Si quantum wires embedded in Si02 by low- energy oxygen implantation ”Nuclear Instruments and Methods in Physics Research, B, 1999, v. 147, pp. 304-309,

Elsevier Science Ltd.) [Reference 1] 3 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) j -------- Order --------- Line ( (Please read the notes on the back before filling out this page) 478013

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs π 5. Description of Invention (2) This method has many disadvantages. The use of 'electron beam lithography and wet chemical etching when v-shaped grooves are formed on the surface of silicon crystals will limit the density of structural elements and reduce the yield of quantum wires. Due to the lack of control in the process, it also reduces the yield of quantum wires. Due to the low density of quantum wires, this quantum wire is not suitable for microelectronic devices where the interaction of charged particles in adjacent quantum wires is very important. In a published work in which the present inventors participated, a method for forming a wave-structured structure (WOS) on a sand crystal, particularly on a silicon-on_insulator SOI, was disclosed. This method includes: sputtering a silicon-on-insulator SOI film by using a nitrogen molecular probe as a light field sweep cat in a high vacuum to form a periodic waveform Wave-ordered-structures (WOS). This nano-undulating wave front is in the direction of ion incidence. This method includes detecting a secondary ion emission signal of the SOI insulator, and stopping sputtering when the signal reaches a predetermined threshold. This published work also revealed that the formation of wave-ordered-structures (W0S) depends on the ion energy E, the ion incidence angle Θ, the normal condition of the opposite surface, and the silicon-on -insulator SOI) Temperature T of the sample. This work also confirms the characteristics of undulation molding, that is, the sputtering depth Dm is relative to the intensity of the wave undulation, and this work also discusses that the sputtering depth Dm depends on the ion energy E, the ion incidence angle Θ, and the insulator. The temperature T ′ of the silicon-on-insulator SOI sample and the wavelength λ of the wave-ordered-structures (WOS) of the outer sand single crystal film are determined. This work also states that the thickness Dm of the silicon-on_insulator SOI on the outer edge of the insulator must not be less than the required wave. 4 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). I --- ^ --- 7 --- install -------- order --------- (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 478013 A7 B7 ___ V. Description of the invention (3) Sputtering depth of long wave-ordered-structures (WOS) (see VK Smirnov, DS Kibalov, SA Krivelevich, PA Lepahin, EV Potapov , RA Yankov, W. Skorupa, VV Makarov, AB Danilin uWave-ordered structures formed on SOI wafers by reactive ion beams ”-Nuclear Instruments and Methods in Physics Research B, 1 999, v. 14 7, pp. 310-315, Elsevier Science Ltd.) [Reference 2]. In one of the works invented by one inventor of the present invention, an annealing method is disclosed for reference to the material disclosed in Reference 2, which has an inert environment temperature of 100CTC for one hour, so that It is annealed. (See VK Smirnov, AB Danili n; "Nanoscale wave-ordered structures on SOI" -Proceedings of the NATO Advanced Research Workshop "Perspective, science and technologies for novel silicon on insulator devices, 5 / Ed By PIF Hemment, 1999, Elsevier Science Ltd.) [Reference 3] 〇 In another work in which one of the inventors participated, it was revealed that the thickness of the silicon nitride (Si3N4) layer, Dn, for the ion energy E, the incident angle of the ion to the surface and high temperature annealing (900-1 000 (: One hour). Annealing has no effect on the thickness of the silicon nitride (SisN4) layer, but increases the sharpness of the silicon (Si) / silicon nitride (ShNU) interface. As shown in his work, Dn is equal to the distance R at which the ions penetrate into the silicon, and it shows a linear function of the ion energy e of the same energy used in the wave_ordered-structures (WOS) molding method. According to the data disclosed here, the dependence of the distance R of the ions into the silicon on the ion energy E can be expressed by the following formula: 5 This standard is suitable for financial standards (CNS) A4 (21G X 297)-IIII J --- U --- install -------- Order --------- < Please read the precautions on the back before filling this page) System 478013 Α7 V. Description of the invention (4) R (nm) = 1.5E (keV) + 4. (1) (see VI. Bachurn, Α. Churilov, EV. Potapov, VK. Smirnov, VV. Makarov and Α · Β · Danilin;

Formation of Thin Silicon Nitride Layers on Si by

Low Energy N2 + Ion Bomardment "-Nuclear I nstruments and M et: hodsi η P hysics R esearch B, 1 999, v, 147, pp. 316-319, Elsevier Science Ltd ·) [Reference 4]. The above reference material [Reference 1 ], [Reference 2], [Reference 3], and [Reference 4] jointly reveal the basic method of silicon quantum wire display molding. Compared with the use of separation lines, the use of sand gravel strands is displayed on microelectronics and optoelectronic components. The biggest benefit is to increase the output and enhance the current characteristics of the signal-to-noise ratio. Due to the interaction of charged particles in adjacent quantum wires, it also gives the potential possible output power to display elements. But the above reference material [Reference 1] [Reference 2], [Reference 3], and [Reference 4] The basic methods of silicon quantum wire display molding jointly disclosed also have many shortcomings. [Reference 2] does not address the waveform structure when the sputtering depth is increased from Dm to Dp ( Whether the wavelength λ of wave-ordered-structures (WOS) changes and whether there is any correlation between 001 and 01) are discussed. The present invention confirms that the characteristics of this method should be the same as when the depth DF The final wave-ordered-structures (WOS) on display are related to the so-called depth Dp of [Reference 2]. At the same time, [Reference 2] for wave-ordered-structures (WOS) There are no limits on the division of the shaped (E, θ) plane, and there is no discussion. These limits are in [Reference 2], [Ref. 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) I ----- Ί--T ----------- Order ----- III ^ 9 (Please read the notes on the back before filling out this page} 478013 A7 B7 V. Invention Explanation (5) Examination 3] and [Reference 4] revealed that the work meant 'required thickness of the silicon outer silicon single crystal (silicon_on-insulator SOI) film, not based on the relative relationship between the parameters provided in the reference material to predict in advance The basic parameters used to control the sputtering process (ion energy E, incidence angle Θ, and temperature T of the silicon single crystal film on the outer edge of the insulator) cannot be determined in advance. In addition, for single-crystal sand films ( silicon-on_insulator SOI) Wave-ordered-structures (WOS) It is important that the undulating valleys of the shape structure and the silicon crystal layer of the outer silicon single crystal film on the outer edge of the insulator coincide with the insulating layer boundary of the outer silicon single crystal film on the outer edge of the insulator. [Reference 2] revealed that the secondary ion emission signal can be used to stop the sputtering, but it does not indicate any method of predetermining the signal chirp to separate the silicon line. That is to say, the aforementioned work does not disclose a method that can make molding-wave-ordered-structures (WOS), the undulations of the wave structure and the silicon crystal layer of the outer silicon single crystal film The boundary between the insulating layers of the silicon single crystal film on the outer edge of the insulation precisely matches to form an isolated silicon crystal line display. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page). Moreover, in order to obtain useful structures in the practical application of silicon-based microelectronics and optoelectronic technology integration, for example, in a In the two separated silicon pad structures connected by the microstructure display, it must be confirmed that the microstructure display can be formed in a specific micro range on the surface. However, there is no application of lithography or the use of lithography in the above works. The present invention also determines that the process of the wave-ordered-structures (WOS) molding process is an impurity on the surface of the silicon-on-insulator SOI film, especially the impurities. It is oxidized 7. This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 478013 A7 B7 V. Description of the invention (6) Shi Xi is very sensitive. These impurities reduce the fluctuation of wave_ordered-structures (WOS). Smoothness. As everyone knows, silicon crystals in the air will produce a thin layer of natural oxide sand on the surface. (Please read the precautions on the back before filling this page) The shortcomings mentioned above have a lot to do with the control of the actual application of wave-ordered-structures (WOS) molding. Known microelectronic components include a 20-nm diameter silicon channel (quantum dot) For the connected silicon pad, a 40-nm-thick insulating layer covers the surface of the silicon channel and the chip-cut pad, and the electrode provided on the surface of the insulating layer. The sand crystal contact pad and the silicon channel are formed on the outer edge of the silicon single crystal. Film (silicon-on-insulator SOI) on a sand single crystal film of matter (see Ε · Leobandung, L. Guo, Υ · Wang, S, Chou "observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperature over 100k ”Applied Physics Letters, v. 67, No. 7, 1 9 9 5, pp · 9 3 8-9 4 0, American Institute of Physics, 1 9 9 5) [Reference 5] o Due to the small size of the component The use of lithography, the shortcomings of this known microelectronic component are non-channel display and low production capacity, that is, the repeatability of effective results is low. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics printed on another known quantum wire base field effect Material (quantum -wire-based FET), comprising silicon pads having a crystal sand 86xl00nm2 of seven wire channel of square cross-section of the connector. The sand crystal line channel is covered by a silicon oxide layer having a thickness of 30-n m. An electrode gate is placed on this group of silicon wire channels. The previous part was made of silicon_on-insulator SOI material (see JP · Colinge, X. Baie, V. Bayot, 8) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 478013 A7 B7 V. Description of the invention (7) E. Grivei αΑ silicon-On-Insulator Quantum Wire59 -Solid-State Electronics, Vol. 39, No. 1,1 996, pp. 49-5 1, Elsevier Science Ltd 1 996) [Reference 6] 0 Due to the limitation of lithography process, this known device cannot form a silicon channel at a distance equal to the length of the silicon channel. All the above references indicate how to make sand quantum wire displays in specific experimental cases. However, none of these references summarizes an experimental method to enable quantum wires to be made to the required size, nor does it propose effective process control. In addition, there is a strong demand in the market, hoping to integrate silicon quantum wires into useful components, such as forming a channel display on a field effect crystal. [Introduction of the present invention] A first feature of the present invention is to provide a silicon crystal microstructure forming method, which includes: using a uniform nitrogen molecular ion fluid to sputter a silicon crystal surface in a vacuum of a degree of vacuum so that Forming a periodic wave-like undulation, the wave-like undulation wavefront is in the same direction as the ion incident plane; and includes the following steps: selecting a desired periodic wave-like undulation with a wavelength ranging from 9 nm to 120 nm; According to the selected wavelength, determine the ion energy, the angle of incidence of the ions on the surface of the material, the temperature of the silicon crystal, the depth of the wave-like undulations, the height of the wave-like undulations, and the range of ions penetrating into the silicon crystal. Preferably, the ion energy, the angle of incidence of the ion, the temperature of the silicon crystal, the depth of the wave-like undulations and the height of the wave-like undulations are all in accordance with the 9 ^ paper standard applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) " " ----- ^ ---- Installation -------- Order --------- (Please read the notes on the back before filling (This page) 478013 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Five, Daming description (8) _ Stomach 11 sub-energy 'the ion incident angle, the temperature of the silicon crystal, the wave-like depth and the wave-like fluctuation The height depends on the experimental data obtained from the periodic undulating wavelengths. This method also includes another step, which is to position and include a suspended silicon nitride mask on the surface of the silicon crystal surface before sputtering, and to sputter the silicon crystal surface through the window hole. . Preferably, this method further includes another step, which is to remove the silicon crystal layer which can form the undulating undulations as desired, before sputtering. Preferably, this method further comprises the step of annealing the undulating material in an inert environment after sputtering. Preferably, the annealing temperature of this material is 1 000 to 1200. 〇, and the time is one hour. In a preferred embodiment of the present invention, the silicon crystal microstructure includes a silicon quantum wire display 'and the silicon crystal includes a silicon crystal layer of an insulating outer silicon single crystal film material. This method also includes: selecting the thickness of the silicon crystal layer to be not less than the forming depth of the wavy undulations, the height of the wavy undulations, and the sum of the ion penetration range. Preferably, this method further includes another step, which is to detect the secondary ion emission signal from the insulating layer of the silicon single crystal film material of the outer periphery of the insulator while sputtering, and to reach a predetermined Sputtering is terminated at the critical threshold, and preferably the critical threshold of the secondary ion emission signal is that the signal exceeds the average background threshold by an amount equal to the peak-to-peak height of the signal noise portion. According to other features of the present invention, the present invention also provides optoelectronic and electrical components including a quantum wire display formed by the method of the present invention, such as a photoelectric two piece, which includes a silicon pad connected by the silicon quantum wire display, One set in the quantum 10 (please read the precautions on the back before filling this page) Order --------- Line one • Ί. -Μ · ^^ scales are applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478013 A7 B7 V. Description of the invention (9) The insulating layer on the wire display and a photovoltaic element with an electrode on the insulating layer. The device for completing this method includes an ultra-high straight empty box, a sample introduction device, an ion microbeamer with adjustable ion energy and ion probes, an electron gun, a position and adjustment of tilt and rotation and attachment There is a sample holder that can change and control the temperature of the sample, a second electronic detector, and a second ion proton analyzer. A convenient conventional device is a high-output instrument for multi-functional surface analysis. The present invention provides a single parameter to control the manufacturing process with a single parameter, that is, a display period (wavelength) required to control the relevant parameters of the manufacturing process, so that it can overcome the disadvantages of the conventional techniques described above. In order to allow your reviewing committee to better understand the technical content of the present invention, the preferred embodiments are described in conjunction with the following drawings, among which. [Schematic description] Figure 1A is a perspective view of a siiicon-on-insulator SOI structure, including a silicon nitride mask. Figure 1B is a perspective view of the final silicon-on-insulator SOI structure after applying the present invention's preliminary silicon-on-insulator SOI structure in Figure 1A. . Fig. 1C shows a control situation in which a secondary ion emission signal is applied to the method of the embodiment of the present invention. Figure 1D is an enlarged cross-sectional view of part A of the sputtering structure in Figure 1B. 11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----- V — ^ ------------ Order --------- (Please read the notes on the back before filling out this page) 478013

Printed tiles and description of invention by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (10) _ ^ Figure 1E is a schematic diagram showing the ion incident angle 'ion energy and waveform structures (WOS) formed according to the present invention ). FIG. 1F is a schematic diagram showing different ion energies given by the wavelengths of the wave-ordered-stmctures (WOS) formed according to the present invention as a function of the material temperature of the silicon on-insulator SOI. . Figures 2A to 2D are schematic plan views of a silicon-on-insulator SOI film, showing the formation of a field-effect crystal element made according to the method of the present invention. Fig. 3 is a body view showing a field effect crystal structure made by the method of the present invention and provided with a silicon crystal microstructure display channel. [Detailed description of the preferred embodiment] Please refer to the preliminary silicon-on-insulator SOI structure shown in Figure 1A, which includes a sand substrate 5, a silicon oxide insulation layer 4. A silicon crystal layer 3 for forming quantum wires thereon, a thin oxide sand layer 2 formed on the sand crystal layer 3, and a nitrided sand mask layer 1 formed on the thin silicon oxide layer 2. . The final silicon-on-insulator SOI structure of FIG. 1B includes a silicon substrate 5 and a silicon oxide insulating layer 4 as shown in FIG. 1A, and the silicon layer as shown in FIG. 1A. 3 has been sputtered into a sand crystal layer 6 masked by the mask layer 1 shown in FIG. 1A, and a silicon crystal microstructure display 7 not masked by the mask layer 1. The arrow indicates the flow direction of N2 + ion fluid during sputtering. The basic sputtering method for forming wave-ordered-structures (WOS) has been detailed in [Reference 2]. For example, 12 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) " " " " " " First (Please read the precautions on the back before filling this page) ---- ---- Order ---------. 478013 A7 B7 V. Description of the invention αι) As described in [Reference 2], a focused ion beam is scanned on a silicon single crystal film (silicon) -on-insulator SOI) material surface. (Please read the precautions on the back before filling in this page) Figure 1D shows an example of a cross-section of a silicon crystal microstructure formed by the sputtering method of the present invention, which includes amorphous silicon nitride region 8, amorphous silicon crystal and nitride Silicon mixture region 9, silicon oxide silicon crystal region 10, and crystalline silicon crystal region 12. The following will describe in detail the silicon-on-insulator SOI material shake, wave-ordered-structures (WOS) and wave-ordered-structures (WOS) molding methods. For the parameters, please refer to Figure 1: D2 is still the initial thickness of silicon-on-insulator SOI material and silicon crystal layer 3. DF is still undulating and thick (that is, in order to obtain a stable wave structure, the minimum thickness of the material removed by sputtering from the original surface of the silicon layer 3 to the peak of the wave structure, the "sputter thickness" is still from the original silicon Vertical distance from the crystal surface to the apex of the wave structure). ΗThe undulating height of the stable waveform structure; that is, the vertical distance between the peak and the nearest valley (double the amplitude). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. R still allows an ion with fixed ion energy to penetrate into the scope of the silicon crystal. The present invention is particularly related to the control of the sputtering process so that the desired microstructure of the silicon crystal can be attached to predetermined parameters. In addition, the investigation of the waveform structure forming method made by the inventor of the present invention, the following conclusions were obtained: (a) from the beginning of the waveform structure forming at the sputtering depth of 111 until the waveform structure is stable at the sputtering depth Dp, and thereafter Sputtered to a depth of several times 値, the wavelength λ of the waveform structure remains unchanged. 13 ^ Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) " 478013 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the invention (12) (b) The height of the undulation, as The time rises linearly from the depth Dm to the depth Dp, and reaches Η 値 at the depth Dp, and then continues to sputter after that, both remain unchanged. That is, after DF, sputtering continues, and the shape and size of the wave structure remain unchanged. However, the wave structure is on the silicon-on-insulator SOI material outside the insulator and is opposite to the direction of ion incidence. Directional movement (Figure 13D shows the position of the waveform structure when the sputtering depth is equal to DF ', and the main diagram shows the situation of this structure after the termination of sputtering). (c) The relative relationship between Dp and Dm can be expressed by the following formula ...

Dp = 1.5Dm (d) The relative relationship between DF and the incident angle λ of the waveform structure can be expressed by the following formula: DF (nm) = 1.3 3 6 (λ (nm) -9) (2) The range of λ is between 9nm ~ 120nm. (e) H is proportional to λ, and this ratio changes with the incident angle Θ of the ion beam; for example: Let θ = 410 丨 J Η = 0 · 26λ at θ = 43 〇 丨 J Η = 0 · 25λ at θ = 45 0 丨 J Η = 0 · 23λ squared θ = 550 丨 J Η = 0 · 22λ at θ = 58 〇 Η J Η = 0 · 22λ (f) from the "real" surface of the silicon crystal, The behavior of the secondary electron emission, the appearance of the response waveform structure at the sputtering depth of 0111, and the stability at the sputtering depth of Dp 14 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ( (Please read the precautions on the back before filling this page) -II! I 丨 · 1 — ------ 478013 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Explanation of the Waveform Structure (13) The beginning of emission enhancement is equivalent to the depth Dm. The beginning of emission saturation is equivalent to the depth of sputtering D7. Investigations have also shown that λ still depends on the ion beam energy E, the incident angle of the ion beam Θ, and the outside of the insulator. Temperature of the silicon-on-insulator SOI material (or, especially, the silicon crystal of the outer silicon single-crystal film) Temperature). The data shown in Figure 1E shows that at room temperature, λ changes with the beam energy E and the incident angle Θ of the ion beam. Curves 15 define wave-ordered-structures (WOS) forming points The range of the domain. According to formula (2), curves 1 5, Ιό, and 120 define the wave-ordered-structures (W0S) subdomain. The wave-like fluctuations have a more coherent structure that is linear between λ and D. Figure 1 F shows that λ changes with temperature at different E and Θ 値. Curve 22 is equivalent to E = 9keV, θ = 45%. Curve 26 is equivalent to E = 9 ke V, Θ = 55. From these The data shows that at room temperature, λ can be changed from 30nm to 120nm in a useful number range. Adjusting the temperature of the sample from room temperature to 500K does not produce a significant effect. When the temperature is increased from 500K to 850K, compared with room temperature, the 値 of λ is reduced by a factor of 3.3. The inventor of the present invention also determined the required waveform structure (^^ 6-0 pool 1 ^ (1-structures, W0S) The depth Db of the silicon crystal layer 3 of the silicon-on-insulator SOI material can be expressed by the following fractional table The: DB > DP + H + R (4) One should note here, the depth DB = DP + H is required to be of the desired stable structure forming the waveform (wave-ordered-structures, WOS). However, the inventors of the present invention have found that in order to ensure the reliable formation of the quantum silicon crystal lines from each other by the sputtering method, and / or the high temperature annealing of subsequent sputtering products, when calculating the minimum depth DB, the ions penetrate into the range R It is important to take into consideration 15 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ '7 --------------- Order- -------- (Please read the notes on the back before filling this page) 478013 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of Invention (14). Investigations conducted by the inventors of the present invention have also confirmed that when the valleys of wave-ordered-structures (WOS) are separated from the insulating outer-peripheral sand single crystal film (silicon-on-insulator SOI), the sand crystal-insulator is shaken. When the distance of the boundary is about R, the secondary emission of ions of the insulating layer of silicon-on-insulator SOI is started. These observations enable the forming method of the silicon microstructures required to be formed with a wavelength-ordered-structures (WOS) wavelength λ 値. In the data shown in Figure 1E, the allowable E and Θ 値 can be determined according to the required λ 所需 from 30nm to 120nm at room temperature (E = 2keV and θ = 58.). Low λ 値, as shown in Figure IF, can be obtained by heating a silicon-on_insulator SOI material to 550K. Similarly, for a selected λ 値, the appropriate E, Θ, and T 値 can also be determined. The range of ion penetration and forming depth D9 can be obtained from the calculation of formulas (1) and (2) and experimental data (3), and the silicon-on-insulator SOI silicon crystal layer The required depth Dp can be obtained from the calculation of formula (4). For example, to produce a silicon quantum wire display with a line period (λ) of 30 nm as shown in Figure 1E, (by induction) it can be determined that λ = 30η E = 2keV and θ = 58 °. From these 値, it can be determined that R = 7nm, H = 6.6nm, DP = 27.6nm, so DB = 41.2nm.

In another example, if a silicon quantum wire display with a line period (λ) of 9 nm is to be manufactured, the sample should be heated to reduce λ by 3.3 times, and the Chinese paper standard (CNS) A4 specification should be applied at 850K 16 (210 X 297 mm)-丨; ---- ΊΙΙΊ ----------- Order --------- Line 9 (Please read the notes on the back before filling this page ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478013 A7 B7 V. Description of the invention (15) _ at λ = 9ηη is equivalent to λ = 30ηη at room temperature. As shown in Figure 1E, (by induction) it can be determined that at 850K λ = 9ηη, E = 2keV and θ = 58 °. From these 値, we can determine R = 7nm, H = 1.99nm, DF = Onm, so D9 = 8.98nni 〇 In another example, if you want to make a silicon quantum wire display with a line period (λ) of 120nm, according to the first As shown in Figure 1E, it can be determined that at λ = 120ηιη, E = 8keV and Θ = 45 °. 0 From these 贝, [j can determine R = 16nm, H > 27.6nm, ϋί ^ Μόππ, so D3 = 189.68nm . Similarly, λ 値, it is also possible to obtain another set of parameters 値, that is, when λ = 120ηιη, E = 5.5keV and θ = 430. From these 値, Beij can determine that R = 12.25nm, H = 30nm, DB = 188.3nm. Therefore, in the quantum wire display period λ 値 is between 9nm and 120nm, the parameters of the control process can be determined as described above. Many silicon-on-insulator SOI materials can be used for this process. For example, silicon-on-insulator silicon-on-insulators obtained by SIMOX technology -insulator SOI) material can reach the desired silicon layer thickness. For other feasible methods, anyone skilled in the art can easily think of, for example, smart cut technology to obtain a siiicon_on_insulator SOI material, or A silicon single crystal film is placed on a quartz or glass wafer. 17 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---- ΊΜ--7 · ---- installation -------- order ------- -^ 9 (Please read the notes on the back before filling this page) 478013 A7 B7 V. Description of the invention (16) (Please read the notes on the back before filling this page) The first picture shows the oxygen implantation and separation Application of SIMOX technology. The thickness of the silicon layer 3 must be highly uniform (suitable SIMOX wafers can be obtained from the US Ibis). -Once the silicon-on-insulator SOI material is selected, the silicon nitride mask layer 1 can be prepared according to Figure 1A. A silicon nitride mask layer 1 is placed on top of the thin silicon oxide layer 2. The mask window hole can be formed on the mask layer 1 by lithography and plasma chemical etching, and the thin silicon oxide layer 2 is used as a barrier layer during the plasma chemical etching. Thereafter, the thin silicon oxide layer 2 in the mask window hole area is removed by a wet etching method, and an overhang is formed on the periphery of the mask window hole. The thickness of the mask layer must be sneezed to prevent the formation of undulations on the surface of the silicon crystal layer 3 in the window area of the mask. A cantilevered edge is formed at the periphery of the mask window hole, which helps to obtain a uniform wave-ordered-structures (WOS) surrounded by a flat silicon crystal surface. As shown by icon number 11A, the silicon crystal layer 6 is grounded during the sputtering process to prevent damage to the silicon crystal microstructure display 7 caused by the charges generated during the sputtering. The photomask window holes printed by the Employee Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are best shown in Figures IA, 1B, and 2 and oriented in the direction of the ion beam so that the ion incident plane will be stable and the ion flow direction will be square. The long sides of the mask window holes are parallel. This design achieves the best results with the overhang of the reticle window. The thickness of the photomask can be selected and when the photomask material is removed by sputtering, the surface of the sand crystal and the surface of the sand crystal in the window aperture area of the photomask are sputtered at almost the same rate. The sputtering step is performed according to predetermined E, T and θ parameters. The sputtering step can be performed on a surface analyzer (such as PHI660 from Perkin Elmer, USA). 18 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm). 478013 A7 B7. 5. Description of the invention (π) (please Read the precautions on the back before filling out this page). During sputtering, the secondary ion emission signal of the insulating layer 4 of the silicon-on-insulator SOI material material is monitored, and the sputtering is terminated when the signal exceeds the critical threshold. The waveform structure is displayed. (Wave-orderedeStructures, WOS) The wave valley is close to the silicon-insulator boundary. As shown in Fig. Ic, 'this critical 値 s' can be defined as the signal exceeding the average background 値 B is equal to the noise signal N peak-to-peak height (that is, S = B + N). A low-energy electron gun (not shown) can be used to illuminate the sputtering area with electrons to compensate for ion charging. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs These steps shape the silicon microstructure display 7 in the mask window area. Figure 1D shows the internal structure of the silicon crystal microstructure display 7 during manufacturing at room temperature. When manufactured at 850K, the internal structure of the silicon microstructure display 7 was different from that produced at room temperature. When manufactured at 850K, the inventors of the present invention have found that compared to manufacturing at room temperature with the same parameters, the wave-ordered-structures (WOS) wavelength 値 is reduced by a factor of 3.3. However, the thickness of each surface layer and the inclination of the wavy edges are the same as when manufactured at room temperature. The structure obtained at the time of manufacturing at 850K has no crystalline silicon region 12. The horizontal area of the amorphous silicon nitride region 8 is shortened by a factor of 3 · 3 compared with room temperature fabrication, and the silicon oxide silicon crystal region 10 is not separated. In this case, after the annealing, the amorphous silicon crystal and silicon nitride mixed region 9 is separated by the amorphous silicon nitride region 8 and can be regarded as a quantum wire. After the sputtering step is completed, the product is annealed at a high temperature under an inert environment. The annealing temperature is 100OW to 1 200 ° C, and the annealing time is at least a minimum. 19 The paper size is applicable to China National Standard (CNS) A4 (210 X 297). Mm) — 478013 A7 B7 V. Description of the invention (IS) (Please read the notes on the back before filling this page). The annealing step causes the nitrogen of the amorphous silicon and silicon nitride mixed region 9 to be effectively used up, and a sever nitrogen cut boundary is generated around the amorphous silicon and silicon nitride mixed region 9. In addition, the amorphous silicon and silicon nitride mixed region 9 is converted into crystalline silicon. The high temperature oxidation step is similar to the oxidation step used in the fabrication of semiconductor oxide gates. As described above, with the present invention, the silicon quantum wire display can be manufactured by any one of three basic methods. First, at room temperature sputtering, the sputtered structure includes a silicon crystal region 12 which is separated by an amorphous silicon nitride region 8 and can be regarded as a quantum line. Second, if the structure that is sputtered at room temperature is subsequently annealed, the amorphous silicon crystal and silicon nitride mixture region 9 is covered with crystalline silicon crystals, and can also be regarded as a strand. Third, if the display is sputtered at 850K, the sputtered structure does not contain the crystalline silicon crystal region 12, and then the annealing causes the amorphous silicon crystal and silicon nitride mixture region 9 to be converted into crystalline silicon crystal. Thus a quantum wire display is formed, which is separated by the amorphous silicon nitride region 8. Annealing is also applied to the lowest corner of the amorphous silicon nitride region 8 to improve the separation effect of the amorphous silicon crystal and silicon nitride mixture region 9 in each of the above cases. Qiu Zhi, Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the above, quantum wire displays with a wavelength range of 30 nm to 120 nm can be sputtered at a temperature of more than 550K. Increasing the material temperature can shorten the wavelength to about 9nm, and at about 850K, the lowest wavelength can be obtained. Depending on the process parameters, the wave-ordered-structures (WOS) obtained by sputtering may include crystalline silicon regions 12, which can provide usable and separated quantums. In the sputtered structure that does not include the crystalline silicon region 12, the quantum wire is formed in the amorphous silicon and silicon nitride mixed region 9 by annealing the sputtered structure. 20 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 478013 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (19) The second and third pictures show the above method Made of elements with quantum wire displays 7, such as field-effect crystals. Figure 2A shows τρ: before sputtering, the nitrided sand mask layer 1 square; the outer edge of the silicon outer single crystal silicon (silicon_on_insulat〇r SOI) material boundary defines a mask window. FIG. 2B shows that the quantum wire display 7 is formed on the sand crystal layer 6. Fig. 2C shows the first step of making a 7-element with quantum wire display. The first step of the barrel temperature oxidation step 'forms a thin insulating layer 28 on the surface of the firing structure. Using conventional lithographic techniques, a polysilicon rectangular structure 30 is formed on the upper end of the insulating layer and traverses the width of the quantum wire display 7. The length l of the line display 7 may be longer than the width W of the sandy rectangular structure 30. In the surrounding area of the polysilicon rectangular structure, the silicon single crystal film insulating layer 4 can be etched back to the outer edge of the insulator. Then, by lithography, the endpoints of the polysilicon rectangular structure 30 are etched, so that the silicon pads 36 and 38 are left on the quantum wires Any of Chen Yu's ['7' and 'and', as shown in Figure 2D, metallizes the sand crystal pad% and π. Here, the reference numeral 17 refers to the quantum wire display 7 after the etching, and its length From L to W. It must be understood here that after the quantum wire is made, the element can be manufactured using conventional semiconductor manufacturing techniques. Figures 2D and 3 show the field effect transistor made by the above method. In Figs. 2D and 3, reference numeral 32 denotes an oxide insulating layer, and reference numeral 34 denotes a polysilicon crystal layer left after etching of the opposite surface layers 28 and 30 in Fig. C3. In Figure 3, each of the layers 32 and 34 has been partially removed, leaving the underlying quantum wire display 7 exposed. In FIG. 2D, the layers 32 and 34 extend to the silicon pads 36 and 38. The invention enables the size of such components to be made smaller, and the product quality and stability to be better. 21 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----- TI — --- • Installation -------- Order --------- ^ 9. Jing Jing read the notes on the back before filling out this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478013 A7 B7 V. Description of the invention (20) The present invention uses the sputtering method to make quantum wires on a wave-shaped structure. Display, has been detailed. However, the sputter-shaped wave structure can also be used as a photomask for ion implantation (for example, low-energy phosphorus ion implantation) of silicon crystals in quantum computer applications. Ion implantation is a basic technology used to introduce dopant atoms into semiconductor materials when large integrated circuits are used. Photomask layers with window holes are commonly used for the formation of two-dimensional dopant distributions. After ion implantation, it is usually annealed to activate the dopants electronically and restore the semiconductor crystal structure. For example, after the wave-ordered-structures (WOS) shown in FIG. 1D is formed, the subsequent high-temperature annealing of the amorphous silicon nitride region 8 can be used as a photomask to implant selected ions into the amorphous silicon crystal. The right-hand side of the silicon nitride mixture region 9 (the flow of the low-energy ionic fluid is usually directed toward the surface of the material). This ion implantation process will form a twisted pattern of alternating doping with the same period as wave-ordered-structures (WOS). Using a waveform structure with a period of about 10 nm, the phosphorus-doped strands formed in this way can enable the interaction required in quantum computer applications. Ion implantation can also be used for the fabrication and display of photon beams using wave structures as photomasks. The above are only specific embodiments of the present invention, but the features of the present invention are not limited to it. Any changes or modifications that can be easily considered by those skilled in the art in the field of the present invention can be covered in the following case. The scope of patents. 22 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----- Qin --- ^ 4 ----------- Order ------- --Line (Please read the notes on the back before filling this page)

Claims (1)

478013 A8 B8 C8 D8 6. Scope of patent application 1. A method for forming the microstructure of a silicon crystal surface, including: (Please read the precautions on the back before filling this page) Sentence gas molecule ionic fluid is sputtered on a sand crystal surface to form a periodic wave-like undulation, and the wave front of the wave-like undulation is in the same direction as the ion incident plane; and includes the following steps: before sputtering: selecting A required periodic wave-shaped undulation wavelength, ranging from 9nm to 120 nm; according to the selected wavelength, determine the ion energy, the ion incidence angle to the surface of the material, the temperature of the silicon crystal, the wave shape The forming depth of the undulations, the height of the undulating undulations and the range in which ions penetrate into the silicon crystal. 2. The method as described in item 1 of the scope of patent application, wherein the ion energy, the ion incident angle, the temperature of the silicon crystal, the forming depth of the wavy undulations and the height of the wavy undulations all depend on the ion The energy, the angle of incidence of the ion, the temperature of the silicon crystal, the depth of the wave-like undulations, and the height of the wave-like undulations depend on the experimental data obtained from the wavelength of the periodic wave-like undulations, and the ion infiltration The range of silicon crystals depends on the ion energy. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 3. The method described in item 1 of the scope of patent application, further comprising a step of positioning a silicon nitride light with a window hole and containing overhangs before sputtering A cover on the sputtering area of the silicon crystal surface, and sputtering the silicon crystal surface through the window hole. 4. The method according to item 1 of the patent application scope, further comprising a step of removing any impurities from the wavy undulating silicon crystal layer before sputtering, before sputtering. 5. The method according to item 1 of the patent application scope, further comprising: annealing the undulating material in an inert environment after sputtering. 23 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 478013 A8 B8 _§_ — 6. Application for patent scope 6. The method described in item 1 of the scope of patent application, where the annealing temperature of this material It is between 1000 and 1200 ° C, and the time is one hour. 7. The method as described in item 1 of the aforementioned patent application scope, wherein the silicon crystal microstructure includes a silicon quantum wire display, and the silicon crystal includes a silicon crystal layer of an insulating outer silicon single crystal film material. This method also includes: selecting the thickness of the silicon crystal layer to be not less than the forming depth of the wavy undulations, the height of the wavy undulations, and the sum of the ion penetration range. 8. The method according to item 7 of the scope of patent application, further comprising a step of detecting a secondary ion emission signal from the insulating layer of the silicon single crystal film material on the outer periphery of the insulating material while spraying, and When the measured signal reaches a predetermined threshold, sputtering is terminated. 9. The method according to item 7 of the scope of patent application, wherein the critical threshold of the secondary ion emission signal is the peak-to-peak height of the signal exceeding the average back-equivalent amount of the signal noise portion. 10. As described in item 1 of the scope of the patent application, it includes an insulating layer of a plurality of silicon crystal pads connected by the silicon quantum wire display on the quantum wire display, and an electrode provided on the insulating layer. . (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs n · ϋι tmi ϋϋ ϋϋ ml ϋϋ HI —Jm -ϋ— -I i ^ n In HI 11 n In —. 1 — ^ " J.ml —ϋ In ϋϋ I 1 ^ 1 ϋϋ — ^ — .1— L ^ w 1 ^ 1 l ^ n 1 ^ 1 * — ^ 1 f 24 This paper size applies to the Chinese National Standard (CNS ) A4 size (210X297 mm)