SG53009A1 - Clock skew minimization system and method for integrated circuits - Google Patents

Clock skew minimization system and method for integrated circuits

Info

Publication number
SG53009A1
SG53009A1 SG1997002395A SG1997002395A SG53009A1 SG 53009 A1 SG53009 A1 SG 53009A1 SG 1997002395 A SG1997002395 A SG 1997002395A SG 1997002395 A SG1997002395 A SG 1997002395A SG 53009 A1 SG53009 A1 SG 53009A1
Authority
SG
Singapore
Prior art keywords
integrated circuits
clock skew
minimization system
skew minimization
clock
Prior art date
Application number
SG1997002395A
Other languages
English (en)
Inventor
Ferenc Miklos Bozso
Philip George Emma
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG53009A1 publication Critical patent/SG53009A1/en

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    • H—ELECTRICITY
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Wire Bonding (AREA)
SG1997002395A 1996-08-20 1997-07-07 Clock skew minimization system and method for integrated circuits SG53009A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/700,261 US5760478A (en) 1996-08-20 1996-08-20 Clock skew minimization system and method for integrated circuits

Publications (1)

Publication Number Publication Date
SG53009A1 true SG53009A1 (en) 1998-09-28

Family

ID=24812827

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997002395A SG53009A1 (en) 1996-08-20 1997-07-07 Clock skew minimization system and method for integrated circuits

Country Status (10)

Country Link
US (2) US5760478A (fr)
EP (1) EP0827203B1 (fr)
JP (1) JP3358171B2 (fr)
KR (1) KR100267430B1 (fr)
CN (1) CN1110097C (fr)
DE (1) DE69715762T2 (fr)
HK (1) HK1006242A1 (fr)
MY (1) MY117458A (fr)
SG (1) SG53009A1 (fr)
TW (1) TW357447B (fr)

Families Citing this family (153)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US6714625B1 (en) * 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US5763943A (en) * 1996-01-29 1998-06-09 International Business Machines Corporation Electronic modules with integral sensor arrays
US5856914A (en) * 1996-07-29 1999-01-05 National Semiconductor Corporation Micro-electronic assembly including a flip-chip mounted micro-device and method
JP2964983B2 (ja) * 1997-04-02 1999-10-18 日本電気株式会社 三次元メモリモジュール及びそれを用いた半導体装置
US6687842B1 (en) * 1997-04-02 2004-02-03 Tessera, Inc. Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6281590B1 (en) * 1997-04-09 2001-08-28 Agere Systems Guardian Corp. Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module
US6037822A (en) * 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
DE19743344C2 (de) * 1997-09-30 1999-08-05 Siemens Ag Verfahren zur Montage integrierter Schaltkreise mit Schutz der Schaltkreise vor elektrostatischer Entladung und entsprechende Anordnung von integrierten Schaltkreisen mit Schutz vor elektrostatischer Entladung
CA2218307C (fr) * 1997-10-10 2006-01-03 Gennum Corporation Configuration d'encapsulation 3-d pour module multipuce
JP3441948B2 (ja) * 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
US5869895A (en) * 1997-12-15 1999-02-09 Micron Technology, Inc. Embedded memory assembly
US6198168B1 (en) 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6150188A (en) * 1998-02-26 2000-11-21 Micron Technology Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6090636A (en) * 1998-02-26 2000-07-18 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6091138A (en) * 1998-02-27 2000-07-18 Advanced Micro Devices, Inc. Multi-chip packaging using bump technology
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
WO1999066556A1 (fr) * 1998-06-16 1999-12-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Systeme micro-electronique a integration verticale et son procede de fabrication
US6225699B1 (en) * 1998-06-26 2001-05-01 International Business Machines Corporation Chip-on-chip interconnections of varied characteristics
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
JP2000022074A (ja) * 1998-07-03 2000-01-21 Rohm Co Ltd 半導体装置
US5854507A (en) * 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6674163B1 (en) * 1998-08-18 2004-01-06 Oki Electric Industry Co., Ltd. Package structure for a semiconductor device
US6424034B1 (en) 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
KR100470386B1 (ko) * 1998-12-26 2005-05-19 주식회사 하이닉스반도체 멀티-칩패키지
WO2000041242A1 (fr) * 1998-12-30 2000-07-13 Infineon Technologies Ag Ensemble semi-conducteur
RU2213391C2 (ru) 1998-12-30 2003-09-27 Инфинеон Текнолоджиз Аг Полупроводниковое устройство с интеграцией по вертикали
US6201302B1 (en) * 1998-12-31 2001-03-13 Sampo Semiconductor Corporation Semiconductor package having multi-dies
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
US6204562B1 (en) * 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
US6215193B1 (en) * 1999-04-21 2001-04-10 Advanced Semiconductor Engineering, Inc. Multichip modules and manufacturing method therefor
US6386456B1 (en) * 1999-06-04 2002-05-14 International Business Machines Corporation Memory card identification system
US6239484B1 (en) 1999-06-09 2001-05-29 International Business Machines Corporation Underfill of chip-under-chip semiconductor modules
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US6351144B1 (en) * 1999-07-15 2002-02-26 Altera Corporation Programmable logic device with unified cell structure including signal interface bumps
US6255899B1 (en) 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
KR100673378B1 (ko) * 1999-12-17 2007-01-23 삼성전자주식회사 칩 스케일 적층 칩 패키지와 그 제조 방법
KR100401019B1 (ko) * 1999-12-30 2003-10-08 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6316981B1 (en) * 2000-03-13 2001-11-13 Intel Corporation Signal distribution network on backside of substrate
US6731009B1 (en) * 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
US6437990B1 (en) * 2000-03-20 2002-08-20 Agere Systems Guardian Corp. Multi-chip ball grid array IC packages
US6735755B2 (en) * 2000-03-27 2004-05-11 Jeng-Jye Shau Cost saving methods using pre-defined integrated circuit modules
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
JP3829050B2 (ja) * 2000-08-29 2006-10-04 松下電器産業株式会社 一体型電子部品
KR20020058201A (ko) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 반도체패키지 및 그 제조 방법
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6748994B2 (en) * 2001-04-11 2004-06-15 Avery Dennison Corporation Label applicator, method and label therefor
US6658373B2 (en) * 2001-05-11 2003-12-02 Field Diagnostic Services, Inc. Apparatus and method for detecting faults and providing diagnostics in vapor compression cycle equipment
JP3670625B2 (ja) * 2001-06-13 2005-07-13 松下電器産業株式会社 半導体装置およびその製造方法
US6662126B2 (en) * 2001-08-14 2003-12-09 Sun Microsystems, Inc. Measuring skew using on-chip sampling
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US6541847B1 (en) 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
US6635970B2 (en) 2002-02-06 2003-10-21 International Business Machines Corporation Power distribution design method for stacked flip-chip packages
TW523890B (en) * 2002-02-07 2003-03-11 Macronix Int Co Ltd Stacked semiconductor packaging device
DE10205208A1 (de) * 2002-02-08 2003-09-18 Conti Temic Microelectronic Schaltungsanordnung mit einer mit einem programmierbaren Speicherelement bestückten Leiterplatte
US6730540B2 (en) * 2002-04-18 2004-05-04 Tru-Si Technologies, Inc. Clock distribution networks and conductive lines in semiconductor integrated circuits
US7122904B2 (en) * 2002-04-25 2006-10-17 Macronix International Co., Ltd. Semiconductor packaging device and manufacture thereof
US20050104211A1 (en) * 2002-05-07 2005-05-19 Shinji Baba Semiconductor device having semiconductor chips mounted on package substrate
JP4601892B2 (ja) * 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
US6973793B2 (en) * 2002-07-08 2005-12-13 Field Diagnostic Services, Inc. Estimating evaporator airflow in vapor compression cycle cooling equipment
US6659512B1 (en) * 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
JP2004063579A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp 積層型半導体装置
WO2004015764A2 (fr) 2002-08-08 2004-02-19 Leedy Glenn J Integration de systeme verticale
AU2003301632A1 (en) * 2002-10-22 2004-05-13 Unitive International Limited Stacked electronic structures including offset substrates
TWI230447B (en) * 2003-04-25 2005-04-01 Advanced Semiconductor Eng Multi-chips package
DE10319271A1 (de) * 2003-04-29 2004-11-25 Infineon Technologies Ag Speicher-Schaltungsanordnung und Verfahren zur Herstellung
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
WO2004112136A1 (fr) * 2003-06-12 2004-12-23 Koninklijke Philips Electronics N.V. Dispositif electronique
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
US7098075B1 (en) * 2004-01-29 2006-08-29 Xilinx, Inc. Integrated circuit and method of producing a carrier wafer for an integrated circuit
US7303941B1 (en) 2004-03-12 2007-12-04 Cisco Technology, Inc. Methods and apparatus for providing a power signal to an area array package
US9466595B2 (en) * 2004-10-04 2016-10-11 Intel Corporation Fabrication of stacked die and structures formed thereby
CN101099382B (zh) * 2004-11-12 2011-08-17 松下电器产业株式会社 数字电视接收机用电路模块
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8090897B2 (en) * 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
GB2444663B (en) * 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
DE102005056907B3 (de) * 2005-11-29 2007-08-16 Infineon Technologies Ag 3-dimensionales Mehrchip-Modul
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
EP1835618A1 (fr) * 2006-03-16 2007-09-19 STMicroelectronics S.r.l. Réduction du temps d'exécution d'un transfert de données commandé en externe dans un dispositif intégré
US20070290333A1 (en) * 2006-06-16 2007-12-20 Intel Corporation Chip stack with a higher power chip on the outside of the stack
KR100800472B1 (ko) 2006-06-23 2008-02-04 삼성전자주식회사 스택 패키지(ｓｔａｃｋ ｐａｃｋａｇｅ)용 반도체메모리장치 및 이의 독출 데이터 스큐 조절방법
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
KR100843214B1 (ko) * 2006-12-05 2008-07-02 삼성전자주식회사 메모리 칩과 프로세서 칩이 관통전극을 통해 연결된 플래너멀티 반도체 칩 패키지 및 그 제조방법
US8049323B2 (en) * 2007-02-16 2011-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip holder with wafer level redistribution layer
US8228704B2 (en) * 2007-02-28 2012-07-24 Samsung Electronics Co., Ltd. Stacked semiconductor chip package with shared DLL signal and method for fabricating stacked semiconductor chip package with shared DLL signal
KR101196483B1 (ko) * 2007-07-16 2012-11-01 삼성전자주식회사 스택형 반도체 장치 및 이 장치의 신호 분배 방법
GB0716055D0 (en) * 2007-08-17 2007-09-26 Regan Timothy J Vertical distribution of planar signals in stacked integrated circuits
US8080874B1 (en) * 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US20090091017A1 (en) * 2007-10-09 2009-04-09 Fjelstad Joseph C Partitioned Integrated Circuit Package with Central Clock Driver
US7863960B2 (en) * 2009-04-30 2011-01-04 International Business Machines Corporation Three-dimensional chip-stack synchronization
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
TWI449339B (zh) * 2010-12-13 2014-08-11 Ind Tech Res Inst 時脈偏移補償裝置
KR101774938B1 (ko) 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US8508029B2 (en) * 2011-09-29 2013-08-13 Broadcom Corporation Semiconductor package including an integrated waveguide
US8670638B2 (en) 2011-09-29 2014-03-11 Broadcom Corporation Signal distribution and radiation in a wireless enabled integrated circuit (IC) using a leaky waveguide
US9318785B2 (en) 2011-09-29 2016-04-19 Broadcom Corporation Apparatus for reconfiguring an integrated waveguide
US9075105B2 (en) 2011-09-29 2015-07-07 Broadcom Corporation Passive probing of various locations in a wireless enabled integrated circuit (IC)
US9570420B2 (en) 2011-09-29 2017-02-14 Broadcom Corporation Wireless communicating among vertically arranged integrated circuits (ICs) in a semiconductor package
US9030253B1 (en) 2012-05-30 2015-05-12 Altera Corporation Integrated circuit package with distributed clock network
US9064077B2 (en) 2012-11-28 2015-06-23 Qualcomm Incorporated 3D floorplanning using 2D and 3D blocks
US9098666B2 (en) 2012-11-28 2015-08-04 Qualcomm Incorporated Clock distribution network for 3D integrated circuit
US9536840B2 (en) 2013-02-12 2017-01-03 Qualcomm Incorporated Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
US9041448B2 (en) 2013-03-05 2015-05-26 Qualcomm Incorporated Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
US9177890B2 (en) 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
US9171608B2 (en) 2013-03-15 2015-10-27 Qualcomm Incorporated Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
US9543965B1 (en) 2013-10-04 2017-01-10 Altera Corporation Interposer with embedded clock network circuitry
KR20170001238A (ko) * 2015-06-26 2017-01-04 에스케이하이닉스 주식회사 계단형 기판을 포함하는 반도체 패키지
US9893058B2 (en) * 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure
CN105810237B (zh) * 2016-03-15 2018-08-21 西安紫光国芯半导体有限公司 一种关于dram时钟树走线结构
KR20240036154A (ko) 2016-10-07 2024-03-19 엑셀시스 코포레이션 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이
US10580757B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Face-to-face mounted IC dies with orthogonal top interconnect layers
CN108108501B (zh) * 2016-11-25 2021-07-02 成都锐成芯微科技股份有限公司 集成电路芯片的延时控制方法
US10475766B2 (en) * 2017-03-29 2019-11-12 Intel Corporation Microelectronics package providing increased memory component density
JP2018182213A (ja) * 2017-04-19 2018-11-15 富士通株式会社 半導体装置及び半導体装置の製造方法
CN111418060A (zh) * 2017-10-20 2020-07-14 艾克瑟尔西斯公司 具有正交的顶部互连层的、面对面安装的ic裸片

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59224154A (ja) * 1983-06-03 1984-12-17 Mitsubishi Electric Corp ゲ−トアレイ
JPS60175444A (ja) * 1984-02-22 1985-09-09 Hitachi Ltd 半導体装置
JPS6235528A (ja) * 1985-08-08 1987-02-16 Fujitsu Ltd 高密度実装法
JPS62272560A (ja) * 1986-05-20 1987-11-26 Nec Corp マルチチツプパツケ−ジのクロツク回路接続構造
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
JPH02126685A (ja) * 1988-11-07 1990-05-15 Seiko Epson Corp 固体イメージセンサー
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JP2871041B2 (ja) * 1990-09-06 1999-03-17 三菱電機株式会社 半導体装置
JP3238395B2 (ja) * 1990-09-28 2001-12-10 株式会社東芝 半導体集積回路
EP0486829B1 (fr) * 1990-10-22 1997-04-23 Seiko Epson Corporation Dispositif semi-conducteur et système d'empaquetage pour dispositif semi-conducteur
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
US5434453A (en) * 1991-04-26 1995-07-18 Hitachi, Ltd. Semiconductor integrated circuit device and computer system using the same
JPH04346463A (ja) * 1991-05-24 1992-12-02 Mitsubishi Electric Corp マイクロ波帯パッケージ
US5331235A (en) * 1991-06-01 1994-07-19 Goldstar Electron Co., Ltd. Multi-chip semiconductor package
US5164817A (en) * 1991-08-14 1992-11-17 Vlsi Technology, Inc. Distributed clock tree scheme in semiconductor packages
JPH05129516A (ja) * 1991-11-01 1993-05-25 Hitachi Ltd 半導体装置
US5260233A (en) * 1992-11-06 1993-11-09 International Business Machines Corporation Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
JPH06244282A (ja) * 1993-02-15 1994-09-02 Nec Corp 半導体集積回路装置
DE69426695T2 (de) * 1993-04-23 2001-08-09 Irvine Sensors Corp., Costa Mesa Elektronisches modul mit einem stapel von ic-chips
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
US5565816A (en) * 1995-08-18 1996-10-15 International Business Machines Corporation Clock distribution network

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CN1175805A (zh) 1998-03-11
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MY117458A (en) 2004-06-30
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US5760478A (en) 1998-06-02
TW357447B (en) 1999-05-01
HK1006242A1 (en) 1999-02-19
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EP0827203B1 (fr) 2002-09-25
JP3358171B2 (ja) 2002-12-16
CN1110097C (zh) 2003-05-28
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DE69715762T2 (de) 2003-04-24

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