JPS59224154A - ゲ−トアレイ - Google Patents

ゲ−トアレイ

Info

Publication number
JPS59224154A
JPS59224154A JP58099653A JP9965383A JPS59224154A JP S59224154 A JPS59224154 A JP S59224154A JP 58099653 A JP58099653 A JP 58099653A JP 9965383 A JP9965383 A JP 9965383A JP S59224154 A JPS59224154 A JP S59224154A
Authority
JP
Japan
Prior art keywords
substrates
substrate
semiconductor substrate
semiconductor substrates
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58099653A
Other languages
English (en)
Inventor
Shuhei Iwade
岩出　秀平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58099653A priority Critical patent/JPS59224154A/ja
Publication of JPS59224154A publication Critical patent/JPS59224154A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は、ゲート７ンイにおいて２枚の半導体基板を
７リンブチツブ方式で実装する方法に関するものである
。
従来、この種の装置としては第１図に示すものがあった
。この図において、１は半導体基板、２はパンケージ基
板、３はハンダバンプ、４は前記パンケージ基板２のピ
ンである。
第１図の構造において、半導体基板１はハンダバンプ３
により、パッケージ基板２と固（接続される。このため
、集積度の高い半導体基板１が動作状態で発熱すると、
摂氏１００度近い高温になるため半導体基板１とパッケ
ージ基板２０間の温度差、および熱膨張係数の差により
半導体基板１０両端付近で、ハンダバンプ３に横方向の
応力がかかり、半導体基板１側で、バンプ付近の電気配
線が断線したり、ハンダバンプ３がはがれたりする問題
が生じ、半導体基板１の大きさを小さくしたり、パンケ
ージ基板２の熱膨張係数を半導体基板１のそれに合わせ
るため、高価な材料を使ったパンケージ基板２を用いな
ければならないという問題があった。
また、半導体基板１で発生した熱は、主としてハンダバ
ンプ３だげを介して拡散するため、熱抵抗が大きく、動
作状態において半導体基板１だげが他よりも高温に、な
り、それが半導体基板１上に−作られた集積回路素子の
動作速度を著しく低下させるという問題があった。
この発明は、上記のような従来の欠点を除去するために
なされたもので、大きさが異なり、かつ、回路機能を分
担する２枚の半導体基板をハンダバンブで接続し、それ
をパンケージ基板に接着することにより熱膨張による横
方向のカをなくし、半導体基板に発生する熱を取り除き
易い構造としたゲートアレイを提供するものである。以
下この発明の一実施例を第２図に基づいて説明する。
この図において、１１および１５は第１および第２の半
導体基板、１２はパッケージ基板、１３はハンダバンブ
、１４は前記パッケージ基板１２に取り付けられたピン
である。１６はパンケージ側の電極パッド、１７は前記
第２の半導体基板１５とパンケージ基板１２の電気的導
通な得るための金属配線である。
第２図の構造において、第１の半導体基板１１には、例
えば複雑な論理機能を実現できる論理回路を集積し、第
２の半導体基板１５に消費電力が大きい入カバソファや
出カバソファン集積し、これら２枚の半導体基板１１．
１５Ｙフリンプチッブ方式で接続する。第２の半導体基
板１５０面積は第１の半導体基板１１よりや匁大きくす
ることが好ましく、第２の半導体基板１５とパンケージ
基板１２は接着剤等で接着する。そして、パンケージ基
板１２と第２の半導体基板１５の間の電気的導通は、金
属配線１７によって実現する。
なお、上記実施例では、第１．第２の半導体基板１１．
１５のづち第１の半導体基板１１に、論理機能を有する
素子を塔載し、第２の半導体基板１５には入カバツファ
、出カバソファを塔載［７たが、これは両者の発熱量を
ほぼ等価となるようにしたもので、第１の半導体基板１
１と第２の半導体基板１５の消費電力がほぼ等しくなる
ような講成ならば、集積回路の機能分担などのように分
離してもよい。
以上説明したように、この発明のゲートアレイによれば
、第１の７半導体基板と第２１７）半導体基板の発熱量
はほぼ同一であり、熱膨張係数はともに等しいので、熱
膨張による第１．記２の半導体基板の両端付近でのハン
ダバンプにかかる横方向の応力はほとんどなくなり、ハ
ンダバンプ付近の電気配線が断勝したりハンダバンブが
はかれるという問題はなくなる。また、第２の半導体基
板はパンケージ基板に密着して取り付けられているため
熱抵抗が低くなり、特にその動作時における第２の半導
体基板の温度が従来よりも低くなる。したがって、高温
による集積回路素子の動作速度の劣化を防ぐことができ
る。また、パンケージ基板の上での第Ｊ、第２の半導体
基板の占める面積が従来のものより小さくなるため、パ
ンケージ基板７小さくし装置全体の集積度を向上させる
ことができる等の利点が得られる。
【図面の簡単な説明】
第】図は従来の７リツプフロツプ実装構造を示す図、第
２図はこの発明の一実施例によるクリップフロンプ実装
構造を示す図である。 図中、１１は第１の半導体基板、１２はパッケージ基板
、１３はハンダバンブ、１４はビン、１５は第２の半導
体基板、１６は％極バッド、１７は金属配線である。 第１図 第２図 Ｇ 特許庁長官殿 １．事件の表示　　　特願昭５８−０９９１３５３号２
、発明の名称　　　ケートアレイ ３、補正をする者 ５、補正の対象 明細書の発明の詳細な説明の欄および図面６、補正の内
容 （１）明細書第４頁１４行の「機能分担な」を、「機能
分担を」と補正する。 （２）同じく第５頁１４行、１５〜１６行の「フリップ
フロップ」を、それぞれ「フリップチップ」と補正する
。 （３）　　図面第２図を別紙のように補正する。 以上

Claims (1)

    【特許請求の範囲】
  1. 論理機能を有するゲート回路および入カバソファ、出力
    パンフ７’＆有する１玲素子を第１および第２の半導体
    基板にそれぞれの発熱量が同じになるように分離して形
    成し、前記第１および第２の半導体基板を７リツプチツ
    プ実装力式で接続するとともに前記第２の半導体基板を
    パッケージ基板に密接して取り付けたことを特徴とする
    ゲート７ンイ。
JP58099653A 1983-06-03 1983-06-03 ゲ−トアレイ Pending JPS59224154A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58099653A JPS59224154A (ja) 1983-06-03 1983-06-03 ゲ−トアレイ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58099653A JPS59224154A (ja) 1983-06-03 1983-06-03 ゲ−トアレイ

Publications (1)

Publication Number Publication Date
JPS59224154A true JPS59224154A (ja) 1984-12-17

Family

ID=14253011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58099653A Pending JPS59224154A (ja) 1983-06-03 1983-06-03 ゲ−トアレイ

Country Status (1)

Country Link
JP (1) JPS59224154A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01260846A (ja) * 1988-04-12 1989-10-18 Hitachi Ltd 半導体実装モジュール
JPH0574774A (ja) * 1991-09-12 1993-03-26 Nec Kyushu Ltd 樹脂封止型半導体装置
EP0827203A3 (en) * 1996-08-20 1998-04-15 International Business Machines Corporation Clock skew minimisation system and method for integrated circuits
EP1093165A1 (en) * 1999-10-12 2001-04-18 Agilent Technologies Inc. Integrated circuit assembly
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01260846A (ja) * 1988-04-12 1989-10-18 Hitachi Ltd 半導体実装モジュール
JPH0574774A (ja) * 1991-09-12 1993-03-26 Nec Kyushu Ltd 樹脂封止型半導体装置
EP0827203A3 (en) * 1996-08-20 1998-04-15 International Business Machines Corporation Clock skew minimisation system and method for integrated circuits
US6040203A (en) * 1996-08-20 2000-03-21 International Business Machines Corporation Clock skew minimization and method for integrated circuits
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
EP1093165A1 (en) * 1999-10-12 2001-04-18 Agilent Technologies Inc. Integrated circuit assembly

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