SG52901A1 - An electrode structure of semiconductor integrated circuit and method for forming the package therefor - Google Patents

An electrode structure of semiconductor integrated circuit and method for forming the package therefor

Info

Publication number
SG52901A1
SG52901A1 SG1997000057A SG1997000057A SG52901A1 SG 52901 A1 SG52901 A1 SG 52901A1 SG 1997000057 A SG1997000057 A SG 1997000057A SG 1997000057 A SG1997000057 A SG 1997000057A SG 52901 A1 SG52901 A1 SG 52901A1
Authority
SG
Singapore
Prior art keywords
chip
pads
electrode structure
peripheral bonding
bonding pads
Prior art date
Application number
SG1997000057A
Other languages
English (en)
Inventor
Masakazu Ishino
Ryohei Satoh
Mamoru Mita
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of SG52901A1 publication Critical patent/SG52901A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
SG1997000057A 1996-01-16 1997-01-10 An electrode structure of semiconductor integrated circuit and method for forming the package therefor SG52901A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00443696A JP3345541B2 (ja) 1996-01-16 1996-01-16 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
SG52901A1 true SG52901A1 (en) 1998-09-28

Family

ID=11584189

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997000057A SG52901A1 (en) 1996-01-16 1997-01-10 An electrode structure of semiconductor integrated circuit and method for forming the package therefor

Country Status (7)

Country Link
US (2) US5886409A (zh)
JP (1) JP3345541B2 (zh)
KR (1) KR100225468B1 (zh)
CN (1) CN1143384C (zh)
MY (1) MY127710A (zh)
SG (1) SG52901A1 (zh)
TW (1) TW339455B (zh)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679199B2 (ja) * 1996-07-30 2005-08-03 日本テキサス・インスツルメンツ株式会社 半導体パッケージ装置
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
JPH10313072A (ja) * 1997-05-12 1998-11-24 Hitachi Cable Ltd 半導体素子搭載用基板および半導体装置
US6034437A (en) * 1997-06-06 2000-03-07 Rohm Co., Ltd. Semiconductor device having a matrix of bonding pads
US5981312A (en) * 1997-06-27 1999-11-09 International Business Machines Corporation Method for injection molded flip chip encapsulation
JPH1154658A (ja) 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US6204564B1 (en) 1997-11-21 2001-03-20 Rohm Co., Ltd. Semiconductor device and method for making the same
WO1999036957A1 (fr) * 1998-01-19 1999-07-22 Citizen Watch Co., Ltd. Boitier de semiconducteur
JP2000021939A (ja) * 1998-06-29 2000-01-21 Mitsubishi Electric Corp 突起電極付半導体チップおよびその検査方法
JP2000138313A (ja) * 1998-10-30 2000-05-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6927491B1 (en) * 1998-12-04 2005-08-09 Nec Corporation Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board
US6177726B1 (en) * 1999-02-11 2001-01-23 Philips Electronics North America Corporation SiO2 wire bond insulation in semiconductor assemblies
US6528343B1 (en) 1999-05-12 2003-03-04 Hitachi, Ltd. Semiconductor device its manufacturing method and electronic device
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
US6583364B1 (en) * 1999-08-26 2003-06-24 Sony Chemicals Corp. Ultrasonic manufacturing apparatuses, multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards
JP3183653B2 (ja) * 1999-08-26 2001-07-09 ソニーケミカル株式会社 フレキシブル基板
US6249047B1 (en) * 1999-09-02 2001-06-19 Micron Technology, Inc. Ball array layout
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6388335B1 (en) * 1999-12-14 2002-05-14 Atmel Corporation Integrated circuit package formed at a wafer level
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
US6319811B1 (en) * 2000-02-22 2001-11-20 Scott Zimmerman Bond ply structure and associated process for interconnection of circuit layer pairs with conductive inks
EP1223612A4 (en) * 2000-05-12 2005-06-29 Matsushita Electric Ind Co Ltd PCB FOR SEMICONDUCTOR COMPONENTS, THEIR MANUFACTURING METHOD AND MANUFACTURING OF THE FITTING PLANT FOR THE PCB
JP3596864B2 (ja) * 2000-05-25 2004-12-02 シャープ株式会社 半導体装置
DE10029269B4 (de) * 2000-06-14 2005-10-13 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteiles aus gehäusebildenden Substraten
US6678952B2 (en) * 2000-08-03 2004-01-20 Tessera, Inc. Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof
US6548757B1 (en) 2000-08-28 2003-04-15 Micron Technology, Inc. Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies
US6653563B2 (en) * 2001-03-30 2003-11-25 Intel Corporation Alternate bump metallurgy bars for power and ground routing
JP2003068928A (ja) * 2001-08-28 2003-03-07 Kyocera Corp 高周波用配線基板の実装構造
JP4977937B2 (ja) * 2001-09-25 2012-07-18 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
US6661098B2 (en) * 2002-01-18 2003-12-09 International Business Machines Corporation High density area array solder microjoining interconnect structure and fabrication method
JP3943416B2 (ja) * 2002-03-07 2007-07-11 株式会社ルネサステクノロジ 半導体装置の製造方法
US7423336B2 (en) * 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
US6573595B1 (en) * 2002-04-24 2003-06-03 Scientek Corp. Ball grid array semiconductor package with resin coated metal core
JP3780996B2 (ja) * 2002-10-11 2006-05-31 セイコーエプソン株式会社 回路基板、バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、電気光学装置、並びに電子機器
US6734570B1 (en) 2003-01-24 2004-05-11 Gennum Corporation Solder bumped substrate for a fine pitch flip-chip integrated circuit package
US6972152B2 (en) * 2003-06-27 2005-12-06 Intel Corporation Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
US6911738B2 (en) * 2003-10-27 2005-06-28 Agilent Technologies, Inc. Method and apparatus for improving defective solder joint detection using x-ray inspection of printed assemblies
JP2006013229A (ja) * 2004-06-28 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
US7215031B2 (en) * 2004-11-10 2007-05-08 Oki Electric Industry Co., Ltd. Multi chip package
KR100652397B1 (ko) * 2005-01-17 2006-12-01 삼성전자주식회사 매개 인쇄회로기판을 사용하는 적층형 반도체 패키지
US7259581B2 (en) * 2005-02-14 2007-08-21 Micron Technology, Inc. Method for testing semiconductor components
JP4797482B2 (ja) * 2005-07-20 2011-10-19 ブラザー工業株式会社 配線基板及び配線基板の製造方法
AT9551U1 (de) * 2006-05-16 2007-11-15 Austria Tech & System Tech Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
US8030768B2 (en) * 2007-04-24 2011-10-04 United Test And Assembly Center Ltd. Semiconductor package with under bump metallization aligned with open vias
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
JP4917979B2 (ja) * 2007-07-09 2012-04-18 半導体特許株式会社 半導体装置及びその製造方法
JP5372346B2 (ja) 2007-07-18 2013-12-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US20090032925A1 (en) * 2007-07-31 2009-02-05 England Luke G Packaging with a connection structure
KR101637481B1 (ko) * 2009-04-10 2016-07-07 삼성전자주식회사 솔리드 스테이트 드라이브, 솔리드 스테이트 드라이브 장착 장치 및 컴퓨팅 시스템
DE112011101006T5 (de) * 2010-03-23 2013-01-24 Lear Corporation Leiterplatte mit Aluminium-Leiterbahnen, auf die eine lötbare Schicht aus Material aufgebracht ist
JP5355499B2 (ja) 2010-06-03 2013-11-27 株式会社東芝 半導体装置
JP5714280B2 (ja) * 2010-09-17 2015-05-07 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JPWO2013035655A1 (ja) * 2011-09-09 2015-03-23 株式会社村田製作所 モジュール基板
US8546925B2 (en) * 2011-09-28 2013-10-01 Texas Instruments Incorporated Synchronous buck converter having coplanar array of contact bumps of equal volume
TWI550732B (zh) * 2013-05-17 2016-09-21 南茂科技股份有限公司 晶片封裝結構的製作方法
JP2015088539A (ja) * 2013-10-29 2015-05-07 株式会社デンソー 半導体パッケージ、および、これを実装する配線基板
US9466578B2 (en) * 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
DE102018116531A1 (de) * 2017-10-23 2019-06-06 Samsung Electronics Co., Ltd. Anzeigevorrichtung, Halbleiterpackage und Film für ein Packagesubstrat
DE102019112883B4 (de) * 2019-05-16 2024-05-16 Pac Tech - Packaging Technologies Gmbh Beschichtungsbad zur stromlosen Beschichtung eines Substrats
US20220344225A1 (en) * 2021-04-23 2022-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including test line structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175450A (ja) * 1987-01-16 1988-07-19 Hitachi Ltd 気密封止型半導体装置
JPH01313969A (ja) * 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
JPH03116838A (ja) * 1989-09-29 1991-05-17 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
WO1992020097A1 (en) * 1991-04-26 1992-11-12 Citizen Watch Co., Ltd. Semiconductor device and manufacturing method therefor
US5583377A (en) * 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5382827A (en) * 1992-08-07 1995-01-17 Fujitsu Limited Functional substrates for packaging semiconductor chips
JP3267409B2 (ja) * 1992-11-24 2002-03-18 株式会社日立製作所 半導体集積回路装置
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US5581122A (en) * 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
US5598036A (en) * 1995-06-15 1997-01-28 Industrial Technology Research Institute Ball grid array having reduced mechanical stress

Also Published As

Publication number Publication date
KR100225468B1 (ko) 1999-10-15
JP3345541B2 (ja) 2002-11-18
TW339455B (en) 1998-09-01
US5886409A (en) 1999-03-23
US6137185A (en) 2000-10-24
CN1164128A (zh) 1997-11-05
CN1143384C (zh) 2004-03-24
KR970060464A (ko) 1997-08-12
JPH09199535A (ja) 1997-07-31
MY127710A (en) 2006-12-29

Similar Documents

Publication Publication Date Title
SG52901A1 (en) An electrode structure of semiconductor integrated circuit and method for forming the package therefor
US6977439B2 (en) Semiconductor chip stack structure
US6468836B1 (en) Laterally situated stress/strain relieving lead for a semiconductor chip package
US6531337B1 (en) Method of manufacturing a semiconductor structure having stacked semiconductor devices
US5646828A (en) Thin packaging of multi-chip modules with enhanced thermal/power management
US5831832A (en) Molded plastic ball grid array package
US6458625B2 (en) Multi chip semiconductor package and method of construction
US7691681B2 (en) Chip scale package having flip chip interconnect on die paddle
US6437990B1 (en) Multi-chip ball grid array IC packages
JP3491003B2 (ja) チップサイズパッケージ半導体
GB2307336B (en) Integrated circuit package and method of fabrication
GB9711555D0 (en) High density wirebond chip inter-connect for multi-chip modules
JPH08250653A (ja) マルチチップモジュールパッケージ
EP0590915B1 (en) Chip on board assembly
JPH1084076A (ja) 半導体装置およびその製造方法
EP0741411A3 (en) Method of fabricating multi-chip packages
WO2004012262A3 (en) Method for accommodating small minimum die in wire bonded area array packages
TW557520B (en) Semiconductor package module and process thereof
JPH1093013A (ja) 半導体装置
JPH08236665A (ja) 樹脂封止型半導体装置及びその製造方法
US20030122224A1 (en) Lead frame with dual thin film coated on inner lead terminal
JPS647645A (en) Semiconductor device and manufacture thereof
JP3397045B2 (ja) 半導体装置及びその製造方法
TW494505B (en) Manufacture method of chip package body
KR960043134A (ko) 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지 및 그 제조방법