JP3491003B2 - チップサイズパッケージ半導体 - Google Patents
チップサイズパッケージ半導体Info
- Publication number
- JP3491003B2 JP3491003B2 JP36412197A JP36412197A JP3491003B2 JP 3491003 B2 JP3491003 B2 JP 3491003B2 JP 36412197 A JP36412197 A JP 36412197A JP 36412197 A JP36412197 A JP 36412197A JP 3491003 B2 JP3491003 B2 JP 3491003B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- slot
- signal circuit
- wire bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims description 51
- 239000000919 ceramic Substances 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 7
- 238000000465 moulding Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000007998 bicine buffer Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
ージ(CSP:Chip Size Package)
半導体に関するもので、特に、従来のLOC(Lea
d On Chip)方式のチップをそのまま収容する
よう特殊に、考案された単一層セラミック基板(sub
strate)を採用しパッケージの厚さをより縮小し
生産性を向上させた新しいチップサイズパッケージ半導
体に関するものである。 【0002】【従来の技術】 一般に、半導体パッケージを小型化する
ために、チップサイズパッケージ半導体が提案されてき
た。チップサイズパッケージ半導体(以下、CSP半導
体と言う)は完成されたパッケージの大きさがチップの
大きさと同一であったり又は、チップの大きさより最大
1mmまたは20%程度大きいパッケージを示し、軽量
薄形の小型化を目的として種々の方式が開発されてき
た。 【0003】以下、従来の技術のCSP半導体の2種類
を簡単に説明する。図1はLOC方式のチップを収容す
る従来のCSP半導体を示している。前記CSP半導体
はLOC用チップ1と、前記チップ1の下面の所定位置
で付着テープ4を通じて支持するリードフレーム2とか
らなり、チップ1とリードフレーム2との間はワイヤボ
ンディング部3で相互接続されかつ、全体構成の支持、
保護、及び絶縁のためにモールディングコンパウンドで
成形される。 【0004】しかしながら、前記CSP半導体は予め一
定形態に形成された従来のリードフレームを利用するた
め、作業性が低下され、モールディング作業の際、チッ
プとリードフレームとの間にモールディングコンパウン
ドが充填されない空洞部が生じる恐れがありかつ、リー
ドフレームが変形される恐れがある。尚、トリム(Tr
im)工程時、リードフレームの付近にパッケージチッ
ピング(Chipping)及び亀裂が生じる可能性が
あり、パッケージの厚さを調整しにくい問題点があっ
た。 【0005】従って、上記問題点を解消するために、高
熱加工されたセラミック(Co−FiredCeram
ic)基板を用いたCSP構造が提案された。すなわ
ち、セラミック基板上に信号回路を形成した後、基板の
両面の信号経路をビアホール(via−hole)で連
結させた構造の上面にバンパが形成されたチップを実装
しアンダーフィルコーティングしたCSP半導体が提案
された。 【0006】しかし、前記セラミック基板を用いたCS
P半導体は基板を成形した後、基板両面の信号経路を連
結させるための孔を正確な位置に加工しにくいというこ
とにより、基板製作の費用が増大され、大量生産が困難
であり、基板とチップとの間にバンパが介入されること
でパッケージ厚さの縮小が制限される問題点があった。 【0007】 【発明が解決しようとする課題】前記のような問題点に
鑑み、本発明はチップを支持するためのベースとして作
用する特殊製作された単一層のセラミック基板を提供し
て従来のLOC方式の半導体チップをそのまま収容する
ことにより従来のCSPパッケージより軽量薄形に小型
化できるチップサイズ半導体を提供することにある。 【0008】本発明の他の目的はマルチ−形態の基板を
形成することにより低額で大量生産が可能なチップサイ
ズパッケージを提供することにある。 【0009】本発明のさらに他の目的はセラミック材料
から製作された基板を採用することにより、動作中に生
じた熱を容易に放出してその寿命を延長させうるチップ
サイズパッケージ半導体を提供することにある。 【0010】本発明のさらに他の目的は従来技術のよう
なモールディング工程ではなく、毛細管現象を用いたア
ンダーフィルコーティングでパッケージを組み立てパッ
ケージの信頼性を向上させかつ、工程時間を短縮させう
るチップサイズパッケージ半導体を提供することにあ
る。 【0011】 【課題を解決するための手段】前記目的を達成するため
に、本発明のチップサイズパッケージ半導体は、下面中
央部を縦断するように列を成す点線状に多数のワイヤボ
ンディングパッドが形成されたチップと;チップの下面
側にその上面が位置するようにチップと平行に配置さ
れ、前記多数のワイヤボンディングパッドを囲むことが
可能なサイズで上下面を貫通する長方形状のスロットが
中央部に設けられ、下面にのみ信号回路パターンが形成
された単一層のセラミック板材からなる基板と;ワイヤ
ボンディングパッドがスロット中央部の上方位置に整列
されるようにチップを基板の上面に付着し固定するため
の付着部材と;チップと基板を保持するための保持手段
と;基板の信号回路パターン上に装着され外部回路を形
成する複数のボール部材と、を含み;スロットを通じ
て、チップのワイヤボンディングパッドと基板の信号回
路パターンとがワイヤにより相互接続され内部回路を形
成するチップサイズパッケージ半導体であって;基板の
信号回路パターンが形成された面は、ワイヤボンディン
グ部とボール装着部とを除いた残り部分が誘電体物質で
塗布されており、付着部材はスロットの短辺長を超える
幅を有する付着用テープであり、スロットの長辺両側に
長辺に沿ってそれぞれ同じ長さだけ基板上面に取り付け
られており;保持手段は、チップの先端まで完全に詰め
込まれるように調節された量のアンダーフィルコーティ
ング用樹脂溶液をチップと基板との間に毛細管現象を利
用し自然に充填した後、熱処理により充填された樹脂溶
液をキュウアリングすることによって形成されたことを
特徴とする。 【0012】 【発明の実施の形態】以下、添付の図面を参照して本発
明に係るチップサイズパッケージ半導体のー実施の形態
の構成を詳細に説明する。図2(A)は本発明に係るC
SP半導体の全体形状を示す。図2(B)は図2(A)
のCSP半導体の断面構造を示す。図3は本発明に係る
CSP半導体の単一層セラミック基板の断面、上面、下
面構造を示す。図2及び図3の図面符号について以下に
示す。すなわち、21はチップ、22は基板、22aは
スロット,22bは基板上面,22cは基板下面,23
はテープ、24はワイヤ、25はボール(ボール部
材)、26はアンダーフィルコーティング部、30は信
号回路、31はボール装着部をそれぞれ示す。 【0013】図示のように、本発明はLOC方式のチッ
プ21と、中央部には所定大きさのスロット22aが形
成されかつ、下面22Cには信号回路30パターンが形
成され、チップ21を上面に実装する単一層セラミック
基板22と、チップ21を基板22の上面22bに取り
付けるためのLOC付着用テープ23と、基板22のス
ロット22aを通じてチップ21と基板22の下面22
cに形成された信号回路30のワイヤボンディング部を
接続させるワイヤ24と、信号回路30上に形成された
複数のボール装着部31に各々装着され外部回路を構成
するボール25と、前記構成要素を保持するためのアン
ダーフィルコーティング部26とからなる。 【0014】本発明の主要特徴である基板22を再び説
明すると、図3に示すように、基板22は単一層のセラ
ミック材であって、本発明に係るCSP半導体のベース
としての役割をし、中央部の所定位置に所定大きさのス
ロット22aが形成され、該上面22bには何のパター
ンも形成されず、その下面22cのみに信号回路30の
パターンが形成される。前記パターンの形成は無電解鍍
金法で基板下面22c上にニッケル鍍金してから、電解
鍍金で金鍍金を実施して形成させる。 【0015】信号回路30は図3で点線で示したワイヤ
ボンディング及び信号回路30の端部に形成されたボー
ル装着部31とからなり、前記ワイヤボンディング部は
スロット22aを通じてワイヤ24で直接チップ21に
接続され各々のボール装着部31にはボール25が各々
装着されPCB(Printed CircuitBo
ard)のパターンと繋がる。尚、基板(サブストレー
ト)22の下面22cには前記ワイヤボンディング部及
び前記ボール装着部を除いた部分は誘電体物質で塗布し
て絶縁させる。前述のように、本発明では下面22cに
のみ信号回路パターンが形成された単一層のセラミック
基板が適用され、チップ21と基板22との間にはバン
パの必要がなくワイヤ24で直接接続されパッケージの
厚さが従来のCSP半導体の場合よりさらに薄く製作す
ることが可能であり、基板22には、従来の基板上に正
確な位置に複数の孔が形成される必要がなく、中央部に
所定大きさの単一スロットが形成されるため、加工及び
製造がし易くなる。従って、製造費用の節減と大量生産
が可能となりうる。 【0016】セラミックの良好な熱放出によりチップ動
作の際に、発生する熱が容易に放出され熱適応力が低下
されるためチップの寿命を延長させうる。 【0017】以下、図4乃至図8を参照して、前述の単
一層セラミック基板を用いたCSP半導体を組み立てる
過程を説明する。 【0018】先ず、図4に示すように、基板22の上面
22bにLOC付着用テープ23を付着するが、中央に
形成されたスロット22aの両側に各々取り付ける。 【0019】次に、図5に示すように、基板22のスロ
ット22aの上部にチップ21の中心が整列されるよう
に、テープ23上にチップ21を装着させる。 【0020】次に、図6に示すように、基板22の中央
スロット22aから見えるチップ21に配列されている
ワイヤボンディングパッドと基板22の下面22cに露
出された信号回路30のワイヤボンディング部(点線で
表示された部分)をワイヤ24で接続する。(なお、図
6より、基板下面22cを上側にして図示してある。) 【0021】次に、ワイヤボンディングが完了された
後、図8に示すように、エポキシ系樹脂のようなコーテ
ィング溶液を注入しアンダーフィルコーティング部26
を形成する。この際、前記溶液は毛細管現象でチップ2
1と基板22が形成した狭い隙間内に自然に充填され
る。注入される前記溶液の量はチップ21の先端まで完
全に詰め込まれるように調節する。前記アンダーフィル
溶液の充填が完了された後には硬化させるためにキュア
リング(Curing)を実施する。その結果、従来の
CSP半導体でのモールディング作業が省略され、モー
ルディング作業中に生じるパッケージ内部の空洞部の発
生及び基板での変形問題が除去される効果がある。前記
効果は、前述のように、チップと基板(サブストレー
ト)との間に形成された隙間に毛細管現現象を利用して
コーティング溶液を自然に充填することにより達成され
うるものである。 【0022】次に、前述の工程が完了された製品は基板
22の下面22cの信号回路30の端部に形成された複
数のボール装着部31を溶剤(flux)で処理し、図
8に示すように、ボール装着部31上にボール25をの
せておき、赤外線加熱装置などで加熱してボール25を
装着する。 【0023】以上、各々の段階を経て一個の本発明に係
るCSP半導体が組み立てられる過程を説明したが、前
述のセラミック基板をマルチ(multi)基板形態に
製作して前述の組み立て段階でCSP半導体組立作業を
遂行した後、既形成された切断線に沿って切断すると、
単一CSP半導体の大量生産が可能となる。その結果、
CSP半導体組立工程全体の生産性及び作業性を向上さ
せることができる。 【0024】以上、本発明は前記実施の形態に限定され
るものではなく、その要旨を逸脱しない範囲で各種変更
可能である。 【0025】 【発明の効果】本発明は、従来のパッケージより信頼性
を向上させつつ、より厚さが薄いパッケージが得られ、
かつ熱放出能力が向上されることにより寿命が延長し、
製造工程の短縮、製造費用の節減、作業性及び生産性を
向上させる効果がある。
る。 【図2】本発明に係るチップサイズパッケージを示す斜
視図(A)及び断面図(B)である。 【図3】本発明に係るチップサイズパッケージ半導体の
基板を示す側面図(A)、上部平面図(B)及び下部平
面図(C)である。 【図4】図3の基板上部にLOC付着用テープが取り付
けられた組み立て状態を示す断面図(A)及び平面図
(B)である。 【図5】図4の組み立て状態でテープ上にチップが設置
された組み立て状態を示す断面図(A)及び平面図
(B)である。 【図6】図5の組み立て状態で基板とチップとの間をワ
イヤで接続した組み立て状態を示す断面図(A)及び平
面図(B)である。 【図7】図6の組み立て状態でアンダーフィル(und
er−fill)溶液でコーティングした状態を示す断
面図(A)及び平面図(B)である。 【図8】図7の組み立て状態で基板下面ボール装着部に
ボールが装着され組み立て完了された状態を示す断面図
(A)及び平面図(B)である。 【符号の説明】 21 チップ 22 基板 22a スロット 22b 基板上面 22c 基板下面 23 テープ 24 ワイヤ 25 ボール,ボール部材 26 アンダーフィルコーティング部 30 信号回路 31 ボール装着部
Claims (1)
- (57)【特許請求の範囲】 【請求項1】 下面中央部を縦断するように列を成す点
線状に多数のワイヤボンディングパッドが形成されたチ
ップと、 前記チップの下面側にその上面が位置するようにチップ
と平行に配置され、前記多数のワイヤボンディングパッ
ドを囲むことが可能なサイズで上下面を貫通する長方形
状のスロットが中央部に設けられ、下面にのみ信号回路
パターンが形成された単一層のセラミック板材からなる
基板と、 前記ワイヤボンディングパッドが前記スロット中央部の
上方位置に整列されるように前記チップを前記基板の上
面に付着し固定するための付着部材と、 前記チップと前記基板を保持するための保持手段と、 前記基板の信号回路パターン上に装着され外部回路を形
成する複数のボール部材と、を含み、 前記スロットを通じて、チップのワイヤボンディングパ
ッドと基板の信号回路パターンとがワイヤにより相互接
続され内部回路を形成するチップサイズパッケージ半導
体であって、 前記基板の信号回路パターンが形成された面は、前記ワ
イヤボンディング部とボール装着部とを除いた残り部分
が誘電体物質で塗布されており、 前記付着部材は前記スロットの短辺長を超える幅を有す
る付着用テープであり、スロットの長辺両側に長辺に沿
ってそれぞれ同じ長さだけ基板上面に取り付けられてお
り、 前記保持手段は、チップの先端まで完全に詰め込まれる
ように調節された量のアンダーフィルコーティング用樹
脂溶液を前記チップと前記基板との間に毛細管現象を利
用し自然に充填した後、熱処理により充填された樹脂溶
液をキュウアリングすることによって形成された ことを
特徴とするチップサイズパッケージ半導体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1996P67617 | 1996-12-18 | ||
KR1019960067617A KR100248792B1 (ko) | 1996-12-18 | 1996-12-18 | 단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10275880A JPH10275880A (ja) | 1998-10-13 |
JP3491003B2 true JP3491003B2 (ja) | 2004-01-26 |
Family
ID=19488975
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP36412197A Expired - Fee Related JP3491003B2 (ja) | 1996-12-18 | 1997-12-17 | チップサイズパッケージ半導体 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5920118A (ja) |
JP (1) | JP3491003B2 (ja) |
KR (1) | KR100248792B1 (ja) |
CN (1) | CN1190795A (ja) |
GB (1) | GB2320616B (ja) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861290B1 (en) * | 1995-12-19 | 2005-03-01 | Micron Technology, Inc. | Flip-chip adaptor package for bare die |
USRE43112E1 (en) | 1998-05-04 | 2012-01-17 | Round Rock Research, Llc | Stackable ball grid array package |
KR100340060B1 (ko) * | 1998-06-02 | 2002-07-18 | 박종섭 | 티에스오피와호환성이있는씨에스피핀배치방법및그에의한핀배치구조 |
JP2000156435A (ja) | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6414391B1 (en) * | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
US6541872B1 (en) * | 1999-01-11 | 2003-04-01 | Micron Technology, Inc. | Multi-layered adhesive for attaching a semiconductor die to a substrate |
WO2000048444A2 (de) * | 1999-02-16 | 2000-08-24 | Wichmann Workx Ag Information Technology | Häusung für ein halbleiterchip |
US6387732B1 (en) | 1999-06-18 | 2002-05-14 | Micron Technology, Inc. | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby |
KR100570512B1 (ko) * | 1999-08-06 | 2006-04-13 | 삼성전자주식회사 | 칩 스케일형 반도체 패키지 |
KR100629678B1 (ko) * | 1999-08-30 | 2006-09-29 | 삼성전자주식회사 | 칩 스케일 패키지 제조 방법 |
JP3501281B2 (ja) * | 1999-11-15 | 2004-03-02 | 沖電気工業株式会社 | 半導体装置 |
DE19954888C2 (de) | 1999-11-15 | 2002-01-10 | Infineon Technologies Ag | Verpackung für einen Halbleiterchip |
US6242283B1 (en) * | 1999-12-30 | 2001-06-05 | Siliconware Precision Industries Co., Ltd. | Wafer level packaging process of semiconductor |
JP2001223324A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
US6577015B1 (en) * | 2000-03-07 | 2003-06-10 | Micron Technology, Inc. | Partial slot cover for encapsulation process |
KR100344833B1 (ko) | 2000-04-03 | 2002-07-20 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그의 제조방법 |
US6531335B1 (en) * | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
KR100408391B1 (ko) | 2000-06-09 | 2003-12-06 | 삼성전자주식회사 | 전원 배선을 개선한 볼그리드 어레이 패키지 반도체 장치 |
KR100343432B1 (ko) | 2000-07-24 | 2002-07-11 | 한신혁 | 반도체 패키지 및 그 패키지 방법 |
EP1205973A1 (en) * | 2000-11-10 | 2002-05-15 | United Test Center Inc. | Low-profile semiconductor device and method for manufacturing the same |
JP4018375B2 (ja) | 2000-11-30 | 2007-12-05 | 株式会社東芝 | 半導体装置 |
US6828223B2 (en) * | 2001-12-14 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co. | Localized slots for stress relieve in copper |
DE10201204A1 (de) * | 2002-01-14 | 2003-07-31 | Infineon Technologies Ag | Verfahren zum Herstellen eines Schutzes für Chipkanten und Anordnung zum Schutz von Chipkanten |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US7109588B2 (en) * | 2002-04-04 | 2006-09-19 | Micron Technology, Inc. | Method and apparatus for attaching microelectronic substrates and support members |
JP3678212B2 (ja) * | 2002-05-20 | 2005-08-03 | ウシオ電機株式会社 | 超高圧水銀ランプ |
US6984545B2 (en) * | 2002-07-22 | 2006-01-10 | Micron Technology, Inc. | Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask |
DE10238581B4 (de) * | 2002-08-22 | 2008-11-27 | Qimonda Ag | Halbleiterbauelement |
US6969914B2 (en) * | 2002-08-29 | 2005-11-29 | Micron Technology, Inc. | Electronic device package |
TW567566B (en) * | 2002-10-25 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Window-type ball grid array semiconductor package with lead frame as chip carrier and method for fabricating the same |
US6755700B2 (en) * | 2002-11-12 | 2004-06-29 | Modevation Enterprises Inc. | Reset speed control for watercraft |
US8278751B2 (en) * | 2005-02-08 | 2012-10-02 | Micron Technology, Inc. | Methods of adhering microfeature workpieces, including a chip, to a support member |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
TW200807583A (en) * | 2006-07-20 | 2008-02-01 | Chipmos Technologies Inc | Chip package and manufacturing method threrof |
US20090134504A1 (en) * | 2007-11-28 | 2009-05-28 | Walton Advanced Engineering, Inc. | Semiconductor package and packaging method for balancing top and bottom mold flows from window |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH067810B2 (ja) * | 1988-09-09 | 1994-02-02 | 三洋電機株式会社 | ショーケースの温度計取付構造 |
DE3911711A1 (de) * | 1989-04-10 | 1990-10-11 | Ibm | Modul-aufbau mit integriertem halbleiterchip und chiptraeger |
US5107328A (en) * | 1991-02-13 | 1992-04-21 | Micron Technology, Inc. | Packaging means for a semiconductor die having particular shelf structure |
JP2932785B2 (ja) * | 1991-09-20 | 1999-08-09 | 富士通株式会社 | 半導体装置 |
US5434750A (en) * | 1992-02-07 | 1995-07-18 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package for certain non-square die shapes |
US5384689A (en) * | 1993-12-20 | 1995-01-24 | Shen; Ming-Tung | Integrated circuit chip including superimposed upper and lower printed circuit boards |
JPH08321565A (ja) * | 1995-05-25 | 1996-12-03 | Hitachi Ltd | 半導体装置 |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
GB2312988A (en) * | 1996-05-10 | 1997-11-12 | Memory Corp Plc | Connecting a semiconductor die to a carrier |
-
1996
- 1996-12-18 KR KR1019960067617A patent/KR100248792B1/ko not_active IP Right Cessation
-
1997
- 1997-12-17 JP JP36412197A patent/JP3491003B2/ja not_active Expired - Fee Related
- 1997-12-17 US US08/992,259 patent/US5920118A/en not_active Expired - Lifetime
- 1997-12-18 GB GB9726869A patent/GB2320616B/en not_active Expired - Lifetime
- 1997-12-18 CN CN97114383A patent/CN1190795A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
GB9726869D0 (en) | 1998-02-18 |
CN1190795A (zh) | 1998-08-19 |
KR100248792B1 (ko) | 2000-03-15 |
GB2320616B (en) | 2002-01-16 |
JPH10275880A (ja) | 1998-10-13 |
KR19980048962A (ko) | 1998-09-15 |
GB2320616A (en) | 1998-06-24 |
US5920118A (en) | 1999-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3491003B2 (ja) | チップサイズパッケージ半導体 | |
US5888847A (en) | Technique for mounting a semiconductor die | |
US7615871B2 (en) | Method and apparatus for attaching microelectronic substrates and support members | |
US6781243B1 (en) | Leadless leadframe package substitute and stack package | |
US7413926B2 (en) | Methods of making microelectronic packages | |
US6642609B1 (en) | Leadframe for a semiconductor device having leads with land electrodes | |
EP2005470B1 (en) | Lead frame based, over-molded semiconductor package with integrated through hole technology (tht) heat spreader pin(s) and associated method of manufacturing | |
JP3478139B2 (ja) | リードフレームの製造方法 | |
CN107305879B (zh) | 半导体器件及相应的方法 | |
JP2001024133A (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
JP3655338B2 (ja) | 樹脂封止型半導体装置及びその製造方法 | |
JP3164391B2 (ja) | 垂直リードオンチップパッケージ | |
JPH08241940A (ja) | 半導体装置およびその製造方法 | |
JP3454192B2 (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
KR950006441Y1 (ko) | 고 발열용 반도체 패키지 | |
KR100481926B1 (ko) | 일반칩형반도체패키지및플립칩형반도체패키지와그제조방법 | |
KR100321149B1 (ko) | 칩사이즈 패키지 | |
JP2008147267A (ja) | 半導体装置とその製造方法、および放熱板付きリードフレーム | |
JPH02202042A (ja) | 樹脂封止型半導体装置 | |
KR100604332B1 (ko) | 반도체 패키지 및 그 제조방법 | |
KR19990056345A (ko) | 반도체 칩 패키지 | |
KR970072341A (ko) | 본딩패드의 범프와 내장된 리드 프레임이 접착된 패키지 및 그의 제조방법 | |
JPH04299561A (ja) | リードフレームおよびこれを用いた半導体装置 | |
JP2000150723A (ja) | 半導体装置およびその製造方法 | |
JPH11251481A (ja) | 半導体装置用セラミックパッケージおよび半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071114 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081114 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091114 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091114 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101114 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101114 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111114 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111114 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121114 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121114 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131114 Year of fee payment: 10 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |