JPH10275880A - チップサイズパッケージ半導体 - Google Patents

チップサイズパッケージ半導体

Info

Publication number
JPH10275880A
JPH10275880A JP36412197A JP36412197A JPH10275880A JP H10275880 A JPH10275880 A JP H10275880A JP 36412197 A JP36412197 A JP 36412197A JP 36412197 A JP36412197 A JP 36412197A JP H10275880 A JPH10275880 A JP H10275880A
Authority
JP
Japan
Prior art keywords
chip
substrate
signal circuit
package semiconductor
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP36412197A
Other languages
English (en)
Other versions
JP3491003B2 (ja
Inventor
Byoung Sik Kong
炳 植 孔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH10275880A publication Critical patent/JPH10275880A/ja
Application granted granted Critical
Publication of JP3491003B2 publication Critical patent/JP3491003B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

(57)【要約】 【課題】 単一層のセラミックを提供してＬＯＣ方式の
半導体チップを収容することにより、従来のチップサイ
ズパッケージより軽量薄形小型化できかつ、信頼性をよ
り向上させうるチップサイズパッケージを提供すること
にある。 【解決手段】 ワイヤボンディングパッドがその中央部
に形成されたチップと、上記中央部に所定大きさの四角
形状のスロットが形成された所定大きさのセラミック板
材であって、上記チップを上面に設ける基板と、上記チ
ップを上記基板の上面に取り付けるための付着部材と、
上記信号回路の上記ボール装着部に各々装着され外部回
路と繋がるボールと、上記チップと上記基板との間に充
填され上記チップ及び基板を保持するコーティング部を
具備することを特徴とする。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はチップサイズパッケ
ージ(CSP:Chip Size Package) 半導体に関するもので、
特に、従来のＬＯＣ(Lead On Chip)方式のチップをその
まま収容するよう特殊に、考案された単一層セラミック
基板(sub-strate)を採用しパッケージの厚さをより縮小
し生産性を向上させた新しいチップサイズパッケージ半
導体に関するものである。
【０００２】一般に、半導体パッケージを小型化するた
めに、チップサイズパッケージ半導体が提案されてき
た。チップサイズパッケージ半導体（以下、ＣＳＰ半導
体と言う）は完成されたパッケージの大きさがチップの
大きさと同一であったり又は、チップの大きさより最大
１mmまたは２０％程度大きいパッケージを示し、軽量薄
形の小型化を目的として種々の方式が開発されてきた。
【０００３】以下、従来の技術のＣＳＰ半導体の２種類
を簡単に説明する。図１はＬＯＣ方式のチップを収容す
る従来のＣＳＰ半導体を示している。前記ＣＳＰ半導体
はＬＯＣ用チップ１と、前記チップ１の下面の所定位置
で付着テープ４を通じて支持するリードフレーム２とか
らなり、前記チップ１とリードフレーム２との間はワイ
ヤボンディング部３で相互接続されかつ、全体構成の支
持、保護、及び絶縁のためにモールディングコンパウン
ドで成形される。
【０００４】しかしながら、前記ＣＳＰ半導体は予め一
定形態に形成された従来のリードフレームを利用するた
め、作業性が低下され、モールディング作業の際、チッ
プとリードフレームとの間にモールディングコンパウン
ドが充填されない空洞部が生じる恐れがありかつ、リー
ドフレームが変形される恐れがある。尚、トリム(Trim)
工程時、リードフレームの付近にパッケージチップピン
グ(Chipping)及び亀裂が生じる可能性があり、パッケー
ジの厚さを調整しにくい問題点があった。
【０００５】従って、前記問題点を解消するために、高
熱加工されたセラミック(Co-FiredCeramic)基板を用い
たＣＳＰ構造が提案された。すなわち、セラミック基板
上に信号回路を形成した後、基板の両面の信号経路をビ
アホール(via-hole)で連結させた構造の上面にバンパが
形成されたチップを実装しアンダーフィルコーティング
したＣＳＰ半導体が提案された。
【０００６】しかし、前記セラミック基板を用いたＣＳ
Ｐ半導体は基板を成形した後、基板両面の信号経路を連
結させるための孔を正確な位置に加工しにくいというこ
とにより、基板制作の費用が増大され、大量生産が困難
であり、基板とチップとの間にバンパが介入されること
でパッケージ厚さの縮小が制限される問題点があった。
【０００７】
【発明が解決しようとする課題】前記のような問題点に
鑑み、本発明はチップを支持するためのベースとして作
用する特殊制作された単一層のセラミック基板を提供し
て従来のＬＯＣ方式の半導体チップをそのまま収容する
ことにより従来のＣＳＰパッケージより軽量薄形に小型
化できるチップサイズ半導体を提供することにある。
【０００８】本発明の他の目的はマルチ−形態の基板を
形成することにより低額で大量生産が可能なチップサイ
ズパッケージを提供することにある。
【０００９】本発明のさらに他の目的はセラミック材料
から制作された基板を採用することにより、動作中に生
じられた熱を容易に放出してその寿命延長させうるチッ
プサイズパッケージ半導体を提供することにある。
【００１０】本発明のさらに他の目的は従来技術のよう
なモールディング工程ではなく、毛細管現状を用いたア
ンダーフィルコーティングでパッケージを組み立てパッ
ケージの信頼性を向上させかつ、工程時間を短縮させう
るチップサイズパッケージ半導体を提供することにあ
る。
【００１１】
【課題を解決するための手段】前記目的を達成するため
に、本発明のチップサイズパッケージ半導体はワイヤボ
ンディングパッドがその中央部に形成されたチップと、
前記中央部に所定形状のスロットが形成され少なくとも
一つの表面に信号回路が形成され、前記チップを上面に
設置する基板と、前記チップのボンディングパッドが前
記スロット上部に整列されるよう前記チップを前記基板
の上面に付着し固定する付着部材と、前記チップと前記
基板を保持するための保持手段と、前記基板の信号回路
パターン上に装着され外部回路を形成する複数のボール
部材を含み、前記スロットを通じてチップのボンディン
グパッド及び基板の信号回路がワイヤによって相互接続
され内部回路を形成することを特徴とする。
【００１２】また、前記信号回路にはチップから引き出
されたワイヤが接続される複数のワイヤボンディング部
及び前記ボール部材が定着され固定されるボール装着部
を含んでなることを特徴とする。
【００１３】また、前記基板の信号回路が形成された面
には前記ワイヤボンディング部及びボール装着部を除い
た残り部分が誘電体物質で塗布されることを特徴とす
る。
【００１４】また、前記基板は所定の大きさと形状を有
するセラミックの板材で形成されることを特徴とする。
【００１５】さらに、前記保持手段は所定量のコーティ
ング用樹脂溶液を前記チップと前記基板との間に注入し
充填させてから熱処理により充填された樹脂溶液をキュ
ウアリングすることにより形成されることを特徴とす
る。
【００１６】
【発明の実施の形態】以下、添付の図面を参照して本発
明に係るチップサイズパッケージ半導体のー実施の形態
の構成を詳細に説明する。図２（Ａ）は本発明に係るＣ
ＳＰ半導体の全体形状を示す。図２（Ｂ）は図２（Ａ）
のＣＳＰ半導体の０断面構造を示す。図３は本発明に係
るＣＳＰ半導体の単一層セラミック基板の断面、上面、
下面構造を示す。図２及び図３の図面符号について以下
に示す。すなわち、２１はチップ、２２は基板、２２ａ
はスロット，２２ｂは基板上面，２２ｃは基板下面，２
３はテープ、２４はワイヤ、２５はボール（ボール部
材）、２６はアンダーフィルコーティング部、３０は信
号回路、３１はボール装着部をそれぞれ示す。
【００１７】図示のように、本発明はＬＯＣ方式のチッ
プ２１と、中央部には所定大きさのスロット２２ａが形
成されかつ、下面２２Ｃには信号回路３０パターンが形
成され、前記チップ２１を上面に実装する単一層セラミ
ック基板２２と、前記チップ２１を前記基板２２の上面
２２ｂに取り付けるためのＬＯＣ付着用テープ２３と、
前記基板２２のスロット２２ａを通じて前記チップ２１
と前記基板２２の下面２２ｃに形成された信号回路３０
のワイヤボンディング部を接続させるワイヤ２４と、前
記信号回路３０上に形成された複数のボール装着部３１
に各々装着され外部回路を構成するボール２５と、前記
構成要素を保持するためのアンダーフィルコーティング
部２６とからなる。
【００１８】本発明の主要特徴である前記基板２２を再
び説明すると、図３に示すように、前記基板２２は単一
層のセラミック材であって、本発明に係るＣＳＰ半導体
のベースとして役割をし、中央部の所定位置に所定大き
さのスロット２２ａが形成され、該上面２２ｂには何の
パターンも形成されず、その下面２２ｃのみに信号回路
３０のパターンが形成される。前記パターンの形成は無
電解鍍金法で基板下面２２ｃ上にニッケル鍍金してか
ら、電解鍍金で金鍍金を実施して形成させる。
【００１９】前記信号回路３０は図３で点線で示したワ
イヤボンディング及び前記信号回路３０の端部に形成さ
れたボール装着部３１とからなり、前記ワイヤボンディ
ング部は前記スロット２２ａを通じてワイヤ２４で直接
チップ２１に接続され各々の前記ボール装着部３１には
ボール２５が各々装着されＰＣＢ(Printed Circuit Boa
rd) のパターンと繋がる。尚、前記基板（サブ−ストレ
ート）２２の下面２２ｃには前記ワイヤボンディング部
及び前記ボール装着部を除いた部分は誘電体物質で塗布
して絶縁させる。前述のように、本発明では下面２２ｃ
にのみ信号回路パターンが形成された単一層のセラミッ
ク基板が適用され、チップ２１と基板２２との間にはバ
ンパの必要がなくワイヤ２４で直接接続されパッケージ
の厚さが従来のＣＳＰ半導体の場合よりさらに薄く制作
することが可能であり、前記基板２２には、従来の基板
上に正確な位置に複数の孔が形成される必要がなく、中
央部に所定大きさの単一スロットが形成されるため、加
工及び制作がし易くなる。従って、制作費用の節減と大
量生産が可能となりうる。
【００２０】セラミックの良好な熱放出によりチップ動
作の際に、発生する熱が容易に放出され熱適応力が低下
されるためチップの寿命を延長させうる。
【００２１】以下、図４乃至図８を参照して、前述の単
一層セラミック基板を用いたＣＳＰ半導体を組み立てる
過程を説明する。
【００２２】先ず、図４に示すように、前記基板２２の
上面２２ｂにＬＯＣ付着用テープ２３を付着するが、中
央に形成されたスロット２２ａの両側に各々取り付け
る。
【００２３】次に、図５に示すように、前記基板２２の
スロット２２ａの上部にチップ２１の中心が整列される
ように、前記テープ２３上にチップ２１を装着させる。
【００２４】次に、図６に示すように、前記基板２２の
中央スロット２２ａから見えるチップ２１に配列されて
いるワイヤボンディングパッドと前記基板２２の下面２
２ｃに露出された信号回路３０のワイヤボンディング部
（点線で表示された部分）をワイヤ２４で接続する。
（なお、図６より、基板下面２２ｃを上側にして図示し
てある。）
【００２５】次に、ワイヤボンディングが完了された
後、図８に示すように、エポキシ系樹脂のようなコーテ
ィング溶液を注入しアンダーフィルコーティング部２６
を形成する。この際、前記溶液は毛細管状でチップ２１
と基板２２が形成した狭い隙間内に自然に充填される。
注入される前記溶液の量はチップ２１の先端まで完全に
詰め込まれるように調節する。前記アンダーフィル溶液
の充填が完了された後には硬化させるためにキュアリン
グ(Curing)を実施する。その結果、従来のＣＳＰ半導体
でのモールディング作業が省略され、モールディング作
業中に生じられるパッケージ内部の空洞部の発生及び基
板での変形問題が除去される効果がある。前記効果は、
前述のように、チップと基板（サブ−ストレート）との
間に形成された隙間に毛細管現状を利用してコーティン
グ溶液を自然に充填することにより達成されうるもので
ある。
【００２６】次に、前述の工程が完了された製品は前記
基板２２の下面２２ｃの信号回路３０の端部に形成され
た複数のボール装着部３１を溶剤(flux)で処理し、図８
に示すように、前記ボール装着部３１上にボール２５を
のせておき、赤外線加熱装置などで加熱してボール２５
を装着する。
【００２７】以上、各々の段階を掛けて一個の本発明に
係るＣＳＰ半導体が組み立てられる過程を説明したが、
前述のセラミック基板をマルチ(multi) 基板形態に制作
して前述の組み立て段階でＣＳＰ半導体組立作業を遂行
した後、既形成された切断線に沿って切断すると、単一
ＣＳＰ半導体の大量生産が可能となる。その結果、ＣＳ
Ｐ半導体組立工程全体に掛けた生産性及び作業性を向上
させることができる。
【００２８】以上、本発明は前記実施の形態に限定され
るものではなく、その要旨を逸脱しない範囲で各種変更
可能である。
【００２９】
【発明の効果】本発明は、従来のパッケージより信頼性
を向上させつつ、より厚さが薄いパッケージが得られ、
かつ熱放出能力が向上されることにより寿命が延長し、
制作工程で工程の短縮、制作費用の節減、作業性及び生
産性を向上させる効果がある。
【図面の簡単な説明】
【図１】従来のチップサイズ半導体を示す断面図であ
る。
【図２】本発明に係るチップサイズパッケージを示す斜
視図（Ａ）及び断面図（Ｂ）である。
【図３】本発明に係るチップサイズパッケージ半導体の
基板を示す側面図（Ａ）、上部平面図（Ｂ）及び下部平
面図（Ｃ）である。
【図４】図３の基板上部にＬＯＣ付着用テープが取り付
けられた組み立て状態を示す断面図（Ａ）及び平面図
（Ｂ）である。
【図５】図４の組み立て状態でテープ上にチップが設置
された組み立て状態を示す断面図（Ａ）及び平面図
（Ｂ）である。
【図６】図５の組み立て状態で基板とチップとの間をワ
イヤで接続した組み立て状態を示す断面図（Ａ）及び平
面図（Ｂ）である。
【図７】図６の組み立て状態でアンダーフィル(under-f
ill)溶液でコーティングした状態を示す断面図（Ａ）及
び平面図（Ｂ）である。
【図８】図７の組み立て状態で基板下面ボール装着部に
ボールが装着され組み立て完了された状態を示す断面図
（Ａ）及び平面図（Ｂ）である。
【符号の説明】
２１ チップ ２２ 基板 ２２ａ スロット ２２ｂ 基板上面 ２２ｃ 基板下面 ２３ テープ ２４ ワイヤ ２５ ボール，ボール部材 ２６ アンダーフィルコーティング部 ３０ 信号回路 ３１ ボール装着部

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】 ワイヤボンディングパッドがその中央部
    に形成されたチップと、 前記中央部に所定形状のスロットが形成され少なくとも
    一つの表面に信号回路が形成され、前記チップを上面に
    設ける基板と、 前記チップのボンディングパッドが前記スロットの上部
    に整列されるように前記チップを前記基板の上面の付着
    し固定するための付着部材と、 前記チップと前記基板を保持するための保持手段と、 前記基板の信号回路パターン上に装着され外部回路を形
    成する複数のボール部材を含み、 前記スロットを通じて、チップのボンディングパッド及
    び、基板の信号回路がワイヤにより相互接続され内部回
    路を形成することを特徴とするチップサイズパッケージ
    半導体。
  2. 【請求項２】 前記信号回路にはチップから引き出され
    たワイヤが接続される複数のワイヤボンディング部及び
    前記ボール部材が定着され固定されるボール装着部を備
    えてなることを特徴とする請求項１記載のチップサイズ
    パッケージ半導体。
  3. 【請求項３】 前記基板の信号回路が形成された面には
    前記ワイヤボンディング部及びボール装着部を除いた残
    り部分が誘電体物質で塗布されることを特徴とする請求
    項２記載のチップサイズパッケージ半導体。
  4. 【請求項４】 前記基板は所定の大きさと形状を有する
    セラミックの板材で形成されることを特徴とする請求項
    １，２又は３記載のチップサイズパッケージ半導体。
  5. 【請求項５】 前記保持手段は所定量のコーティング用
    樹脂溶液を前記チップと前記基板との間に注入し充填さ
    せてから熱処理により充填された樹脂溶液をキュウアリ
    ングすることにより形成されることを特徴とする請求項
    １，２，３又は４記載のチップサイズパッケージ半導
    体。
JP36412197A 1996-12-18 1997-12-17 チップサイズパッケージ半導体 Expired - Fee Related JP3491003B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1996P67617 1996-12-18
KR1019960067617A KR100248792B1 (ko) 1996-12-18 1996-12-18 단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체

Publications (2)

Publication Number Publication Date
JPH10275880A true JPH10275880A (ja) 1998-10-13
JP3491003B2 JP3491003B2 (ja) 2004-01-26

Family

ID=19488975

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Application Number Title Priority Date Filing Date
JP36412197A Expired - Fee Related JP3491003B2 (ja) 1996-12-18 1997-12-17 チップサイズパッケージ半導体

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Country Link
US (1) US5920118A (ja)
JP (1) JP3491003B2 (ja)
KR (1) KR100248792B1 (ja)
CN (1) CN1190795A (ja)
GB (1) GB2320616B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333564B1 (en) 1998-06-22 2001-12-25 Fujitsu Limited Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes
KR100570512B1 (ko) * 1999-08-06 2006-04-13 삼성전자주식회사 칩 스케일형 반도체 패키지
KR100629678B1 (ko) * 1999-08-30 2006-09-29 삼성전자주식회사 칩 스케일 패키지 제조 방법

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861290B1 (en) 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
USRE43112E1 (en) 1998-05-04 2012-01-17 Round Rock Research, Llc Stackable ball grid array package
KR100340060B1 (ko) * 1998-06-02 2002-07-18 박종섭 티에스오피와호환성이있는씨에스피핀배치방법및그에의한핀배치구조
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6541872B1 (en) * 1999-01-11 2003-04-01 Micron Technology, Inc. Multi-layered adhesive for attaching a semiconductor die to a substrate
AU2294100A (en) * 1999-02-16 2000-09-04 Microelectronic Packaging Dresden Gmbh Packaging for a semiconductor chip
US6387732B1 (en) 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
JP3501281B2 (ja) * 1999-11-15 2004-03-02 沖電気工業株式会社 半導体装置
DE19954888C2 (de) * 1999-11-15 2002-01-10 Infineon Technologies Ag Verpackung für einen Halbleiterchip
US6242283B1 (en) * 1999-12-30 2001-06-05 Siliconware Precision Industries Co., Ltd. Wafer level packaging process of semiconductor
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6577015B1 (en) * 2000-03-07 2003-06-10 Micron Technology, Inc. Partial slot cover for encapsulation process
KR100344833B1 (ko) 2000-04-03 2002-07-20 주식회사 하이닉스반도체 반도체 패키지 및 그의 제조방법
US6531335B1 (en) * 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
KR100408391B1 (ko) * 2000-06-09 2003-12-06 삼성전자주식회사 전원 배선을 개선한 볼그리드 어레이 패키지 반도체 장치
KR100343432B1 (ko) 2000-07-24 2002-07-11 한신혁 반도체 패키지 및 그 패키지 방법
EP1205973A1 (en) * 2000-11-10 2002-05-15 United Test Center Inc. Low-profile semiconductor device and method for manufacturing the same
JP4018375B2 (ja) 2000-11-30 2007-12-05 株式会社東芝 半導体装置
US6828223B2 (en) * 2001-12-14 2004-12-07 Taiwan Semiconductor Manufacturing Co. Localized slots for stress relieve in copper
DE10201204A1 (de) * 2002-01-14 2003-07-31 Infineon Technologies Ag Verfahren zum Herstellen eines Schutzes für Chipkanten und Anordnung zum Schutz von Chipkanten
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
US7109588B2 (en) * 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
JP3678212B2 (ja) * 2002-05-20 2005-08-03 ウシオ電機株式会社 超高圧水銀ランプ
US6984545B2 (en) * 2002-07-22 2006-01-10 Micron Technology, Inc. Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
DE10238581B4 (de) * 2002-08-22 2008-11-27 Qimonda Ag Halbleiterbauelement
US6969914B2 (en) * 2002-08-29 2005-11-29 Micron Technology, Inc. Electronic device package
TW567566B (en) * 2002-10-25 2003-12-21 Siliconware Precision Industries Co Ltd Window-type ball grid array semiconductor package with lead frame as chip carrier and method for fabricating the same
US6755700B2 (en) * 2002-11-12 2004-06-29 Modevation Enterprises Inc. Reset speed control for watercraft
US8278751B2 (en) 2005-02-08 2012-10-02 Micron Technology, Inc. Methods of adhering microfeature workpieces, including a chip, to a support member
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
TW200807583A (en) * 2006-07-20 2008-02-01 Chipmos Technologies Inc Chip package and manufacturing method threrof
US20090134504A1 (en) * 2007-11-28 2009-05-28 Walton Advanced Engineering, Inc. Semiconductor package and packaging method for balancing top and bottom mold flows from window

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067810B2 (ja) * 1988-09-09 1994-02-02 三洋電機株式会社 ショーケースの温度計取付構造
DE3911711A1 (de) * 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
US5107328A (en) * 1991-02-13 1992-04-21 Micron Technology, Inc. Packaging means for a semiconductor die having particular shelf structure
JP2932785B2 (ja) * 1991-09-20 1999-08-09 富士通株式会社 半導体装置
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
JPH08321565A (ja) * 1995-05-25 1996-12-03 Hitachi Ltd 半導体装置
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
GB2312988A (en) * 1996-05-10 1997-11-12 Memory Corp Plc Connecting a semiconductor die to a carrier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333564B1 (en) 1998-06-22 2001-12-25 Fujitsu Limited Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes
KR100570512B1 (ko) * 1999-08-06 2006-04-13 삼성전자주식회사 칩 스케일형 반도체 패키지
KR100629678B1 (ko) * 1999-08-30 2006-09-29 삼성전자주식회사 칩 스케일 패키지 제조 방법

Also Published As

Publication number Publication date
GB2320616A (en) 1998-06-24
KR19980048962A (ko) 1998-09-15
CN1190795A (zh) 1998-08-19
US5920118A (en) 1999-07-06
KR100248792B1 (ko) 2000-03-15
JP3491003B2 (ja) 2004-01-26
GB9726869D0 (en) 1998-02-18
GB2320616B (en) 2002-01-16

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