AU2294100A - Packaging for a semiconductor chip - Google Patents
Packaging for a semiconductor chipInfo
- Publication number
- AU2294100A AU2294100A AU22941/00A AU2294100A AU2294100A AU 2294100 A AU2294100 A AU 2294100A AU 22941/00 A AU22941/00 A AU 22941/00A AU 2294100 A AU2294100 A AU 2294100A AU 2294100 A AU2294100 A AU 2294100A
- Authority
- AU
- Australia
- Prior art keywords
- packaging
- semiconductor chip
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE29902754U DE29902754U1 (en) | 1998-02-20 | 1999-02-16 | Package for a semiconductor chip |
DE29902754 | 1999-02-16 | ||
PCT/EP2000/000678 WO2000048444A2 (en) | 1999-02-16 | 2000-01-28 | Packaging for a semiconductor chip |
Publications (1)
Publication Number | Publication Date |
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AU2294100A true AU2294100A (en) | 2000-09-04 |
Family
ID=8069480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU22941/00A Abandoned AU2294100A (en) | 1999-02-16 | 2000-01-28 | Packaging for a semiconductor chip |
Country Status (2)
Country | Link |
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AU (1) | AU2294100A (en) |
WO (1) | WO2000048444A2 (en) |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0428260A (en) * | 1990-05-23 | 1992-01-30 | Matsushita Electric Ind Co Ltd | Method of mounting semiconductor chip |
US5703405A (en) * | 1993-03-15 | 1997-12-30 | Motorola, Inc. | Integrated circuit chip formed from processing two opposing surfaces of a wafer |
JP3146849B2 (en) * | 1994-05-27 | 2001-03-19 | 松下電器産業株式会社 | Electronic component and method of manufacturing electronic component |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
JPH09260441A (en) * | 1996-03-26 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device |
US6667560B2 (en) * | 1996-05-29 | 2003-12-23 | Texas Instruments Incorporated | Board on chip ball grid array |
KR100231276B1 (en) * | 1996-06-21 | 1999-11-15 | 황인길 | Semiconductor package structure and its manufacturing method |
KR100248792B1 (en) * | 1996-12-18 | 2000-03-15 | 김영환 | Chip size semiconductor package using single layer ceramic substrate |
JPH1154537A (en) * | 1997-07-31 | 1999-02-26 | Mitsui High Tec Inc | Semiconductor device and its manufacture |
JPH11219984A (en) * | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
-
2000
- 2000-01-28 AU AU22941/00A patent/AU2294100A/en not_active Abandoned
- 2000-01-28 WO PCT/EP2000/000678 patent/WO2000048444A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2000048444A2 (en) | 2000-08-24 |
WO2000048444A3 (en) | 2003-05-22 |
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Date | Code | Title | Description |
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MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |