SG160403A1 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG160403A1
SG160403A1 SG201001798-6A SG2010017986A SG160403A1 SG 160403 A1 SG160403 A1 SG 160403A1 SG 2010017986 A SG2010017986 A SG 2010017986A SG 160403 A1 SG160403 A1 SG 160403A1
Authority
SG
Singapore
Prior art keywords
thermal expansion
core
temperature changes
multilayer substrate
coefficient
Prior art date
Application number
SG201001798-6A
Other languages
English (en)
Inventor
Masahiro Wada
Hiroyuki Tanaka
Hiroshi Hirose
Itoh Teppei
Kenya Tachibana
Original Assignee
Sumitomo Bakelite Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co filed Critical Sumitomo Bakelite Co
Publication of SG160403A1 publication Critical patent/SG160403A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
SG201001798-6A 2006-09-13 2007-09-05 Semiconductor device SG160403A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006248473 2006-09-13

Publications (1)

Publication Number Publication Date
SG160403A1 true SG160403A1 (en) 2010-04-29

Family

ID=39183681

Family Applications (1)

Application Number Title Priority Date Filing Date
SG201001798-6A SG160403A1 (en) 2006-09-13 2007-09-05 Semiconductor device

Country Status (9)

Country Link
US (1) US8008767B2 (enExample)
EP (1) EP1956648A4 (enExample)
JP (2) JP4802246B2 (enExample)
KR (2) KR20080091086A (enExample)
CN (1) CN101356643B (enExample)
CA (1) CA2630824C (enExample)
SG (1) SG160403A1 (enExample)
TW (1) TW200830486A (enExample)
WO (1) WO2008032620A1 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941245B2 (en) * 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
JP5408131B2 (ja) * 2008-06-12 2014-02-05 住友ベークライト株式会社 半導体素子搭載基板
US8399773B2 (en) * 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US8502399B2 (en) * 2009-06-22 2013-08-06 Sumitomo Bakelite Co., Ltd. Resin composition for encapsulating semiconductor and semiconductor device
CN101735562B (zh) * 2009-12-11 2012-09-26 广东生益科技股份有限公司 环氧树脂组合物及其制备方法及采用其制作的层压材料及覆铜箔层压板
JP2011222946A (ja) * 2010-03-26 2011-11-04 Sumitomo Bakelite Co Ltd 回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法
JP5593897B2 (ja) * 2010-07-12 2014-09-24 住友ベークライト株式会社 回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法
JP2012049423A (ja) * 2010-08-30 2012-03-08 Sumitomo Bakelite Co Ltd 回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法
KR101728203B1 (ko) 2010-09-30 2017-04-18 히타치가세이가부시끼가이샤 접착제 조성물, 반도체 장치의 제조 방법 및 반도체 장치
KR101464454B1 (ko) * 2010-10-22 2014-11-21 히타치가세이가부시끼가이샤 접착제 조성물, 반도체 장치의 제조 방법 및 반도체 장치
US20120156474A1 (en) * 2010-12-20 2012-06-21 E. I. Du Pont De Nemours And Company Article having curable coating comprising imidazolium monocarboxylate salt
US8969732B2 (en) * 2011-09-28 2015-03-03 Ibiden Co., Ltd. Printed wiring board
JP6281184B2 (ja) * 2012-03-14 2018-02-21 住友ベークライト株式会社 金属張積層板、プリント配線基板、半導体パッケージ、および半導体装置
US9196356B2 (en) * 2013-03-14 2015-11-24 Globalfoundries Singapore Pte. Ltd. Stackable non-volatile memory
US9218875B2 (en) 2013-03-14 2015-12-22 Globalfoundries Singapore Pte. Ltd. Resistive non-volatile memory
KR102130547B1 (ko) * 2013-03-27 2020-07-07 삼성디스플레이 주식회사 가요성 기판 및 이를 포함하는 가요성 표시 장치
US9155191B2 (en) 2013-05-31 2015-10-06 Qualcomm Incorporated Substrate comprising inorganic material that lowers the coefficient of thermal expansion (CTE) and reduces warpage
KR102116962B1 (ko) 2013-06-25 2020-05-29 삼성전자주식회사 반도체 패키지
US9778510B2 (en) * 2013-10-08 2017-10-03 Samsung Electronics Co., Ltd. Nanocrystal polymer composites and production methods thereof
MX2016011858A (es) * 2014-03-28 2016-12-02 Huntsman Advanced Mat Licensing (Switzerland) Gmbh Un procedimiento para la preparacion de un articulo de material compuesto con fibra reforzada, los articulos compuestos obtenidos y el uso de los mismos.
JP6212011B2 (ja) * 2014-09-17 2017-10-11 東芝メモリ株式会社 半導体製造装置
TWI526129B (zh) * 2014-11-05 2016-03-11 Elite Material Co Ltd Multilayer printed circuit boards with dimensional stability
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
JP6793517B2 (ja) * 2016-10-17 2020-12-02 株式会社ダイセル シート状プリプレグ
US20190259731A1 (en) * 2016-11-09 2019-08-22 Unisem (M) Berhad Substrate based fan-out wafer level packaging
US20180130768A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
JP6991014B2 (ja) * 2017-08-29 2022-01-12 キオクシア株式会社 半導体装置
KR102397902B1 (ko) * 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
JP7135364B2 (ja) * 2018-03-23 2022-09-13 三菱マテリアル株式会社 絶縁回路基板、及び、絶縁回路基板の製造方法
JP7289108B2 (ja) * 2019-02-21 2023-06-09 パナソニックIpマネジメント株式会社 半導体封止材料及び半導体装置
EP4007458B1 (en) * 2019-07-31 2023-08-09 Fuji Corporation Method for manufacturing circuit wiring by three-dimensional additive manufacturing
JP7346150B2 (ja) 2019-08-09 2023-09-19 キヤノン株式会社 インクジェット記録ヘッドおよびインクジェット記録装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5224265A (en) * 1991-10-29 1993-07-06 International Business Machines Corporation Fabrication of discrete thin film wiring structures
JP3238340B2 (ja) 1996-12-04 2001-12-10 住友ベークライト株式会社 液状エポキシ樹脂封止材料
JPH11116659A (ja) 1997-10-20 1999-04-27 Sumitomo Bakelite Co Ltd デバイス封止用紫外線硬化型液状樹脂組成物
JPH11233571A (ja) 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びアンダーフィル材並びに熱硬化性フィルム材
US6225704B1 (en) * 1999-02-12 2001-05-01 Shin-Etsu Chemical Co., Ltd. Flip-chip type semiconductor device
JP2001313314A (ja) * 2000-04-28 2001-11-09 Sony Corp バンプを用いた半導体装置、その製造方法、および、バンプの形成方法
JP2002050718A (ja) * 2000-08-04 2002-02-15 Hitachi Ltd 半導体装置
US7192997B2 (en) 2001-02-07 2007-03-20 International Business Machines Corporation Encapsulant composition and electronic package utilizing same
US6512182B2 (en) * 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
JPWO2003021664A1 (ja) * 2001-08-31 2005-07-07 株式会社日立製作所 半導体装置、構造体及び電子装置
US7038142B2 (en) * 2002-01-24 2006-05-02 Fujitsu Limited Circuit board and method for fabricating the same, and electronic device
AU2003234394A1 (en) * 2002-05-23 2003-12-12 3M Innovative Properties Company Nanoparticle filled underfill
JP2004035668A (ja) 2002-07-02 2004-02-05 Sanyo Chem Ind Ltd 注型用エポキシ樹脂組成物
JP2004134679A (ja) 2002-10-11 2004-04-30 Dainippon Printing Co Ltd コア基板とその製造方法、および多層配線基板
JP2004277671A (ja) * 2003-03-19 2004-10-07 Sumitomo Bakelite Co Ltd プリプレグおよびそれを用いたプリント配線板
JP2005097524A (ja) 2003-09-05 2005-04-14 Sumitomo Bakelite Co Ltd 樹脂組成物、プリプレグおよび積層板
US7285321B2 (en) * 2003-11-12 2007-10-23 E.I. Du Pont De Nemours And Company Multilayer substrates having at least two dissimilar polyimide layers, useful for electronics-type applications, and compositions relating thereto
JP4400191B2 (ja) * 2003-11-28 2010-01-20 住友ベークライト株式会社 樹脂組成物およびそれを用いた基板
US7148577B2 (en) * 2003-12-31 2006-12-12 Intel Corporation Materials for electronic devices
JP2005236067A (ja) 2004-02-20 2005-09-02 Dainippon Printing Co Ltd 配線基板と配線基板の製造方法、および半導パッケージ
JP2005236220A (ja) 2004-02-23 2005-09-02 Dainippon Printing Co Ltd 配線基板と配線基板の製造方法、および半導パッケージ
JP2005254680A (ja) 2004-03-12 2005-09-22 Sumitomo Bakelite Co Ltd 積層板の連続製造方法および装置
JP4108643B2 (ja) * 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
CN100531528C (zh) * 2004-05-27 2009-08-19 揖斐电株式会社 多层印刷配线板
JP4449608B2 (ja) 2004-07-09 2010-04-14 凸版印刷株式会社 半導体装置
JP2006080356A (ja) 2004-09-10 2006-03-23 Toshiba Corp 半導体装置及びその製造方法
US7335608B2 (en) 2004-09-22 2008-02-26 Intel Corporation Materials, structures and methods for microelectronic packaging
US7459782B1 (en) * 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US20070298260A1 (en) * 2006-06-22 2007-12-27 Kuppusamy Kanakarajan Multi-layer laminate substrates useful in electronic type applications

Also Published As

Publication number Publication date
EP1956648A4 (en) 2011-09-21
EP1956648A1 (en) 2008-08-13
TWI374523B (enExample) 2012-10-11
KR101195408B1 (ko) 2012-10-29
JP4802246B2 (ja) 2011-10-26
CN101356643A (zh) 2009-01-28
US8008767B2 (en) 2011-08-30
US20090267212A1 (en) 2009-10-29
KR20080091086A (ko) 2008-10-09
JP2010004050A (ja) 2010-01-07
CA2630824C (en) 2013-01-08
KR20110000761A (ko) 2011-01-05
CA2630824A1 (en) 2008-03-20
TW200830486A (en) 2008-07-16
WO2008032620A1 (en) 2008-03-20
CN101356643B (zh) 2012-04-25
JPWO2008032620A1 (ja) 2010-01-21

Similar Documents

Publication Publication Date Title
SG160403A1 (en) Semiconductor device
US8202765B2 (en) Achieving mechanical and thermal stability in a multi-chip package
TWI575678B (zh) 電路結構翹曲減小的製造方法其製品
WO2010117701A3 (en) Optical device with large thermal impedance
TW200744120A (en) Semiconductor structure, semiconductor wafer and method for fabricating the same
TW200705621A (en) Interposer and semiconductor device
US8614517B2 (en) Semiconductor device and method of manufacturing the same
WO2012177934A3 (en) Integrated circuits with components on both sides of a selected substrate and methods of fabrication
WO2010025218A3 (en) Composite semiconductor substrates for thin-film device layer transfer
TW200625572A (en) Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
MY151034A (en) Semicondutor package, core layer material, buildup layer material, and sealing resin composition
WO2011139875A3 (en) Tce compensation for ic package substrates for reduced die warpage assembly
WO2006127163A3 (en) Method of detachable direct bonding at low temperatures
TW200802799A (en) Semiconductor device
WO2010090820A3 (en) Ic package with capacitors disposed on an interposal layer
TWI263256B (en) Flip-chip semiconductor device
TW200635009A (en) Semiconductor packages and methods of manufacturing thereof
WO2008078516A1 (ja) 酸化シリコン薄膜の製造装置及び形成方法
SG171678A1 (en) Wafer level package integration and method
WO2004059728A3 (en) Method of fabricating an integrated circuit and semiconductor chip
WO2010141351A3 (en) Wafer bonding technique in nitride semiconductors
JP2009111373A5 (enExample)
US10529820B2 (en) Method for gallium nitride on diamond semiconductor wafer production
SG151203A1 (en) Integrated circuit package system with warp-free chip
ATE502397T1 (de) Halbleiterbauelement