SG159493A1 - Method for trimming a structure obtained by the assembly of two plates - Google Patents

Method for trimming a structure obtained by the assembly of two plates

Info

Publication number
SG159493A1
SG159493A1 SG201000395-2A SG2010003952A SG159493A1 SG 159493 A1 SG159493 A1 SG 159493A1 SG 2010003952 A SG2010003952 A SG 2010003952A SG 159493 A1 SG159493 A1 SG 159493A1
Authority
SG
Singapore
Prior art keywords
plate
trimming
structure obtained
thinning
pedestal
Prior art date
Application number
SG201000395-2A
Other languages
English (en)
Inventor
Marc Zussy
Bernard Aspar
Chrystelle Lagahe-Blanchard
Hubert Moriceau
Original Assignee
Commissariat A Laeenergie Atom
Tracit Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat A Laeenergie Atom, Tracit Technologies filed Critical Commissariat A Laeenergie Atom
Publication of SG159493A1 publication Critical patent/SG159493A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Micromachines (AREA)
  • Bending Of Plates, Rods, And Pipes (AREA)
  • Connection Of Plates (AREA)
  • Surface Treatment Of Glass (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
SG201000395-2A 2004-12-28 2005-12-22 Method for trimming a structure obtained by the assembly of two plates SG159493A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0413979A FR2880184B1 (fr) 2004-12-28 2004-12-28 Procede de detourage d'une structure obtenue par assemblage de deux plaques

Publications (1)

Publication Number Publication Date
SG159493A1 true SG159493A1 (en) 2010-03-30

Family

ID=34953374

Family Applications (1)

Application Number Title Priority Date Filing Date
SG201000395-2A SG159493A1 (en) 2004-12-28 2005-12-22 Method for trimming a structure obtained by the assembly of two plates

Country Status (8)

Country Link
US (2) US8329048B2 (ja)
EP (1) EP1831923B1 (ja)
JP (1) JP5197017B2 (ja)
KR (1) KR101291086B1 (ja)
CN (1) CN101084577B (ja)
FR (1) FR2880184B1 (ja)
SG (1) SG159493A1 (ja)
WO (1) WO2006070160A1 (ja)

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FR2957190B1 (fr) 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
FR2967295B1 (fr) * 2010-11-05 2013-01-11 Soitec Silicon On Insulator Procédé de traitement d'une structure multicouche
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FR3076393A1 (fr) * 2017-12-28 2019-07-05 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile
DE102018111200A1 (de) * 2018-05-09 2019-11-14 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung eines wenigstens teilweise gehäusten Halbleiterwafers
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
FR3085957B1 (fr) 2018-09-14 2021-01-29 Commissariat Energie Atomique Procede de collage temporaire avec adhesif thermoplastique incorporant une couronne rigide
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
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Also Published As

Publication number Publication date
JP2008526038A (ja) 2008-07-17
US8628674B2 (en) 2014-01-14
CN101084577B (zh) 2010-06-16
US20130078785A1 (en) 2013-03-28
FR2880184B1 (fr) 2007-03-30
US20090095399A1 (en) 2009-04-16
JP5197017B2 (ja) 2013-05-15
FR2880184A1 (fr) 2006-06-30
CN101084577A (zh) 2007-12-05
EP1831923A1 (fr) 2007-09-12
EP1831923B1 (fr) 2019-05-22
WO2006070160A1 (fr) 2006-07-06
KR20070110261A (ko) 2007-11-16
KR101291086B1 (ko) 2013-08-01
US8329048B2 (en) 2012-12-11

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