KR960026267A - 고융점금속박막의 형성방법 - Google Patents

고융점금속박막의 형성방법 Download PDF

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KR960026267A
KR960026267A KR1019950055584A KR19950055584A KR960026267A KR 960026267 A KR960026267 A KR 960026267A KR 1019950055584 A KR1019950055584 A KR 1019950055584A KR 19950055584 A KR19950055584 A KR 19950055584A KR 960026267 A KR960026267 A KR 960026267A
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high melting
substrate
point metal
melting point
gas
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다까아끼 미야모또
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이데이 노브유끼
소니 가부시끼가이샤
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric

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Abstract

본 발명은 고융점금속 할로겐화물과 수소가스를 함유하는 가스혼합물을 플라즈마 화학적 기상성장법으로 처리함으로써 기판상에 고융점금속박막을 형성하는 방법이며, 그 방법은 그 프로세서의 초기단계에서 수소가스에 대한 고융점금속 할로겐화물의 혼합비를 비교적 작은값으로 조정하는 공정과, 프로세서의 초기단계 이후에, 수소가스에 대한 고융점금속 할로겐화물의 혼합비를 비교적 큰 값으로 조정하는 공정과, 를 포함하여 이루어진다.

Description

고융점금속박막의 형성방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 제1프로세스에 의해서, 제2도에 나타난 반도체 웨이퍼로부터 자연산화막을 제거한 후에 실리콘기판 표면의 하부분 위에 제1티탄막층이 형성된 반도체웨이퍼를 개략적으로 나타내는 단면도이다.

Claims (9)

  1. 고융점금속 할로겐화물과 수소가스를 함유하는 가스혼합물을 플라즈마 화학적 기상성장법을 받게 함으로써 기판상에 고유점금속박막을 형성하는 방법에 있어서, 프로세스의 초기단계에서 수소가스에 대한 상기 고융점금속 할로겐화물의 혼합비를 비교적 작은값으로 조정하는 공정과, 프로세스의 초기단계 이후, 수소가스에 대한 상기 고융점금속 할로겐화물의 상기 혼합비를 비교적 큰 값으로 조정하는 공정과, 를 포함하여 이루어지는 것을 특징으로 하는 고융점금속박막의 형성방법.
  2. 제1항에 있어서, 고융점금속박막의 형성에 앞서 상기 기판상의 지연산화막을 제거하는 공정과 상기 기판이 대기중에 접하게 되는 것을 방지하면서, 상기 고융점금속박막의 형성을 수행하는 공정과,를 더한층 포함하는 것을 특징으로 하는 고융점금속박막의 형성방법.
  3. 기판상에 고융점금속박막을 형성하는 방법에 있어서, 상기 기판상의 자연산화막을 미리 제거시키는 공정과, 상기 기판이 대기중에 접하게 되는 것을 방지하면서, 분자내에 적어도 질소원자를 함유하는 가스를 사용하여 상기 기판의 표면을 질화시키는 공정과, 고융점금속 할로겐화물과 수소가스를 함유하는 가스혼합물을 플라즈마 화학적 기상성장법을 받게 하여 상기 기판상에 상기 고융점금속박막을 퇴적시키는 공정과,를 포함하는 것을 특징으로 하는 고융점금속박막의 형성방법.
  4. 제3항에 있어서, 분자내에 적어도 질소원자를 함유하는 상기 가스는 질소가스와 암모니아가스와 히드라진가스로 구성되는 그룹에서 선택된 적어도 하나의 가스물질인 것을 특징으로 하는 고융점금속박막의 형성방법.
  5. 제2항에 있어서, 기판상의 상기 자연산화막은 상기 기판을 수소가스와 실란가스와 아르곤가스로 구성된 그룹에서 선택된 적어도 하나의 가스물질이 사용된 플라즈마처리를 받게 함으로써 제거되는 것을 특징으로 하는 고융점금속박막의 형성방법.
  6. 제1항에 있어서, 상기 기판내측의 실리콘물질이 그 표면의 적어도 한부분에 노출되는 것을 특징으로 하는 고융점금속박막의 형성방법.
  7. 제1항에 있어서, 상기 기판상의 알루미늄계 물질이 그 표면의 적어도 한부분에 노출되는 것을 특징으로 하는 고융점금속박막의 형성방법.
  8. 제7항에 있어서, 수소가스와 실란가스와 아르곤가스로 구성된 그룹에서 선택된 적어도 하나의 가스물질을 사용해서 상기 기판을 플라즈마처리하여 기판상의 상기 자연산화막을 제거시키는 공정과, 이어서 상기 기판의 표면을 수소가스와 상기 고융점금속 할로겐화물을 함유하는 가스혼합물로 처리하여 상기 기판의 알루미늄계 물질의 표면상에 퇴적된 자연산화막을 제거시키는 공정과,를 더한층 포함하는 것을 특징으로 하는 고융점금속박막의 형성방법.
  9. 제1항에 있어서, 상기 고융점금속박막은 티탄박막인 것을 특징으로 하는 고융점금속박막의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950055584A 1994-12-26 1995-12-23 고융점금속박막의 형성방법 KR960026267A (ko)

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JP94-323187 1994-12-26
JP6323187A JPH08176823A (ja) 1994-12-26 1994-12-26 高融点金属薄膜の成膜方法

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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6132564A (en) * 1997-11-17 2000-10-17 Tokyo Electron Limited In-situ pre-metallization clean and metallization of semiconductor wafers
JPH1012729A (ja) * 1996-06-27 1998-01-16 Nec Corp 半導体装置の製造方法
GB2319532B (en) * 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
JPH10237662A (ja) * 1996-12-24 1998-09-08 Sony Corp 金属膜のプラズマcvd方法、および金属窒化物膜の形成方法ならびに半導体装置
KR19980060529A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 금속 배선 형성 방법
US6221792B1 (en) * 1997-06-24 2001-04-24 Lam Research Corporation Metal and metal silicide nitridization in a high density, low pressure plasma reactor
US5976976A (en) 1997-08-21 1999-11-02 Micron Technology, Inc. Method of forming titanium silicide and titanium by chemical vapor deposition
US6054768A (en) * 1997-10-02 2000-04-25 Micron Technology, Inc. Metal fill by treatment of mobility layers
JP3221381B2 (ja) * 1997-11-21 2001-10-22 日本電気株式会社 半導体装置の製造方法
TW507015B (en) * 1997-12-02 2002-10-21 Applied Materials Inc In-situ, preclean of wafers prior to a chemical vapor deposition titanium deposition step
JP3381774B2 (ja) * 1997-12-24 2003-03-04 東京エレクトロン株式会社 CVD−Ti膜の成膜方法
US6143362A (en) * 1998-02-25 2000-11-07 Micron Technology, Inc. Chemical vapor deposition of titanium
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
US6010961A (en) * 1998-02-26 2000-01-04 Micron Technology, Inc. Methods of establishing electrical communication with substrate node locations, semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry, and semiconductor assemblies
KR100484253B1 (ko) * 1998-06-27 2005-07-07 주식회사 하이닉스반도체 반도체 장치의 타이타늄막 형성방법
JP3191290B2 (ja) * 1999-01-07 2001-07-23 日本電気株式会社 半導体装置の製造方法及び半導体装置の製造方法に用いられるプラズマcvd装置
CA2308944C (en) 1999-05-19 2008-04-01 Smith International, Inc. Well reference apparatus and method
US6499537B1 (en) 1999-05-19 2002-12-31 Smith International, Inc. Well reference apparatus and method
US6543536B2 (en) 1999-05-19 2003-04-08 Smith International, Inc. Well reference apparatus and method
US7088037B2 (en) * 1999-09-01 2006-08-08 Micron Technology, Inc. Field emission display device
US6365515B1 (en) * 2000-08-28 2002-04-02 Micron Technology, Inc. Chemical vapor deposition process
US6573181B1 (en) 2000-10-26 2003-06-03 Applied Materials, Inc. Method of forming contact structures using nitrogen trifluoride preclean etch process and a titanium chemical vapor deposition step
US7169704B2 (en) * 2002-06-21 2007-01-30 Samsung Electronics Co., Ltd. Method of cleaning a surface of a water in connection with forming a barrier layer of a semiconductor device
JP2010056567A (ja) * 2002-10-17 2010-03-11 Tokyo Electron Ltd 成膜方法
WO2007023950A1 (ja) * 2005-08-26 2007-03-01 Hitachi, Ltd. 半導体装置の製造方法
JP5207615B2 (ja) * 2006-10-30 2013-06-12 東京エレクトロン株式会社 成膜方法および基板処理装置
JP5211503B2 (ja) 2007-02-16 2013-06-12 富士通セミコンダクター株式会社 半導体装置の製造方法
KR20090001000A (ko) * 2007-06-29 2009-01-08 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
JP2009141227A (ja) * 2007-12-08 2009-06-25 Tokyo Electron Ltd チタン膜の成膜方法及びチタン膜の成膜装置
US8227708B2 (en) * 2009-12-14 2012-07-24 Qualcomm Incorporated Via structure integrated in electronic substrate
KR20130010362A (ko) * 2011-07-18 2013-01-28 삼성전자주식회사 반도체 장치의 제조방법
FR2979749B1 (fr) * 2011-09-07 2014-03-28 St Microelectronics Crolles 2 Procede de realisation d'une couche de siliciure dans le fond d'une tranchee, et dispositif pour la mise en oeuvre dudit procede
JP2014090051A (ja) * 2012-10-30 2014-05-15 Renesas Electronics Corp 半導体装置およびその製造方法
KR101529788B1 (ko) * 2013-12-10 2015-06-29 성균관대학교산학협력단 금속 칼코게나이드 박막 및 그 제조방법
US9446947B2 (en) * 2014-08-25 2016-09-20 Texas Instruments Incorporated Use of metal native oxide to control stress gradient and bending moment of a released MEMS structure
US9947753B2 (en) 2015-05-15 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
US9887160B2 (en) * 2015-09-24 2018-02-06 International Business Machines Corporation Multiple pre-clean processes for interconnect fabrication
US10504834B2 (en) * 2018-03-01 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure and the method of forming the same
US10685842B2 (en) * 2018-05-18 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Selective formation of titanium silicide and titanium nitride by hydrogen gas control
DE102019103699A1 (de) * 2018-11-30 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Finnen-Feldeffekttransistor-Bauelement und Verfahren zu dessen Herstellung
US11107690B2 (en) * 2018-11-30 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
CN112397442A (zh) * 2019-08-13 2021-02-23 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4331710A (en) * 1980-09-08 1982-05-25 Fujitsu Limited Method of forming an insulation film on semiconductor device surface
US4361599A (en) * 1981-03-23 1982-11-30 National Semiconductor Corporation Method of forming plasma etched semiconductor contacts
JPS6289873A (ja) * 1985-10-14 1987-04-24 Semiconductor Energy Lab Co Ltd 透明導電膜形成方法
US4715937A (en) * 1986-05-05 1987-12-29 The Board Of Trustees Of The Leland Stanford Junior University Low-temperature direct nitridation of silicon in nitrogen plasma generated by microwave discharge
JPH0745649B2 (ja) * 1987-04-15 1995-05-17 出光石油化学株式会社 接着剤の製造方法
KR0145302B1 (ko) * 1988-04-28 1998-08-17 카자마 젠쥬 얇은 막의 형성방법
US5174881A (en) * 1988-05-12 1992-12-29 Mitsubishi Denki Kabushiki Kaisha Apparatus for forming a thin film on surface of semiconductor substrate
JPH02162722A (ja) * 1988-12-16 1990-06-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US5162262A (en) * 1989-03-14 1992-11-10 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
US5155063A (en) * 1990-10-09 1992-10-13 Nec Corporation Method of fabricating semiconductor device including an al/tin/ti contact
US5238872A (en) * 1990-12-11 1993-08-24 Samsung Semiconductor, Inc. Barrier metal contact architecture
DE69225082T2 (de) * 1991-02-12 1998-08-20 Matsushita Electronics Corp Halbleiter-Vorrichtung mit Verdrahtung der verbesserten Zuverlässigkeit und Verfahren zu ihner Herstellung
US5173327A (en) * 1991-06-18 1992-12-22 Micron Technology, Inc. LPCVD process for depositing titanium films for semiconductor devices
JPH05152292A (ja) * 1991-11-30 1993-06-18 Sony Corp 配線形成方法
JPH05326517A (ja) * 1992-05-20 1993-12-10 Fujitsu Ltd 半導体装置の製造方法
JPH06323052A (ja) * 1993-03-17 1994-11-22 Patago Ag 盗難防止装置
US5443995A (en) * 1993-09-17 1995-08-22 Applied Materials, Inc. Method for metallizing a semiconductor wafer
KR0179677B1 (ko) * 1993-12-28 1999-04-15 사토 후미오 반도체장치 및 그 제조방법
US5403434A (en) * 1994-01-06 1995-04-04 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafer
JP3328416B2 (ja) * 1994-03-18 2002-09-24 富士通株式会社 半導体装置の製造方法と製造装置
US5665640A (en) * 1994-06-03 1997-09-09 Sony Corporation Method for producing titanium-containing thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer

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