KR950021220A - 반도체 소자의 텅스텐 실리사이드 형성방법 - Google Patents

반도체 소자의 텅스텐 실리사이드 형성방법 Download PDF

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Publication number
KR950021220A
KR950021220A KR1019930028140A KR930028140A KR950021220A KR 950021220 A KR950021220 A KR 950021220A KR 1019930028140 A KR1019930028140 A KR 1019930028140A KR 930028140 A KR930028140 A KR 930028140A KR 950021220 A KR950021220 A KR 950021220A
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South Korea
Prior art keywords
tungsten silicide
semiconductor device
sih
reactor
deposited
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KR1019930028140A
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English (en)
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KR970009867B1 (ko
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정성희
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김주용
현대전자산업 주식회사
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Priority to KR1019930028140A priority Critical patent/KR970009867B1/ko
Publication of KR950021220A publication Critical patent/KR950021220A/ko
Priority to US08/654,003 priority patent/US5726096A/en
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Publication of KR970009867B1 publication Critical patent/KR970009867B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 텅스텐 실리사이드를 형성하는 방법에 관한 것으로, 반도체 소자에서 소자의 속도(Speed)를 개선하기 위하여 폴리실리콘상에 텅스텐 실리사이드를 증착 형성할 때, 폴리실리콘이 형성된 웨이퍼를 반응로에 장착한 후, 반응로를 소정온도로 유지하고 WF6와 SiH4가스를 유입하여 텅스텐 실리사이드를 1차로 얇게 증착한 다음, 반응로에 SiH4가스를 다량 유입하여 1차로 증착된 텅스텐 실리사이드내에 존재하는 불소(F)이온을 증발시켜 제거하고, 다시 상기 1차로 증착된 텅스텐 실리사이드상에 2차로 상기 1차와 같은 분위기하에서 텅스텐 실리사이드를 증착한 후, 반응로에 SiH4가스를 다량 유입하여 불소이온을 제거하고, 이러한 공정을 텅스텐 실리사이드 소정두께가 될때까지 반복 실시하므로써, 텅스텐 실리사이드 내에 존재하는 불소이온으로 인한 후공정시 결함요인을 제거하므로 반도체 소자의 신뢰성을 증대시킬 수 있는 반도체 소자의 텅스텐 실리사이드를 형성하는 방법에 관해 기술된다.

Description

반도체 소자의 텅스텐 실리사이드 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 및 제1B도는 본 발명에 의한 반도체 소자의 텅스텐 실리사이드를 형성하는 단계를 설명하기 위해 도시한 단면도.

Claims (2)

  1. 반도체 소자의 전기적 특성을 향상시키기 위한 텅스텐 실리사이드 형성방법에 있어서, 도전층으로 사용될 폴리실리콘(3)이 증착된 웨이퍼(10)를 반응로에 장착한 다음, WF6와 SiH4가스를 이용한 CVD방법으로 텅스텐 실리사이드(4)를 설정된 두께보다 얇게 1차 증착한 후, 반응로에 SiH4가스를 유입하여 상기 1차 증착된 텅스텐 실리사이드(4)를 SiH4처리하여 불소를 제거하고, 다시 2차 증착 및 SiH4처리 공정을 반복적으로 실시하면서 설정된 두께의 텅스텐 실리사이드를 완성하는 것을 특징으로 하는 반도체 소장의 텅스텐 실리사이드 형성방법.
  2. 제1항에 있어서, 상기 불소제거를 위하여 수소화합물을 유입하여 텅스텐 실리사이드의 불소이온을 제거하는 것을 특징으로 하는 반도체 소장의 텅스텐 실리사이드 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930028140A 1993-12-17 1993-12-17 반도체 소자의 텅스텐 실리사이드 형성방법 KR970009867B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019930028140A KR970009867B1 (ko) 1993-12-17 1993-12-17 반도체 소자의 텅스텐 실리사이드 형성방법
US08/654,003 US5726096A (en) 1993-12-17 1996-05-28 Method for forming a tungsten silicide layer in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930028140A KR970009867B1 (ko) 1993-12-17 1993-12-17 반도체 소자의 텅스텐 실리사이드 형성방법

Publications (2)

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KR950021220A true KR950021220A (ko) 1995-07-26
KR970009867B1 KR970009867B1 (ko) 1997-06-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332124B1 (ko) * 1995-03-07 2002-09-04 주식회사 하이닉스반도체 반도체소자의게이트전극형성방법

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665611A (en) * 1996-01-31 1997-09-09 Micron Technology, Inc. Method of forming a thin film transistor using fluorine passivation
KR100272259B1 (ko) * 1996-10-23 2000-12-01 김영환 반도체소자의실리사이드막의형성방법
JP4101901B2 (ja) * 1997-04-25 2008-06-18 シャープ株式会社 半導体装置の製造方法
US6210813B1 (en) 1998-09-02 2001-04-03 Micron Technology, Inc. Forming metal silicide resistant to subsequent thermal processing
US7262125B2 (en) * 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US6635965B1 (en) * 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7955972B2 (en) * 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7141494B2 (en) * 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7589017B2 (en) * 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7005372B2 (en) * 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7754604B2 (en) * 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
JP4798688B2 (ja) * 2004-08-26 2011-10-19 エルピーダメモリ株式会社 半導体装置の製造方法
US7550381B2 (en) * 2005-07-18 2009-06-23 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface
KR100680969B1 (ko) * 2005-08-18 2007-02-09 주식회사 하이닉스반도체 텅스텐실리사이드 박막 형성방법
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US8049178B2 (en) * 2007-08-30 2011-11-01 Washington State University Research Foundation Semiconductive materials and associated uses thereof
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US8058170B2 (en) * 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8551885B2 (en) * 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8207062B2 (en) * 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
CN104272441A (zh) 2012-03-27 2015-01-07 诺发系统公司 钨特征填充
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
KR20200032756A (ko) 2017-08-14 2020-03-26 램 리써치 코포레이션 3차원 수직 nand 워드라인을 위한 금속 충진 프로세스
KR20200140391A (ko) 2018-05-03 2020-12-15 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
JP2022513479A (ja) 2018-12-14 2022-02-08 ラム リサーチ コーポレーション 3d nand構造上の原子層堆積
WO2020210260A1 (en) 2019-04-11 2020-10-15 Lam Research Corporation High step coverage tungsten deposition
US10916431B2 (en) 2019-04-16 2021-02-09 International Business Machines Corporation Robust gate cap for protecting a gate from downstream metallization etch operations

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231056A (en) * 1992-01-15 1993-07-27 Micron Technology, Inc. Tungsten silicide (WSix) deposition process for semiconductor manufacture
US5364803A (en) * 1993-06-24 1994-11-15 United Microelectronics Corporation Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332124B1 (ko) * 1995-03-07 2002-09-04 주식회사 하이닉스반도체 반도체소자의게이트전극형성방법

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US5726096A (en) 1998-03-10
KR970009867B1 (ko) 1997-06-18

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