KR960023223A - 실리콘 이동을 감소시키기 위한 질화 금속막의 처리방법 - Google Patents

실리콘 이동을 감소시키기 위한 질화 금속막의 처리방법 Download PDF

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KR960023223A
KR960023223A KR1019950072404A KR19950072404A KR960023223A KR 960023223 A KR960023223 A KR 960023223A KR 1019950072404 A KR1019950072404 A KR 1019950072404A KR 19950072404 A KR19950072404 A KR 19950072404A KR 960023223 A KR960023223 A KR 960023223A
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metal
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metal layer
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plasma
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로이 호워 글엔
다비드 코스텔니크 다니엘
쉬 이-쳉
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제임스 조셉 드롱
어플라이드 머티어리얼스, 인코포레이티드
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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Abstract

배리어를 통한 실리콘의 이동을 감소시키기 위한 직접회로상에 금속질화 배리어층의 표면을 처리하는 방법이다. (TiN과 같음)금속 질화 배리어는 질소플라즈마에 노출되어 금속 질화 배리어의 배리어 성능을 개선시킨다.

Description

실리콘 이동을 감소시키기 위한 질화 금속막의 처리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 실시예에 따른 예시적인 질소 플라즈마 처리를 도시하는 부분적으로 완성된 집적회로에 대한 단면도.

Claims (16)

  1. 기판과 제1금속층과 접촉하는 제1금속의 질화물층을 갖는 집적회로의 제조방법에 있어서, 질화된 제1금속층을 질소 플라즈마에 노출시키는 단계를 포함하는 것을 특징으로 하는 직접회로 제조방법.
  2. 제1항에 있어서, 질소플라즈마 단계가 0.1Torr 및 100Torr. 사이의 압력으로 질소를 포함하는 반응기에서 수행되고 10 내지 600초 동안 50 내지 500와트의 전력으로 질화된 제1금속층을 플라즈마에 노출시키는 단계를 또한 포함하는 것을 특징으로 하는 방법.
  3. 제2항에 있어서, 제1금속층과 제1금속의 질화층의 증착이 스퍼터링에 의하여 이루어지고 화학증착법에 의하여 제2금속층을 증착시키는 단계를 또한 포함하는 것을 특징으로 하는 방법.
  4. 제3항에 있어서, 플라즈마 단계와 제2금속층의 화학적 증착단계가 동일한 반응기내에서 발생하는 것을 특징으로 하는 방법.
  5. 제4항에 있어서, 제1금속이 티타늄이고 제2금속이 텅스텐인 것을 특징으로 하는 방법.
  6. 제1금속을 기판에 증착시키는 단계와, 제1금속의 질화층을 제1금속과 접촉상태를 전착시키는 단계와 제2금속층을 제1금속의 질화물과 접촉상태로 전착시키는 단계를 포함하는 기판을 갖는 집적회로를 제조하는 방법에 있어서, 질화물 제1금속층을 증착 후 그리고 제2금속의 증착전에 질소 플라즈마에 노출시키는 단계를 포함하는 것을 특징으로 하는 집적회로 제조방법.
  7. 제6항에 있어서, 질소플라즈마 단계가 0.1 내지 500Torr. 사이의 압력으로 질소를 포함하는 반응기에서 수행되고 10 내지 600초 동안 50 내지 500와트의 전력으로 질화된 제1금속층은 플라즈마에 노출시키는 단계를 포함하는 것을 특징으로 하는 방법.
  8. 제7항에 있어서, 제1금속층과 질화된 제1금속층의 증착이 스퍼터링으로 수행되고 제2금속층의 증착이 화학증착법에 의하여 수행되는 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 플라즈마 단계와 제2금속층의 화학적 증착이 동일한 반응로에서 수행되는 것을 특징으로 하는 방법.
  10. 제9항에 있어서, 제1금속이 티타늄이고 제2금속이 텅스텐인 것을 특징으로 하는 방법.
  11. 제6항에 있어서, 플라즈마 단계가 상기 기판이 300℃ 내지 600℃ 사이의 온도에 유지되는 동안 수행되는 것을 특징으로 하는 방법.
  12. 티타늄을 기판에 스퍼터링하는 단계와, 티타늄 질화층을 티타늄층과 접촉하는 상태로 스퍼터링하는 단계와, 텅스텐층을 티타늄 질화층과 접촉하는 상태로 증착하는 단계를 포함하는 기판을 갖는 집적회로 제조방법에 있어서, 증착후 텅스텐층의 증착전에 티타늄 질화층을 질소분위기에 노출시키는 단계를 포함하는 것을 특징으로 하는 방법.
  13. 내용 없음
  14. 제13항에 있어서, 질소플라즈마 단계가 0.1 내지 100Torr.의 압력으로 질소를 함유하는 반응기에서 수행되고 10 내지 600초 사이에서 50 내지 500와트의 전력으로 질화된 제1금속층을 플라즈마에 노출시키는 단계를 포함하는 것을 특징으로 하는 방법.
  15. 제14항에 있어서, 텅스텐층이 화학증착법에 의하여 증착되는 것을 특징으로 하는 방법.
  16. 제15항에 있어서, 플라즈마 단계와 텅스텐층의 화학증착이 동일한 반응기내에서 이루어지는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950072404A 1994-12-30 1995-12-30 실리콘 이동을 감소시키기 위한 질화 금속막의 처리방법 KR960023223A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/367,377 1994-12-30
US08/367,377 US5712193A (en) 1994-12-30 1994-12-30 Method of treating metal nitride films to reduce silicon migration therein

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KR960023223A true KR960023223A (ko) 1996-07-18

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EP (1) EP0720214A3 (ko)
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US5712193A (en) 1998-01-27
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EP0720214A3 (en) 1997-10-08

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