US20100267230A1 - Method for forming tungsten contacts and interconnects with small critical dimensions - Google Patents

Method for forming tungsten contacts and interconnects with small critical dimensions Download PDF

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US20100267230A1
US20100267230A1 US12755248 US75524810A US2010267230A1 US 20100267230 A1 US20100267230 A1 US 20100267230A1 US 12755248 US12755248 US 12755248 US 75524810 A US75524810 A US 75524810A US 2010267230 A1 US2010267230 A1 US 2010267230A1
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temperature
tungsten
cvd
layer
embodiments
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Anand Chandrashekar
Feng Chen
Raashina Humayun
Michal Danek
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Chen Feng
Novellus Systems Inc
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Novellus Systems Inc
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Abstract

Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application claims the benefit under U.S.C. 119(e) to U.S. provisional application 61/169,954 filed Apr. 16, 2009, titled “METHOD FOR FORMING TUNGSTEN CONTACTS AND INTERCONNECTS WITH SMALL CRITICAL DIMENSIONS,” the entirety of which is incorporated herein by this reference.
  • BACKGROUND
  • [0002]
    The deposition of tungsten films using chemical vapor deposition (CVD) techniques is an integral part of many semiconductor fabrication processes. Tungsten films may be used as low resistivity electrical connections in the form of horizontal interconnects, vias between adjacent metal layers, and contacts between a first metal layer and the devices on the silicon substrate. In a conventional tungsten deposition process, the wafer is heated to the process temperature in a vacuum chamber, and then a very thin portion of tungsten film, which serves as a seed or nucleation layer, is deposited. Thereafter, the remainder of the tungsten film (the bulk layer) is deposited on the nucleation layer. Conventionally, the tungsten bulk layer is formed by the reduction of tungsten hexafluoride (WF6) with hydrogen (H2) on the growing tungsten layer.
  • [0003]
    As semiconductor devices scale to the 32 nm technology node and beyond, shrinking contact and via dimensions make chemical vapor deposition of tungsten more challenging. Increasing aspect ratios can lead to voids or large seams within device features, resulting in lower yields and decreased performance in microprocessor and memory chips. The International Technology Roadmap for Semiconductors (ITRS) calls for 32 nm stacked capacitor DRAM contacts to have aspect ratios of greater than 20:1. Logic contacts, though not as aggressive as DRAM contacts, will still be challenged as aspect ratios grow to more than 10:1. Void-free fill in aggressive features like these is problematic using conventional CVD tungsten deposition techniques.
  • SUMMARY OF INVENTION
  • [0004]
    One aspect of the invention relates to methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Another aspect of the invention relates to methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0005]
    FIG. 1 is a schematic illustration of a feature filled with tungsten nucleation and bulk layers according to certain embodiments.
  • [0006]
    FIG. 2 is a plot showing volume percentage of a feature occupied by a nucleation layer as a function of technology node (feature size) for 12 Å and 50 Å nucleation layers.
  • [0007]
    FIG. 3 is a process flow diagram illustrating operations in a method of filling a feature with tungsten according to various embodiments.
  • [0008]
    FIG. 4 depicts schematic illustrations of feature cross-sections at various stages of a process according to certain embodiments.
  • [0009]
    FIG. 5 depicts a schematic illustration of a substrate cross-section after a feature filling process according to certain embodiments.
  • [0010]
    FIG. 6 is a plot depicting defects as a function of film thickness for a films deposited 1) by a pulsed layer nucleation (PNL) process and low temperature chemical vapor deposition (CVD) process and 2) by a PNL process only.
  • [0011]
    FIG. 7 depicts images of films after high and low temperature CVD fill of 32 nm features.
  • [0012]
    FIG. 8 depicts resistivity as a function of film thickness for films deposited by high and low temperature CVD.
  • [0013]
    FIG. 9 is a plot depicting resistivity as a function of film thickness for tungsten films deposited by various processes.
  • [0014]
    FIGS. 10-12 are process flow diagrams illustrating operations in methods of filling a feature with tungsten according to various embodiments.
  • [0015]
    FIG. 13 is a process flow diagram illustrating operations in a method of depositing a tungsten nucleation layer that may be employed with certain embodiments.
  • [0016]
    FIGS. 14A and 14B illustrates gas pulse sequences in a low resistivity treatment according to various embodiments.
  • [0017]
    FIG. 15 is a schematic illustration of a feature cross-section after a feature filling process according to certain embodiments.
  • [0018]
    FIG. 16A is a plot illustrating resistivity of 50 nm and 10 nm films as a function of reducing agent exposure during a low resistivity treatment process.
  • [0019]
    FIG. 16B is a plot illustrating resistivity of a 50 nm film as a function of reducing agent exposure for a low resistivity treatment for features filled via high temperature CVD only and features filled via low and high temperature CVD.
  • [0020]
    FIG. 17 is a plot illustrating resistivity as a function of film thickness for various fill processes.
  • [0021]
    FIG. 18 is a process flow diagram illustrating operations in a method of filling a feature with tungsten according to various embodiments.
  • [0022]
    FIG. 19 is a plot illustrating resistivity as a function of film thickness for various fill processes.
  • [0023]
    FIG. 20 is a schematic illustration of a processing system suitable for conducting tungsten deposition process in accordance with embodiments of the invention.
  • [0024]
    FIG. 21 is a basis illustration of a tungsten deposition in accordance with embodiments of the invention.
  • DETAILED DESCRIPTION Introduction
  • [0025]
    In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, which pertains to forming thin tungsten films. Modifications, adaptations or variations of specific methods and structures shown and discussed herein will be apparent to those skilled in the art and are within the scope of this invention.
  • [0026]
    Extending tungsten to sub-32 nm technologies is critical to maintaining via/contact performance and reliability in both memory and logic devices. There are various challenges in tungsten fill as devices scale to smaller technology nodes. One challenge is preventing an increase in resistance due to the thinner films in contacts and vias. As features become smaller, the tungsten (W) contact or line resistance increases due to scattering effects in the thinner W film. While efficient tungsten deposition processes require tungsten nucleation layers, these layers typically have higher electrical resistivities than the bulk tungsten layers. As features become smaller, low resistivity tungsten films minimize power losses and overheating in integrated circuit designs. The thin barrier and tungsten nucleation films, which are higher in resistivity, occupy a larger percentage of the smaller features.
  • [0027]
    FIG. 1 shows a volume occupied by a nucleation film 110 and a bulk tungsten material 120 in a via/contact structure 100. FIG. 2 shows the percent the percent volume occupied by 12 Å and 50 Å nucleation films as a function of technology node. Because the resistivity of the nucleation layer is higher than that of the bulk layer (ρnucleationbulk) the thickness of the nucleation layer should be minimized to keep the total resistance as low as possible. On the other hand, the tungsten nucleation should be sufficiently thick to fully cover the underlying substrate to support high quality bulk deposition.
  • [0028]
    Another challenge in tungsten plugfill as devices scale to smaller technology nodes is step coverage. Stacked capacitor DRAM contacts, for example, require high aspect ratio tungsten fill of features greater than 20:1 at 32 nm nodes. Logic contacts, though not as aggressive as DRAM contacts, still have challenges as the smaller contact openings increase the aspect ratio requirements to near 10:1. Memory devices typically use CVD TiCl4 based Ti/TiN liner/barriers, which are fairly conformal. Logic devices, however, still rely on PVD/MOCVD based Ti/TiN films that create additional step coverage challenges associated with large overhang that creates a reentrant shape or pinch off. PVD overhang from the liner/barrier film magnifies the difficulty in filling small features. This makes it difficult to fill features not only with the nucleation film, but ultimately the bulk CVD film. Incoming overhang combined with the dimensions of high aspect ratio structures makes it difficult or impossible to achieve void-free plugfill using CVD tungsten deposition processes used in previous technology nodes.
  • [0029]
    According to various embodiments, the present invention provides tungsten fill processes to overcome aggressive aspect rations and liner/barrier step coverage limitations, including reducing nucleation film thickness and improving step coverage of the fill process. In certain embodiments, the methods also provide superior barrier films against fluorine attack of the underlying barrier/liner layer.
  • [0030]
    FIG. 3 presents a process flow sheet illustrating operations in a method of providing fill according to certain embodiments. The process begins by providing substrate having a high aspect ratio feature formed therein. (302). While embodiments of the invention are not limited to high aspect ratio features, the methods described herein are critical to achieving good void-free fill in high aspect ratio features, for which CVD processes used to fill features in earlier technology nodes do not provide adequate fill. According to various embodiments, the substrate feature has an aspect ratio of at least 10:1, at least 15:1, at least 20:1, at least 25:1 or at least 30:1. Also according to various embodiments, the feature size is characterized by the feature opening size in addition to or instead of the aspect ratio. The opening may be from 10 nm-100 nm, or 10 nm-50 nm wide. For example, in certain embodiments, the methods may be advantageously used with features having narrow openings, regardless of the aspect ratio.
  • [0031]
    In certain embodiments, the recessed feature is formed within a dielectric layer on a substrate, with the bottom of the feature providing contact to an underlying metal layer. Also in certain embodiments, the feature includes a liner/barrier layer on its sidewalls and/or bottom. Examples of liner layers include Ti/TiN, TiN and WN. In addition to or instead of diffusion barrier layers, the feature may include layers such as an adhesion layer, a nucleation layer, a combination of thereof, or any other applicable material lining the sidewalls and bottom of the feature.
  • [0032]
    In certain embodiments, the feature is a re-entrant feature; that is the liner layer or other material forms an overhang that partially blocks the feature opening. Because many deposition processes do not have good step coverage properties, i.e., more material is deposited on the field region and near the opening than inside the feature, the liner layer thicker near the opening than, for example, inside the feature. For the purposes of this description, “near the opening” is defined as an approximate position or an area within the feature (i.e., along the side wall of the feature) corresponding to between about 0-10% of the feature depth measured from the field region. In certain embodiments, the area near the opening corresponds to the area at the opening. Further, “inside the feature” is defined as an approximate position or an area within the feature corresponding to between about 20-60% of the feature depth measured from the field region on the top of the feature. Typically, when values for certain parameters (e.g., thicknesses) are specified “near the opening” or “inside the feature”, these values represent a measurement or an average of multiple measurements taken within these positions/areas. In certain embodiments, an average thickness of the under-layer near the opening is at least about 10% greater than that inside the feature. In more specific embodiments, this difference may be at least about 25%, at least about 50%, or at least about 100%. Distribution of a material within a feature may also be characterized by its step coverage. For the purposes of this description, “step coverage” is defined as a ratio of two thicknesses, i.e., the thickness of the material inside the feature divided by the thickness of the material near the opening. In certain examples, the step coverage of the liner or other under-layer is less than about 100% or, more specifically, less than about 75% or even less than about 50%.
  • [0033]
    Returning to FIG. 3, a tungsten nucleation layer is then deposited in the feature, typically to conformally coat the sidewalls and bottom of the feature (304). In general, a nucleation layer is a thin conformal layer which serves to facilitate the subsequent formation of a bulk material thereon. Conformation to the underlying feature is critical to support high quality deposition. Various processes may be used to form the nucleation layer, including but not limited to, CVD processes, atomic layer deposition (ALD) processes and pulsed nucleation layer (PNL) deposition processes.
  • [0034]
    In a PNL technique, pulses of reactants are sequentially injected and purged from the reaction chamber, typically by a pulse of a purge gas between reactants. A first reactant is typically adsorbed onto the substrate, available to react with the next reactant. The process is repeated in a cyclical fashion until the desired thickness is achieved. PNL is similar to atomic layer deposition techniques reported in the literature. PNL is generally distinguished from ALD by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer film growth per cycle). In the context of the description provided herein, PNL broadly embodies any cyclical process of sequentially adding reactants for reaction on a semiconductor substrate. Thus, the concept embodies techniques conventionally referred to as ALD. In the context of description provided herein, CVD embodies processes in which reactants are together introduced to a reactor for a vapor-phase reaction. PNL and ALD processes are distinct from CVD processes and vice-versa.
  • [0035]
    Forming a nucleation layer using one or more PNL cycles is discussed in U.S. Pat. Nos. 6,844,258; 7,005,372; 7,141,494; 7,262,125; and 7,589,017; US Patent Publication Nos. 2008/0254623 and 2009/0149022, and U.S. patent application Ser. No. 12/407,541, all of which references are incorporated herein by reference in their entireties. These PNL nucleation layer processes involve exposing a substrate to various sequences of reducing agents and tungsten precursors to grow a nucleation layer of the desired thickness. A combined PNL-CVD method of depositing a nucleation layer is described in U.S. Pat. No. 7,655,567, also incorporated in its entirety.
  • [0036]
    Nucleation layer thickness is enough to support high quality deposition. In certain embodiments, the requisite thickness depends in part on the nucleation layer deposition method. As described further below, in certain embodiments a PNL method providing near 100% step coverage nucleation film at thicknesses as low as about 12 Å (as compared to typical nucleation films of 50 Å) may be used in certain embodiments. Regardless of the method used to deposit the nucleation layer, however, the reduced temperature CVD operation used to fill the feature can be used with thinner nucleation layers than required by conventional higher temperature CVD. Without being bound by any particular theory, it is believed that this may be because the slower chemistry at the reduced temperatures improves growth even on nucleation sites that are not fully developed. According to various embodiments, nucleation layers of between about 30-50 Å (3-5 nm) may be formed, in certain embodiments, as low as 10-15 Å.
  • [0037]
    In certain embodiments, depositing the nucleation layer is followed by a post-deposition treatment operation to improve resistivity. Such treatment operations are described further below and in more detail in U.S. Patent Publication No. 2009/0149022, and U.S. patent application Ser. No. 12/407,541, both of which are incorporated by reference herein.
  • [0038]
    Once the nucleation layer is formed, the process continues by filling the feature with a low-temperature CVD tungsten film (306). In this operation, a reducing agent and a tungsten-containing precursor are flowed into a deposition chamber to deposit a bulk fill layer in the feature. An inert carrier gas may be used to deliver one or more of the reactant streams, which may or may not be pre-mixed. Unlike PNL or ALD processes, this operation generally involves flowing the reactants continuously until the desired amount is deposited. In certain embodiments, the CVD operation may take place in multiple stages, with multiple periods of continuous and simultaneous flow of reactants separated by periods of one or more reactant flows diverted.
  • [0039]
    Various tungsten-containing gases including, but not limited to, WF6, WCl6, and W(CO)6 can be used as the tungsten-containing precursor. In certain embodiments, the tungsten-containing precursor is a halogen-containing compound, such as WF6. In certain embodiments, the reducing agent is hydrogen gas, though other reducing agents may be used including silane (SiH4), disilane (Si2H6) hydrazine (N2H4), diborane (B2H6) and germane (GeH4). In many embodiments, hydrogen gas is used as the reducing agent in the CVD process.
  • [0040]
    CVD filling of the feature is performed at a reduced temperature. According to various embodiments, the reduced temperature (process and/or substrate temperature) is in one of the following ranges: between about 250-350° C., between about 250° C.-340° C., between about 250° C.-330° C., between about 250° C.-325° C., between about 250° C.-320° C., between about 250° C.-315° C., between about 250° C.-310° C., between about 250° C.-305° C., or between about 250° C.-300° C. Also according to various embodiments, the process and/or substrate temperature is: between about 260-310° C., between about 270° C.-310° C., between about 280° C.-310° C., or between about 290° C.-310° C. In certain embodiments, the process and/or substrate temperature is about 300° C.
  • [0041]
    After filling the feature, the temperature is raised to deposit a high temperature CVD layer (308). The high temperature may be in one of the following ranges: between about 350-450° C., between about 360° C.-450° C., between about 370° C.-450° C., between about 380° C.-450° C., between about 390° C.-450° C., or between about 400° C.-450° C. In certain embodiments, the high temperature CVD is performed at about 395° C. Raising the temperature may involve raising the substrate temperature. According to various embodiments, the temperature is raised at least about 50° C., at least about 60° C., at least about 70° C., at least about 80° C., at least about 90° C., at least about 100° C., or at least about 110° C. The high temperature CVD layer is then deposited (310). In certain embodiments, operations 308 and 310 are not performed; that is, after the low temperature CVD process is complete and the feature is filled, the substrate moves on for further processing such as planarization.
  • [0042]
    In certain embodiments, transitioning from operation 306 to operation 308 involves moving the substrate from one deposition station to another in a multi-station chamber. Still further, each of operation 304, the post-deposition resistivity treatment (if performed), operation 306 and operation 308 is performed in a different station of the same multi-station chamber.
  • [0043]
    In alternative embodiments in which a single station is used to perform operations 306 and 308, transitioning from operation 306 to operation 308 involved shutting off a flow of tungsten precursor (optionally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature. Once the substrate temperature is stabilized, the tungsten precursor and other gases, if necessary, are flowed into the reaction chamber for the high temperature deposition. In other embodiments, transitioning from operation 306 may involve raising the substrate temperature while allowing the deposition to continue during the transition period.
  • [0044]
    In embodiments in which the high temperature tungsten CVD film is deposited, it may be deposited as an overburden layer on the filled feature. FIG. 4 illustrates schematic representations of one example of a feature's cross-sections at different stages of a filling process in which a high temperature CVD layer is deposited after the feature 410 is filled using reduced temperature CVD. Cross-section 401 represents an example of the feature 410 prior to any tungsten deposition. In this example, the feature 410 is formed in a dielectric layer 430, has an opening 425 at the top surface 405 of the substrate and includes a liner layer 413, such as TiN layer. In certain embodiments, the size of the cavity near the opening 425 is narrower that inside the feature, for example, due to overhang 415 of the under-layer 413 as depicted in FIG. 4.
  • [0045]
    Cross-section 411 represents the feature after reduced temperature CVD is performed to fill the feature with low temperature CVD bulk layer 453. (The tungsten nucleation layer is not depicted in FIG. 4.) In certain embodiments, the reduced temperature CVD is performed at least until the feature corner 417 (the point at which the substrate transitions from a planar region to the recessed feature) is covered with low temperature CVD tungsten. This is because in certain embodiments the liner, dielectric or other under-layer is particularly vulnerable to F2 attack at the feature corner. As discussed further below, the reduced temperature CVD tungsten has unexpectedly good barrier properties, and protects the under-layer from F2 exposure during the subsequent high temperature CVD deposition.
  • [0046]
    Cross-section 421 represents the feature after the higher temperature CVD is performed to deposit an overburden layer 455. The feature sidewalls and corners are protected from F2 attack by the low-temperature CVD film 453. Cross-section 431 provides a comparative example of a narrow feature such as that depicted in cross-section 401 filled using a conventional (high temperature) process. With a high temperature process, because of the overhang 415 and the relatively poor step coverage of the high temperature layer 455, the closed feature has an unfilled void 429 (i.e., a seam). The seam is problematic for a variety reasons—increasing resistance in the feature and causing problems during chemical-mechanical planarization (CMP). Although not visible in the schematic, the corners or other parts of the liner have adhesion problems due to F2 attack, exhibiting peeling or and defects. Such defects are discussed further below with reference to FIG. 6.
  • [0047]
    In certain embodiments, a substrate having both high aspect ratio features and low aspect ratio features to be filled with tungsten is provided. For example, a substrate may have one or more features having an aspect ratio of at least about 10:1 and one or more features having aspect ratio of less than about 5:1, or 1:1 or 1:2. A reduced temperature CVD operation may then be performed to fill the one or more high aspect ratio features, followed by a high temperature CVD operation to fill the low aspect ratio features. FIG. 5 depicts an example of a high aspect ratio feature 510 and a low aspect ratio feature 520 filled in this manner. Feature 510 is filled with low temperature CVD film 553, critical to providing good void-free fill in narrow opening, high aspect ratio features. Due to its wide opening (e.g., on the order of hundreds of nanometers to a few microns), an insignificant amount of low-temperature CVD film is deposited into feature 520. A high temperature CVD operation is then used to fill feature 520 with high temperature CVD film 555, and in this case, deposit overburden.
  • [0048]
    Reduced temperature CVD is critical to obtaining high quality tungsten fill in narrow, high aspect ratio features. Current tungsten CVD is performed at temperatures around 400° C. Obtaining excellent plugfill on advanced node features is a challenge that is magnified when the features have pinched openings (as illustrated at cross-section 401 of FIG. 4). Another challenge is presented by thinning TiN barriers to allow more space in the features for tungsten deposition. In certain embodiments, the advanced node features have barrier layers as less than 5 nm thick, as thin as 1 nm. Fluorine migration from the WF6 in conventional CVD processes into the Ti liner region results in integration problems include fluorine attack of the liner and yield loss.
  • [0049]
    The reduced temperature CVD described above is critical to obtaining high quality plugfill. Without being bound by a particular theory, it is believed that the high quality plugfill provided by the reduced temperature CVD is due to a number of factors. First, lower CVD temperature decreases the tungsten deposition rate by reducing thermal decomposition of the tungsten-containing precursor. This is believed to aid in plugfill in high aspect ratio, narrow features by reducing tungsten deposition at the feature opening thereby allowing more WF6 (or other tungsten-containing precursor) molecules to reach the lower regions of the feature and deposit tungsten. In conventional CVD processes, deposition at the top of the feature prevents precursor diffusion into the lower region of the feature. The result is voids or seams in the internal region of the feature, such as depicted in cross-section 431 in FIG. 4. Better plugfill has multiple benefits: it results in more tungsten in the feature, promoting electron transport and reducing contact and line resistance, and it prevents post-CMP problems. For example, it reduces the likelihood that CMP slurry is trapped in seams and voids.
  • [0050]
    In addition to the above mechanisms, it is believed that excellent plugfill is due to insufficient energy at the reduced temperatures to promote fluorine migration through the tungsten nucleation and TiN layers and/or insufficient energy to form TiFx from a reaction between Ti and F or T1 and WF6, even if the fluorine atoms or tungsten hexafluoride molecules do migrate. A low temperature CVD reaction minimizes Ti attack by fluorine.
  • [0051]
    In addition to the above, it was found that low temperature CVD tungsten film provides unexpectedly good fluorine barrier properties compared to tungsten films deposited by other processes. FIG. 6 shows results of a defect study conducted on conventional PNL W and PNL W+low temperature CVD. PNL W only or PNL W+low temperature W films were deposited on a Ti/TiN substrate at the following thicknesses:
  • [0000]
    PNL W only: 34 Å, 54 Å and 76 Å
    PNL W+low temp CVD W: 22 Å PNL+8 Å CVD (30 Å total), 22 Å PNL+10 Å CVD (32 Å total), 22 Å PNL+15 Å CVD (37 Å total)
  • [0052]
    Both PNLW and low temp CVD occurred at 300° C. Then the W films were subjected to a torture test where they were exposed to WF6 at 395° C. If fluorine diffuses through the W film and the TiN it reacts with the underlying Ti to form volatile TiFX compounds and results in typical “volcano” defects as well as local peeling, cracking or bubbling. These defects are visible under an optical microscope. As shown in FIG. 6, low temperature CVD W along with thin PNL W behaved as a better W diffusion layer than PNL W only. This is an unexpected result in that for the same overall thickness of W film the low temperature CVD film provides improved F barrier properties. It would have been expected that the thin PNL+low temperature CVD layer would have similar defect counts as the thin PNL layer deposited at the same temperature.
  • [0053]
    A fluorine attack study was performed on wafers patterned with 100 nm opening/10:1 aspect ratio features including PVD Ti/MOCVD TiN barrier layers. A tungsten nucleation layer was deposited in the features, with a thin (12 Å) layer used so as to generate an exaggerated signal. Features were filled with either 395° C. CVD tungsten or 350° C. CVD tungsten. Feature fill was then examined and compared. The low temperature CVD fill provided better plugfill as well as reduced fluorine attack. In addition to showing reduced fluorine attack, the results indicate that reduced temperature provides better step coverage on thin nucleation layers. Without being bound by any particular theory, it is believed that the slower chemistry of the reduced temperature process allows growth on nucleation sites that are not fully formed.
  • [0054]
    Fill of 32 nm re-entrant features was performed using 300° C. and 395° C. The filled features were compared, and the films were examined for volcano defects. Low temperature CVD resulted in better fill, with fewer or no seams or voids. Voids were observed in the high temperature CVD filled features. FIG. 7 shows microscopic images of the 395° C. film (701) and the 300° C. film (702). Many volcano defects are observed in the 395° C. film; none in the 300° C. film. In addition to providing improved plugfill and reduced fluorine attack, the low temperature films have resistivities comparable to the high temperature films. This is shown in FIG. 8.
  • [0055]
    Also provided are improved methods of depositing ultra-low resistivity tungsten films. According to various embodiments, these methods involve depositing a thin PNL nucleation layer, performing a low resistivity treatment on the nucleation layer, and depositing a high temperature CVD layer to fill the feature. In certain embodiments, the low resistivity treatment includes a low temperature CVD process.
  • [0056]
    It has been found that low resistivity processes that grow low resistivity tungsten for thicknesses larger than 20 nm and above may not grow low resistivity tungsten at thicknesses of 20 nm or less. When the critical dimension of the devices reduces to 40 nm or lower, the thickness of the tungsten layers in the structures is 20 nm or less. FIG. 9 presents a plot illustrating film resistivity as a function of thickness for films treated using a first low resistivity process (905) and for films treated using a thin film low resistivity process according to certain embodiments (901). For comparison, a film deposited without low resistivity treatment (907) is depicted.
  • [0057]
    The process used to deposit films represented by 905 involves depositing a PNL nucleation layer in a hydrogen-free ambient at reduced temperature followed by a high temperature low resistivity treatment. The untreated films (data series 907 were deposited by a PNL nucleation layer, with no low resistivity treatment. Nucleation layers of about 20-25 Å were deposited, with the remaining thickness deposited by low-temperature CVD. While the high temperature treatment results in film having lower resistivity for thicknesses greater than 120 Å (12 nm), the opposite is true for thicknesses less than 120 Å. Process parameters for deposition of the films are shown below:
  • [0000]
    Nucleation Nucleation Low resistivity Low resistivity
    layer pulse layer treatment treatment CVD CVD
    Data series sequence temperature pulse sequence temperature chemistry temperature
    907 (no B/W/S/W + 300° C. n/a n/a WF6 and H2 300° C.
    Treatment) 3 × (S/W)
    (H2 ambient)
    905 (high 5 × (B/W) 300° C. 6 × (B) 395°C. WF6 and H2 300° C.
    temperature (H2-free
    treatment) ambient)
    901 (thin 5 × (B/W) 300° C. 6 × (B) 300°C. WF6 and H2 300° C.
    film (H2-free (partial
    resistivity ambient) thickness)
    treatment) 395° C.
    (remaining
    thickness)
  • [0058]
    B=B2H6/W=WF6/S=SiH4
  • [0059]
    The increase in resistivity for thin films treated via with high temperature process was unexpected. As can be seen from the figure, the low-resistivity treatment according to an embodiment of the inventive processes provides low resistivities even for films less than 120 Å. According to various embodiments, the thin film resistivity treatment involves performing a low temperature resistivity treatment involving exposing a deposited nucleation layer to multiple pulses of reducing agent at a reduced temperature. The multiple pulses of reducing agent may or may not include intervening pulses of a tungsten-containing precursor. Also according to various embodiments, the thin film resistivity treatment involves a partial fill via reduced temperature CVD prior to completing fill via high temperature CVD. While depositing some amount of the bulk CVD material, the reduced temperature CVD operation may be considered as a low-resistivity treatment. In certain embodiments, the processes involve both a low temperature exposure to multiple pulses of reducing agent and a partial fill via reduced temperature CVD, as in the films represented by data series 901 in FIG. 9.
  • [0060]
    While these processes described herein are appropriate for filling features having sub-40 nm critical dimensions, in particular for films having critical dimensions of 32 nm or smaller, they may also be employed for thicker films. As discussed further below, the improved resistivity is also observed for thicker films.
  • [0061]
    FIGS. 10-12 present process flow sheets illustrating operations in methods of filling features with low resistivity tungsten according to various embodiments. First, in FIG. 10, a substrate having a high aspect ratio recessed feature is provided to a deposition chamber (1002). As noted above, the feature may have a narrow opening, e.g., 40 nm in width or less. Also in certain embodiments, the method may be used to fill features having lower aspect ratios and/or wider openings. A tungsten nucleation layer is then deposited in the feature (1004).
  • [0062]
    While the nucleation layer may be deposited by any known method, in certain embodiments, improved resistivity is obtained by depositing the nucleation layer at low temperature, then performing a multi-pulse low resistivity treatment. Such methods of depositing the nucleation layer are described in U.S. Pat. No. 7,589,017, incorporated by reference herein and in U.S. Patent Publication 2008/0254623, also incorporated by reference herein.
  • [0063]
    In certain examples, the nucleation layer is deposited as described in FIG. 13. After a substrate without a nucleation layer (as at 401 in FIG. 4) is provided, the as-provided substrate is exposed to a boron-containing reducing agent to form a boron-containing layer on the substrate surface (1302). The boron-containing layer is often a layer of elemental boron, though in some embodiments, it may contain other chemical species or impurities from the boron-containing species itself or from residual gases in the reaction chamber. Any suitable boron-containing species may be used, including borane (BH3), diborane (B2H6), triborane, etc. Examples of other boron-containing species include boron halides (e.g., BF3, BCl3) with hydrogen.
  • [0064]
    Substrate temperature is low—below about 350° C., for example between about 250° C. and 350° C. or 250° C. and 325° C. In certain embodiments, the temperature is around 300° C. In certain embodiments, diborane is provided from a diluted source (e.g., 5% diborane and 95% nitrogen). Diborane may be delivered the reaction chamber using other or additional carrier gases such as nitrogen and/or argon. Importantly, no hydrogen is used.
  • [0065]
    Once the boron-containing layer is deposited to a sufficient thickness, the flow of boron-containing species to the reaction chamber is stopped and the reaction chamber is purged with a carrier gas such as argon, hydrogen, nitrogen or helium. In certain embodiments, only argon is used at the carrier gas. The gas purge clears the regions near the substrate surface of residual gas reactants that could react with fresh gas reactants for the next reaction step.
  • [0066]
    Continuing to the next operation in FIG. 13, the substrate is contacted with a tungsten-containing precursor to form a portion of the tungsten nucleation layer (1304). Any suitable tungsten-containing precursor may be used. In certain embodiments the tungsten-containing precursor is one of WF6, WCl6 and W(CO)6. The tungsten-containing precursor is typically provided in a dilution gas, such as argon, nitrogen, or a combination thereof. As with the boron-containing precursor pulse, the tungsten-containing precursor is delivered in a non-hydrogen environment. The substrate temperature is low—below about 350° C., for example between about 250° C. and 350° C. or 250° C. and 325° C. In certain embodiments, the temperature is around 300° C. In many cases, the substrate temperature is the same as during the exposure to the boron-containing species. Tungsten-containing precursor dosage and substrate exposure time will vary depending upon a number of factors. In general, the substrate is exposed until the adsorbed boron species is sufficiently consumed by reaction with the tungsten-containing precursor to produce a portion of the tungsten nucleation layer. Thereafter, the flow of tungsten-containing precursor to the reaction chamber is stopped and the reaction chamber is purged. The resulting portion of tungsten nucleation layer deposited in one boron-containing reducing agent/tungsten-containing precursor PNL cycle may be about 5 Å.
  • [0067]
    The low temperature boron-containing reducing agent pulse and tungsten precursor pulse operations are repeated to build up the tungsten nucleation layer to the desired thickness (1306). Between about 2-7 PNL cycles are required to deposit the very thin nucleation layer in certain embodiments, although in certain embodiments a single cycle may be sufficient. Depending on the substrate, the first one or two cycles may not result in thickness gain due to nucleation delay. As described previously, the tungsten nucleation layer should be sufficiently thin so as to not unduly increase the overall tungsten film, but sufficiently thick so as to support a high quality bulk tungsten deposition. The process described above is able to deposit a tungsten nucleation layer that can support high quality bulk deposition as low as about 10 Å in the high aspect ratio and/or narrow width feature. The thickness of the deposited nucleation layer is typically between about 10 Å and 50 Å, or for example, between 10 Å and 30 Å.
  • [0068]
    Temperature is one of the process conditions that affects the amount of tungsten deposited. Others include pressure, flow rate and exposure time. Maintaining temperatures at or below about 350° C. results in less material deposited during a cycle. This in turn provides lower resistivity. In some embodiments, temperatures may be about 300° C. or 200° C.
  • [0069]
    Referring back to FIG. 10, after the tungsten nucleation layer is deposited, the deposited nucleation layer is treated via low temperature multi-pulse treatment to lower resistivity (1006). FIGS. 14 a and 14 b are graphs showing examples of pulse sequences that may be used according to various embodiments of the low resistivity treatment. FIG. 14 a shows an example of a pulse sequence such as described in U.S. Patent Publication No. 2009/0149022, incorporated by reference herein. The treatment process described therein involves exposing the deposited nucleation layer to multiple pulses of a reducing agent (without intervening pulses of another reactive compound). In FIG. 14 a, diborane is depicted as the reducing agent, though other reducing agents may be used. The treatment lowers resistivity, while providing good adhesion and resistance non-uniformity. Notably, using multiple reducing agent pulses is shown to provide significantly improved resistivity and uniformity than using a single pulse—even with the same overall exposure time. However, too many pulses may lead to poor adhesion of the eventual tungsten film to the underlying layer. An optimal number of pulses, e.g., between 2-8 is used to obtain low resistivity, low non-uniformity and acceptable adhesion. Unlike the nucleation layer deposition described in FIG. 13, the treatment operation may be performed with hydrogen in the background. Thus, transitioning from the nucleation to the treatment operation may involve turning on a flow of hydrogen in certain embodiments. Also in certain embodiments, a nucleation layer is deposited in a first station of a multi-station deposition chamber, with the low resistivity treatment performed in a second station. Transitioning from the nucleation deposition to the low resistivity treatment involves transferring the substrate to the second station.
  • [0070]
    FIG. 14 b shows another example of a pulse sequence in which the nucleation layer is exposed to multiple cycles of alternating reducing agent and a tungsten-containing precursor pulses. Diborane, B2H6, and tungsten hexafluoride, WF6, are shown as the reducing agent and tungsten-containing precursor, respectively, though certain embodiments may use other compounds. Alternating pulses of a reducing agent and tungsten-containing precursor are also used to deposit the tungsten nucleation layer, but in the treatment operation, typically substantially no tungsten is deposited. The flow rate and/or pulse time of the tungsten-containing precursor is limited to only scavenge the excess boron on the surface and in the chamber from the low-resistivity treatment, reducing the boron impurity. This in turn results in less micro-peeling and better film adhesion in certain embodiments. Accordingly, tungsten-containing precursor pulse exposure time and/or flow rate (relative to the reducing agent pulse) during the treatment may be less than that used to deposit the nucleation layer.
  • [0071]
    Some combination of the pulse sequences shown in FIGS. 14 a and 14 b may also be performed in certain embodiments. In the embodiments described herein, the multi-pulse treatment operation is performed at a reduced temperature (1006), below about 350° C., for example between about 250° C. and 350° C. or 250° C. and 325° C. In certain embodiments, the temperature is around 300° C. As shown above in FIG. 9 and discussed further below, for thin films, performing the low-resistivity treatment at low temperatures unexpectedly provides better resistivity than performing the treatment at higher temperatures. Without being bound by any particular theory, it is believed that this may be due to the amount of boron seen by the substrate. This is discussed further below with reference to FIG. 16A. According to various embodiments, the total amount of diborane (or other boron-containing reducing agent) exposure may be between about 1E-5 to 1E-2 moles, or more particularly, from about 1E-4 to 1E-3 moles during the multi-pulse treatment. A CVD bulk layer is then deposited to fill the feature (1008). This may involve reduced temperature fill, high temperature fill, or in some embodiments, a combination of both.
  • [0072]
    FIG. 11 shows a process flow sheet in a method of filling features with low resistivity tungsten according to certain embodiments in which reduced temperature CVD is used to partially fill the feature after the nucleation layer is deposited. High temperature CVD is then performed to complete the feature fill. A substrate having a high aspect ratio and/or narrow opening is provided as described with respect to FIG. 10 (1102). A nucleation layer is then deposited in the feature (1104). As described above, in certain embodiments, the nucleation layer is deposited as described in FIG. 13, with alternating diborane and tungsten precursor pulses in a low-temperature hydrogen-free environment. A multi-pulse low resistivity treatment is then optionally performed (1106). This treatment may involve multiple reducing agent pulses, without pulsing an intervening tungsten-precursor (as shown in FIG. 14 a) or may involve multiple reducing agent/tungsten precursor pulses (as shown in FIG. 14 b) or some combination of these. According to various embodiments, the multi-pulse treatment involves heating the substrate to a temperature between about 350° C. to 450° C., e.g., about 395° C., and allowing the temperature to stabilize, and exposing the nucleation layer, while maintaining the substrate temperature, to the multiple pulses. In other embodiments, the multi-pulse treatment is performed at a lower temperature, as described above with respect to FIG. 10.
  • [0073]
    Next, the feature is partially filled with a reduced temperature CVD bulk layer (1108). Various tungsten-containing gases including, but not limited to, WF6, WCl6, and W(CO)6 can be used as the tungsten-containing precursor. In certain embodiments, the tungsten-containing precursor is a halogen-containing compound, such as WF6. In certain embodiments, the reducing agent is hydrogen gas, though other reducing agents may be used including silane, disilane, hydrazine, diborane, and germane. In many embodiments, hydrogen gas is used as the reducing agent in the CVD process.
  • [0074]
    According to various embodiments, the reduced temperature (process and/or substrate temperature) is in one of the following ranges: between about 250-350° C., between about 250° C.-340° C., between about 250° C.-330° C., between about 250° C.-325° C., between about 250° C.-320° C., between about 250° C.-315° C., between about 250° C.-310° C., between about 250° C.-305° C., or between about 250° C.-300° C. Also according to various embodiments, the process temperature is: between about 260-310° C., between about 270° C.-310° C., between about 280° C.-310° C., or between about 290° C.-310° C. In certain embodiments, the process and/or substrate temperature is about 300° C.
  • [0075]
    Fill is completed via a high temperature CVD deposition (1110). The high temperature may be in one of the following ranges: between about 350-450° C., between about 360° C.-450° C., between about 370° C.-450° C., between about 380° C.-450° C., between about 390° C.-450° C., or between about 400° C.-450° C. In certain embodiments, the high temperature CVD is performed at about 395° C. Raising the temperature may involve raising the substrate temperature. According to various embodiments, the temperature is raised at least about 25° C., 30° C., 50° C., at least about 60° C., at least about 70° C., at least about 80° C., at least about 90° C., at least about 100° C., at least about 110° C., or at least about 125° C. In one process example, a low temperature CVD operation is performed at about 250° C. and a high temperature at 350° C. In certain embodiments, the temperature is raised no more than about 150° C. or even 125° C. to prevent thermal shock and consequent wafer breakage.
  • [0076]
    In certain embodiments, transitioning from operation 1108 to operation 1110 involves moving the substrate from one deposition station to another in a multi-station chamber. In alternative embodiments in which a single station is used to perform operations, transitioning from operation 1108 to operation 1110 may involve shutting off a flow of tungsten precursor (optionally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature. Once the substrate temperature is stabilized, the tungsten precursor and other gases, if necessary, are flowed into the reaction chamber for the high temperature deposition. In other embodiments, transitioning from operation 1210 may involve raising the substrate temperature while allowing the deposition to continue during the transition period.
  • [0077]
    According to various embodiments, reduced temperature CVD may be used to deposit about 0-70% of the total thickness of the bulk CVD fill. FIG. 15 illustrates a schematic representation of one example of a feature's cross-section after partial reduced temperature CVD fill and completed fill via high temperature CVD. Cross-section 1501 shows conformal partial fill reduced temperature CVD layer 1553 and high temperature fill 1555. T, the total thickness of the deposited CVD layer, is indicated (T is the width of the feature fill minus the tungsten nucleation layer thickness). 2T1 is the total thickness deposited via reduced temperature CVD. In certain embodiments, reduced temperature CVD may be used to deposit about 30-80% or 30-60% of the total thickness of the bulk CVD fill. The reduced temperature layer may also be characterized in terms of thickness deposited, with T1 being between about 1-10 nm or about 2-8 nm.
  • [0078]
    As discussed further below, partially filling the gap with reduced temperature CVD prior to completing gap fill with high temperature CVD improves resistivity. While the reduced temperature CVD operation generally deposits some amount of conformal tungsten in the feature, it may also be thought of as a low resistivity treatment operation. In certain embodiments, the exposure time and/or dose of the reduced temperature operation may be short or small enough such that substantially no tungsten is deposited.
  • [0079]
    FIG. 12 presents a process flow diagram in which both a low temperature multi-pulse treatment is performed as well as a partial fill via reduced temperature CVD prior to completing fill via high temperature CVD. As with in reference to FIGS. 10 and 11, a substrate having a high aspect ratio feature is provided (1202), and a nucleation layer is deposited in the feature (1204). Depositing a nucleation layer according to certain embodiments is described in FIG. 13. A low-temperature multiple pulse treatment is then performed (1206) as described above with respect to FIG. 10. At this juncture, in certain embodiments, both the nucleation layer formation and subsequent multi-pulse treatment operation involve the use of a boron-containing compound exclusively as a reducing agent; that is, silanes or other non-boron-containing reducing agents are not used in any operation preceding CVD deposition. Partial fill via reduced temperature CVD is then performed (1208), followed by completing fill using high temperature CVD (1210) as described above with respect to FIG. 11.
  • [0080]
    In certain embodiments, the processes described herein involve exposing a deposited tungsten nucleation layer to multiple, sequential pulses of diborane or other boron-containing reducing agent. See, e.g., the above discussion with respect to FIG. 10. FIG. 16A plots resistivity of blanket tungsten films as a function of total diborane exposure (in moles) during a low-temperature multi-pulse treatment process on nucleation layers. Nucleation layer were dosed with diborane as shown, followed by CVD to deposit 50 nm or 10 nm blanket films. 50 nm tungsten film resistivity decreases with increased dose time. Unexpectedly, for the thin 10 nm film, resistivity increases with increased dose time. In certain embodiments, with thin films of about 20 nm or less, the multi-pulse treatment is not performed, or the diborane exposure is maintained at no more than about 1E-5 to 1E-3 moles total exposure.
  • [0081]
    As indicated above, partial fill of a feature using reduced temperature CVD improves resistivity. FIG. 16B plots resistivity of 50 nm blanket films deposited with partial reduced temperature (300° C.) CVD and high temperature-only (395° C.) CVD as a function of multi-pulse low resistivity tungsten (LRW) diborane pulses. The process shown in FIG. 13 was used to deposit the nucleation layer, followed by a multi-pulse treatment as represented in FIG. 14 a at 395° C. The partial reduced temperature CVD film is 6 nm, with the remainder of the film thickness deposited by high temperature CVD. Resistivities of both films decrease with an increased number of cycles of the multi-pulse treatment. However, the films with a thin reduced temperature CVD film deposited after the treatment have a lower resistivity that those films with high temperature-only CVD films. As shown, for thick films (e.g., >40 nm), the reduced temperature CVD partial fill improves resistivity. In certain embodiments, the reduced temperature CVD achieves low resistivity with a lower number of diborane pulses.
  • [0082]
    FIG. 17 shows film resistivity plotted against film thickness for the processes as described above in reference to FIGS. 10-12. For all films, a nucleation layer of about 2 nm was deposited with the nucleation layer sequence was 5×(B2H6/WF6) (H2-free ambient) at 300° C. Processes used to deposit the blanket films are shown below:
  • [0000]
    Low Low
    resistivity resistivity
    treatment treatment CVD CVD
    Process pulse sequence temperature chemistry temperature
    A 6 x (B2H6) 395° C. WF6 and H2 395° C. (only)
    B 6 x (B2H6) 395° C. WF6 and H2 300° C. (only)
    C 6 x (B2H6) 300° C. WF6 and H2 300° C. (partial
    (FIG. 12) thickness -
    about 30 Å or
    3 nm for each
    film)
    395° C.
    (remaining
    thickness)
    D 6 x (B2H6) 300° C. WF6 and H2 300° C. (only)
    E 6 x (B2H6) 300° C. WF6 and H2 395° C. (only)

    Between 8 and 15 nm, process C (a low temperature multi-pulse treatment and partial reduced temperature CVD) resulted in the lowest resistivity. Unexpectedly, partial reduced temperature CVD (process C) results in lower resistivity than reduced temperature-only CVD (process D) and high-temperature only CVD (E) for identical nucleation and treatment processes for films of about 7.5 nm and above.
  • [0083]
    Comparing process A to process E, low temperature low resistivity treatment results in lower resistivity for films less than about 9 nm thick. However, for reduced temperature-only CVD, as discussed above with respect to FIG. 9, the high temperature low-resistivity treatment (process B) results in higher resistivity than the low temperature low-resistivity process (process D) for almost all film thicknesses below about 120 nm.
  • [0084]
    In certain embodiments, reduced temperature CVD is preceded by a tungsten-precursor soak operation to lower resistivity. FIG. 18 presents a process flow illustrating operations in such a process. First, a substrate having a high aspect ratio feature is provided (1802). As with all the processes described herein, this process may also be employed with other feature geometries. Then, a tungsten nucleation layer is deposited in the feature by any appropriate method (1804), followed by a multi-pulse treatment (1806) as described above with reference to FIGS. 14A and 14B. At this point, the substrate is exposed to the tungsten-precursor, without the presence of reducing agent, in a tungsten-precursor soak operation (1808). Soak time may be between about 0.5 seconds to 10 seconds, e.g., about 1-5 seconds. Temperature during the soak operation may be the same temperature as the subsequent reduced temperature CVD, e.g., 300° C. After the tungsten-precursor soak, the feature is then filled with reduced temperature CVD tungsten film (1810). In alternative embodiments, the tungsten-precursor soak may be performed prior to partial fill reduced temperature CVD.
  • [0085]
    FIG. 19 is a plot of thin film resistivity as function of film thickness for films deposited by reduced temperature CVD with and without a WF6 soak. For all films, a nucleation layer was deposited using the process shown in FIG. 13, followed by a multi-pulse diborane low resistivity treatment. For films between about 8-12 nm, soaking achieves lower resistivity than the process without soaking. In certain embodiments, the process described in FIG. 18 is used to achieve low resistivity with the high quality plugfill described above with reference to FIG. 3.
  • [0086]
    Apparatus
  • [0087]
    The methods of the invention may be carried out in various types of deposition apparatus available from various vendors. Examples of suitable apparatus include a Novellus Concept-1 Altus™, a Concept 2 Altus™, a Concept-2 ALTUS-S™, Concept 3 Altus™ deposition system, and Altus Max™ or any of a variety of other commercially available CVD tools. In some cases, the process can be performed on multiple deposition stations sequentially. See, e.g., U.S. Pat. No. 6,143,082, which is incorporated herein by reference for all purposes. In some embodiments, a nucleation layer is deposited, e.g., by a pulsed nucleation process at a first station that is one of two, five or even more deposition stations positioned within a single deposition chamber. Thus, the reducing gases and the tungsten-containing gases are alternately introduced to the surface of the semiconductor substrate, at the first station, using an individual gas supply system that creates a localized atmosphere at the substrate surface.
  • [0088]
    A second station may then be used to complete nucleation layer deposition or to perform a multi-pulse low resistivity treatment. In certain embodiments, a single pulse low resistivity treatment may be performed.
  • [0089]
    One or more stations are then used to perform CVD as described above. Two or more stations may be used to perform CVD in a parallel processing. Alternatively a wafer may be indexed to have the CVD operations performed over two or more stations sequentially. For example, in processes involving both low temperature and high temperature CVD operations, a wafer or other substrate is indexed from one CVD station to another for each operation.
  • [0090]
    FIG. 20 is a block diagram of a processing system suitable for conducting tungsten thin film deposition processes in accordance with embodiments of the invention. The system 2000 includes a transfer module 2003. The transfer module 2003 provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between the various reactor modules. Mounted on the transfer module 2003 is a multi-station reactor 2009 capable of performing PNL deposition, multi-pulse treatment if desired, and CVD according to embodiments of the invention. Chamber 2009 may include multiple stations 2011, 2013, 2015, and 2017 that may sequentially perform these operations. For example, chamber 2009 could be configured such that station 2011 performs PNL deposition, station 2013 performs multi-pulse treatment, and stations 2015 and 2017 perform CVD. Each deposition station includes a heated wafer pedestal and a showerhead, dispersion plate or other gas inlet. An example of a deposition station 2100 is depicted in FIG. 21, including wafer support 2102 and showerhead 2103. A heater may be provided in pedestal portion 2101.
  • [0091]
    Also mounted on the transfer module 2003 may be one or more single or multi-station modules 2007 capable of performing plasma or chemical (non-plasma) pre-cleans. The module may also be used for various other treatments, e.g., post liner tungsten nitride treatments. The system 2000 also includes one or more (in this case two) wafer source modules 2001 where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 2019 first removes wafers from the source modules 2001 to loadlocks 2021. A wafer transfer device (generally a robot arm unit) in the transfer module 2003 moves the wafers from loadlocks 2021 to and among the modules mounted on the transfer module 2003.
  • [0092]
    In certain embodiments, a system controller 2029 is employed to control process conditions during deposition. The controller will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.
  • [0093]
    The controller may control all of the activities of the deposition apparatus. The system controller executes system control software including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, RF power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored on memory devices associated with the controller may be employed in some embodiments.
  • [0094]
    Typically there will be a user interface associated with the controller. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
  • [0095]
    The computer program code for controlling the deposition and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program.
  • [0096]
    The controller parameters relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, plasma conditions such as RF power levels and the low frequency RF frequency, cooling gas pressure, and chamber wall temperature. These parameters are provided to the user in the form of a recipe, and may be entered utilizing the user interface.
  • [0097]
    Signals for monitoring the process may be provided by analog and/or digital input connections of the system controller. The signals for controlling the process are output on the analog and digital output connections of the deposition apparatus.
  • [0098]
    The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the inventive deposition processes. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.
  • [0099]
    A substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and/or target. A process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into the chamber prior to deposition in order to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck.
  • [0100]
    Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions. The foregoing describes implementation of embodiments of the invention in a single or multi-chamber semiconductor processing tool.
  • [0101]
    Applications
  • [0102]
    The present invention may be used to deposit thin, low resistivity tungsten layers for many different applications. One application is vias, contacts and other tungsten structures commonly found in electronic devices. Another application are interconnects in integrated circuits such as memory chips and microprocessors. Interconnects are current lines found on a single metallization layer and are generally long thin flat structures. A primary example of an interconnect application is a bit line in a memory chip. In general, the invention finds application in any environment where thin, low-resistivity tungsten layers are required.
  • Other Embodiments
  • [0103]
    While this invention has been described in terms of several embodiments, there are alterations, modifications, permutations, and substitute equivalents, which fall within the scope of this invention. For example, while the above description is chiefly in the context of feature fill, the methods described above may also be used to deposit low resistivity tungsten films on blanket surfaces. These may be formed by a blanket deposition of a tungsten layer (by a process as described above), followed by a patterning operation that defines the location of current carrying tungsten lines and removal of the tungsten from regions outside the tungsten lines.
  • [0104]
    It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and substitute equivalents as fall within the true spirit and scope of the present invention.

Claims (19)

  1. 1. A method of filling a recessed feature on a substrate, the method comprising:
    providing a substrate having a field region and a first feature recessed from the field region, said recessed feature comprising sidewalls, a bottom, an opening, and corners;
    depositing a tungsten nucleation layer on the sidewalls and bottom of the recessed feature; and
    filling the feature with a low temperature CVD tungsten bulk layer via a chemical vapor deposition (CVD) process; wherein the substrate temperature during the CVD process is maintained at between about 250° C. and 350° C.
  2. 2. The method of claim 1, further comprising after filling the first recessed feature, raising the substrate temperature at least about 50° C. and, after raising the substrate temperature, depositing a high temperature bulk tungsten CVD layer on the filled first recessed feature.
  3. 3. The method of claim 1 wherein the first recessed feature has an aspect ratio of at least 10:1.
  4. 4. The method of claim 1 wherein the first recessed feature has an aspect ratio of at least 20:1.
  5. 5. The method of claim 1 wherein width of the first recessed feature opening is no more than about 100 nm.
  6. 6. The method of claim 1 wherein width of the first recessed feature opening is no more than about 50 nm.
  7. 7. The method of claim 1 wherein the width of the first recessed feature opening is no more than about 40 nm.
  8. 8. The method of claim 1 wherein filling the first recessed feature comprises covering the feature corners with the low temperature CVD bulk layer.
  9. 9. The method of claim 1 wherein the substrate further comprises a second feature recessed from the field region, said second recessed feature having an aspect ratio lower than that of the first feature.
  10. 10. The method of claim 9 further comprising, after filling the first recessed feature, raising the substrate temperature at least about 50° C. and, after raising the substrate temperature, depositing a high temperature bulk tungsten CVD layer to fill the second recessed feature.
  11. 11. The method of claim 1 wherein filling the feature with a low temperature CVD tungsten bulk layer comprises introducing a halogenated tungsten-containing precursor and a reducing agent into a reaction station housing the substrate.
  12. 12. The method of claim 11 wherein the halogenated tungsten-containing precursor is tungsten hexafluoride.
  13. 13. The method of claim 1 wherein the feature comprises a liner layer.
  14. 14. The method of claim 13 wherein the liner layer is a Ti/TiN layer.
  15. 15. The method of claim 13 wherein the liner layer has a thickness of no more than 5 nm.
  16. 16. The method of claim 1 further comprising, after depositing a tungsten nucleation layer on the sidewalls and bottom of the recessed feature and prior to filling the feature with a low temperature CVD tungsten bulk layer, soaking the substrate with a tungsten-precursor.
  17. 17. The method of claim 1 wherein substrate temperature during the CVD process is maintained at between about 250° C. and 325° C.
  18. 18. An apparatus for depositing tungsten film on a substrate comprising:
    a) a multistation substrate deposition chamber comprising:
    a tungsten nucleation layer deposition station, the deposition station comprising a substrate support and one or more gas inlets configured to expose the substrate to pulses of gas;
    a bulk layer deposition station, the tungsten bulk layer deposition station comprising a substrate support and one or more gas inlets configured to expose the substrate to gases; and
    b) a controller for controlling the operations in the multistation deposition chamber, comprising machine readable instructions for:
    pulsing a plurality of reducing agent pulse/purge gas pulse/tungsten-containing precursor pulse cycles in the tungsten nucleation layer deposition station to deposit on tungsten nucleation layer on the substrate surface;
    transferring the substrate from the tungsten nucleation layer deposition station to the bulk layer deposition station; and
    simultaneously flowing reducing agent and tungsten-containing precursor into the bulk layer deposition station while maintaining a substrate temperature of between about 250° C. and 350° C.
  19. 19. The apparatus of claim 18 further comprising a low-resistivity treatment station, the low-resistivity treatment station comprising a substrate support and one or more gas inlets configured to expose the substrate to pulses of gas; wherein controller further comprises machine readable instructions for pulsing a plurality of reducing agent pulses into the low-resistivity treatment station and wherein the instructions for transferring the substrate from the tungsten nucleation layer deposition station to the bulk layer deposition station comprise instructions for transferring the substrate from the tungsten nucleation layer deposition station to the low-resistivity treatment station and instructions for transferring the substrate from the low-resistivity treatment station to the bulk layer deposition station.
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Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100159694A1 (en) * 2008-06-12 2010-06-24 Novellus Systems Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US20100273327A1 (en) * 2007-12-05 2010-10-28 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US20110059608A1 (en) * 2009-09-09 2011-03-10 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US20110221044A1 (en) * 2010-03-12 2011-09-15 Michal Danek Tungsten barrier and seed for copper filled tsv
US20110223763A1 (en) * 2001-05-22 2011-09-15 Lana Hiului Chan Methods for growing low-resistivity tungsten for high aspect ratio and small features
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US8101521B1 (en) 2007-07-24 2012-01-24 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US8367546B2 (en) 2007-12-21 2013-02-05 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8546250B2 (en) 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
WO2014058536A1 (en) * 2012-10-11 2014-04-17 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US8883637B2 (en) 2011-06-30 2014-11-11 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
US20160071764A9 (en) * 2009-08-04 2016-03-10 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US9589835B2 (en) 2008-12-10 2017-03-07 Novellus Systems, Inc. Method for forming tungsten film having low resistivity, low roughness and high reflectivity
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
EP3206222A1 (en) * 2016-02-02 2017-08-16 Semiconductor Manufacturing International Corporation (Shanghai) Method and system for uniform deposition of metal
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
WO2015026491A1 (en) * 2013-08-19 2015-02-26 Applied Materials, Inc. Apparatus for impurity layered epitaxy
US9899234B2 (en) 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
US9449921B1 (en) * 2015-12-15 2016-09-20 International Business Machines Corporation Voidless contact metal structures

Citations (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746375A (en) * 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
US4804560A (en) * 1986-03-17 1989-02-14 Fujitsu Limited Method of selectively depositing tungsten upon a semiconductor substrate
US5028565A (en) * 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
US5227329A (en) * 1990-08-31 1993-07-13 Hitachi, Ltd. Method of manufacturing semiconductor device
US5250329A (en) * 1989-04-06 1993-10-05 Microelectronics And Computer Technology Corporation Method of depositing conductive lines on a dielectric
US5326723A (en) * 1992-09-09 1994-07-05 Intel Corporation Method for improving stability of tungsten chemical vapor deposition
US5391394A (en) * 1990-01-08 1995-02-21 Lsi Logic Corporation Tungsten deposition process for low contact resistivity to silicon
US5661080A (en) * 1992-12-10 1997-08-26 Hyundai Electronics Industries Co., Ltd. Method for fabricating tungsten plug
US5726096A (en) * 1993-12-17 1998-03-10 Hyundai Electronics Industries Co., Ltd. Method for forming a tungsten silicide layer in a semiconductor device
US5795824A (en) * 1997-08-28 1998-08-18 Novellus Systems, Inc. Method for nucleation of CVD tungsten films
US5804249A (en) * 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US5817576A (en) * 1994-09-27 1998-10-06 Applied Materials, Inc. Utilization of SiH4 soak and purge in deposition processes
US5926720A (en) * 1997-09-08 1999-07-20 Lsi Logic Corporation Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
US5956609A (en) * 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US6017818A (en) * 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US6037263A (en) * 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6066366A (en) * 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6099904A (en) * 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
US6107200A (en) * 1998-03-12 2000-08-22 Fujitsu Limited Semiconductor device manufacturing method
US6143082A (en) * 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
US6174812B1 (en) * 1999-06-08 2001-01-16 United Microelectronics Corp. Copper damascene technology for ultra large scale integration circuits
US6245654B1 (en) * 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US20010008808A1 (en) * 1995-10-25 2001-07-19 Fernando Gonzalez A Method Of Fabricating A DRAM Transistor With A Dual Gate Oxide Technique
US6265312B1 (en) * 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US20010014533A1 (en) * 1999-01-08 2001-08-16 Shih-Wei Sun Method of fabricating salicide
US6277744B1 (en) * 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US20010015494A1 (en) * 1997-06-13 2001-08-23 Kie Y. Ahn Integrated circuit wiring with low rc time delay
US6294468B1 (en) * 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6297152B1 (en) * 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
US6309966B1 (en) * 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
US20010044041A1 (en) * 2000-05-18 2001-11-22 Badding Michael E. High performance solid electrolyte fuel cells
US6355558B1 (en) * 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6404054B1 (en) * 1998-10-28 2002-06-11 Samsung Electronics Co., Ltd. Tungsten layer formation method for semiconductor device and semiconductor device using the same
US20020090796A1 (en) * 1999-09-13 2002-07-11 Applied Materials, Inc. Silicon layer to improve plug filling by CVD
US6465347B2 (en) * 1998-12-18 2002-10-15 Tokyo Electron Limited Tungsten film forming method
US20020177316A1 (en) * 2000-11-16 2002-11-28 Miller Anne E. Slurry and method for chemical mechanical polishing of copper
US20030059980A1 (en) * 2001-09-25 2003-03-27 Ling Chen Copper interconnect barrier layer structure and formation method
US6551929B1 (en) * 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6566250B1 (en) * 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
US6566262B1 (en) * 2001-11-01 2003-05-20 Lsi Logic Corporation Method for creating self-aligned alloy capping layers for copper interconnect structures
US20030104126A1 (en) * 2001-10-10 2003-06-05 Hongbin Fang Method for depositing refractory metal layers employing sequential deposition techniques
US20030127043A1 (en) * 2001-07-13 2003-07-10 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US6593233B1 (en) * 1995-03-03 2003-07-15 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US6635965B1 (en) * 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US20040014315A1 (en) * 2001-07-16 2004-01-22 Applied Materials, Inc. Formation of composite tungsten films
US20040044127A1 (en) * 2002-08-22 2004-03-04 Konica Corporation Organic-inorganic hybrid film, its manufacturing method, optical film, and polarizing film
US6706625B1 (en) * 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6720261B1 (en) * 1999-06-02 2004-04-13 Agere Systems Inc. Method and system for eliminating extrusions in semiconductor vias
US6740585B2 (en) * 2001-07-25 2004-05-25 Applied Materials, Inc. Barrier formation using novel sputter deposition method with PVD, CVD, or ALD
US20040142557A1 (en) * 2003-01-21 2004-07-22 Novellus Systems, Inc. Deposition of tungsten nitride
US20040202786A1 (en) * 2001-05-22 2004-10-14 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US20040206267A1 (en) * 2002-12-23 2004-10-21 Sankar Sambasivan Aluminum phosphate coatings
US6844258B1 (en) * 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US20050031786A1 (en) * 2001-05-22 2005-02-10 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US6861356B2 (en) * 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US20050059236A1 (en) * 2003-09-11 2005-03-17 Akio Nishida Semiconductor device and a method of manufacturing the same
US6902763B1 (en) * 1999-10-15 2005-06-07 Asm International N.V. Method for depositing nanolaminate thin films on sensitive surfaces
US6905543B1 (en) * 2002-06-19 2005-06-14 Novellus Systems, Inc Methods of forming tungsten nucleation layer
US6908848B2 (en) * 2000-12-20 2005-06-21 Samsung Electronics, Co., Ltd. Method for forming an electrical interconnection providing improved surface morphology of tungsten
US20050136594A1 (en) * 2003-12-23 2005-06-23 Hynix Semiconductor Inc. Method for forming bit-line of semiconductor device
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US6962873B1 (en) * 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
US20060003581A1 (en) * 2004-06-30 2006-01-05 Johnston Steven W Atomic layer deposited tantalum containing adhesion layer
US20070099420A1 (en) * 2005-11-02 2007-05-03 Dominguez Juan E Direct tailoring of the composition and density of ALD films
US7220671B2 (en) * 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
US20070190780A1 (en) * 2003-06-18 2007-08-16 Applied Materials, Inc. Atomic layer deposition of barrier materials
US20080081127A1 (en) * 2006-09-28 2008-04-03 Thompson David M Organometallic compounds, processes for the preparation thereof and methods of use thereof
US20080124926A1 (en) * 2001-05-22 2008-05-29 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7416979B2 (en) * 2001-07-25 2008-08-26 Applied Materials, Inc. Deposition methods for barrier and tungsten materials
US7429402B2 (en) * 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US20080254623A1 (en) * 2001-05-22 2008-10-16 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US20090163025A1 (en) * 2007-12-21 2009-06-25 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US7655567B1 (en) * 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US20100055900A1 (en) * 2008-09-02 2010-03-04 Jae-Hyun Kang Mask and method for fabricating semiconductor device using the same
US20100159694A1 (en) * 2008-06-12 2010-06-24 Novellus Systems Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US7754604B2 (en) * 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
US7772114B2 (en) * 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US20100267235A1 (en) * 2009-04-16 2010-10-21 Feng Chen Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US20110059608A1 (en) * 2009-09-09 2011-03-10 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US20110221044A1 (en) * 2010-03-12 2011-09-15 Michal Danek Tungsten barrier and seed for copper filled tsv

Family Cites Families (154)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1763823B1 (en) * 1968-08-16 1971-11-11 Ellenberger & Poensgen Electromagnetic Ignition Switch anchor with a rotary magnet for einphaseninduktionsmotoren
JPS6133894B2 (en) 1979-08-16 1986-08-05 Toshiba Tungaloy Co Ltd
JPS62260340A (en) 1986-05-06 1987-11-12 Toshiba Corp Manufacture of semiconductor device
US4962063A (en) 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
GB8907898D0 (en) 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
US5250467A (en) 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
US5308655A (en) 1991-08-16 1994-05-03 Materials Research Corporation Processing for forming low resistivity titanium nitride films
US5567583A (en) 1991-12-16 1996-10-22 Biotronics Corporation Methods for reducing non-specific priming in DNA detection
US5370739A (en) 1992-06-15 1994-12-06 Materials Research Corporation Rotating susceptor semiconductor wafer processing cluster tool module useful for tungsten CVD
JPH08115984A (en) 1994-10-17 1996-05-07 Hitachi Ltd Semiconductor device and its manufacture
US6001729A (en) 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JPH0927596A (en) 1995-07-11 1997-01-28 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5833817A (en) 1996-04-22 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving conformity and contact bottom coverage of sputtered titanium nitride barrier layers
US5633200A (en) 1996-05-24 1997-05-27 Micron Technology, Inc. Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer
US5963833A (en) 1996-07-03 1999-10-05 Micron Technology, Inc. Method for cleaning semiconductor wafers and
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US5916634A (en) 1996-10-01 1999-06-29 Sandia Corporation Chemical vapor deposition of W-Si-N and W-B-N
KR100214852B1 (en) * 1996-11-02 1999-08-02 김영환 Forming method for metal wiring in semiconductor device
US6310300B1 (en) 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
KR100255516B1 (en) * 1996-11-28 2000-05-01 김영환 A metal wire of semiconductor device and forming method thereof
JP3090074B2 (en) 1997-01-20 2000-09-18 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6156382A (en) 1997-05-16 2000-12-05 Applied Materials, Inc. Chemical vapor deposition process for depositing tungsten
US6287965B1 (en) 1997-07-28 2001-09-11 Samsung Electronics Co, Ltd. Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
US5913145A (en) 1997-08-28 1999-06-15 Texas Instruments Incorporated Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
US6452276B1 (en) 1998-04-30 2002-09-17 International Business Machines Corporation Ultra thin, single phase, diffusion barrier for metal conductors
JP2000188401A (en) 1998-12-22 2000-07-04 Hyundai Electronics Ind Co Ltd Method of forming gate electrode of semiconductor device
JP3206578B2 (en) * 1999-01-11 2001-09-10 日本電気株式会社 The method of manufacturing a semiconductor device having a multilayer wiring structure
JP4570704B2 (en) 1999-02-17 2010-10-27 株式会社アルバック Barrier film manufacturing method
US6306211B1 (en) 1999-03-23 2001-10-23 Matsushita Electric Industrial Co., Ltd. Method for growing semiconductor film and method for fabricating semiconductor device
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
WO2001016405A1 (en) 1999-08-30 2001-03-08 Ebara Corporation Method for measuring leveler concentration of plating solution, and method and apparatus for controlling plating solution
US6924226B2 (en) * 1999-10-02 2005-08-02 Uri Cohen Methods for making multiple seed layers for metallic interconnects
US6610151B1 (en) * 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
FI117944B (en) 1999-10-15 2007-04-30 Asm Int The method of growing siirtymämetallinitridiohutkalvojen
EP1221178A1 (en) 1999-10-15 2002-07-10 ASM America, Inc. Method for depositing nanolaminate thin films on sensitive surfaces
JP4191900B2 (en) 2000-01-06 2008-12-03 三星電子株式会社Samsung Electronics Co.,Ltd. Method of forming a tungsten contact plugs of a semiconductor device
US6777331B2 (en) * 2000-03-07 2004-08-17 Simplus Systems Corporation Multilayered copper structure for improving adhesion property
US6429126B1 (en) * 2000-03-29 2002-08-06 Applied Materials, Inc. Reduced fluorine contamination for tungsten CVD
JP3651360B2 (en) 2000-05-19 2005-05-25 株式会社村田製作所 The method of forming the electrode film
US7253076B1 (en) * 2000-06-08 2007-08-07 Micron Technologies, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6875212B2 (en) * 2000-06-23 2005-04-05 Vertelink Corporation Curable media for implantable medical device
US6620723B1 (en) * 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US7732327B2 (en) * 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7101795B1 (en) * 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7405158B2 (en) * 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6491978B1 (en) 2000-07-10 2002-12-10 Applied Materials, Inc. Deposition of CVD layers for copper metallization using novel metal organic chemical vapor deposition (MOCVD) precursors
US6218301B1 (en) 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
EP1203950B1 (en) 2000-11-02 2005-09-07 Shipley Company, L.L.C. Plating bath analysis
WO2002041379A1 (en) * 2000-11-17 2002-05-23 Tokyo Electron Limited Method of forming metal wiring and semiconductor manufacturing apparatus for forming metal wiring
KR100375230B1 (en) * 2000-12-20 2003-03-08 삼성전자주식회사 Method for forming an interconnection of semiconductor device having a smooth surface
KR100399417B1 (en) 2001-01-08 2003-09-26 삼성전자주식회사 A method for preparing of integrated circuit of semiconductor
US20020117399A1 (en) * 2001-02-23 2002-08-29 Applied Materials, Inc. Atomically thin highly resistive barrier layer in a copper via
KR20020072996A (en) 2001-03-14 2002-09-19 주성엔지니어링(주) Method for forming a metal plug
US6740221B2 (en) 2001-03-15 2004-05-25 Applied Materials Inc. Method of forming copper interconnects
US20020190379A1 (en) 2001-03-28 2002-12-19 Applied Materials, Inc. W-CVD with fluorine-free tungsten nucleation
US20020168840A1 (en) 2001-05-11 2002-11-14 Applied Materials, Inc. Deposition of tungsten silicide films
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US6686278B2 (en) 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
JP4032872B2 (en) * 2001-08-14 2008-01-16 東京エレクトロン株式会社 Method of forming a tungsten film
JP4595989B2 (en) 2001-08-24 2010-12-08 東京エレクトロン株式会社 Film formation method
JP2003142484A (en) 2001-10-31 2003-05-16 Mitsubishi Electric Corp Method of manufacturing semiconductor device
US20030091739A1 (en) * 2001-11-14 2003-05-15 Hitoshi Sakamoto Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus
US20030091870A1 (en) 2001-11-15 2003-05-15 Siddhartha Bhowmik Method of forming a liner for tungsten plugs
US20030123216A1 (en) 2001-12-27 2003-07-03 Yoon Hyungsuk A. Deposition of tungsten for the formation of conformal tungsten silicide
US6998014B2 (en) * 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6833161B2 (en) * 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
KR100446300B1 (en) 2002-05-30 2004-08-30 삼성전자주식회사 Method for forming metal interconnections of semiconductor device
US20030224217A1 (en) 2002-05-31 2003-12-04 Applied Materials, Inc. Metal nitride formation
US7144488B2 (en) 2002-06-05 2006-12-05 Shipley Company, L.L.C. Electrode, electrochemical cell, and method for analysis of electroplating baths
JP2004235456A (en) * 2003-01-30 2004-08-19 Seiko Epson Corp Film depositing system, film depositing process, and process for manufacturing semiconductor device
US7713592B2 (en) 2003-02-04 2010-05-11 Tegal Corporation Nanolayer deposition process
JP3956049B2 (en) * 2003-03-07 2007-08-08 東京エレクトロン株式会社 Method of forming a tungsten film
JP2005029821A (en) 2003-07-09 2005-02-03 Tokyo Electron Ltd Film-forming method
US7078341B2 (en) 2003-09-30 2006-07-18 Tokyo Electron Limited Method of depositing metal layers from metal-carbonyl precursors
US6924223B2 (en) 2003-09-30 2005-08-02 Tokyo Electron Limited Method of forming a metal layer using an intermittent precursor gas flow process
US20050139838A1 (en) 2003-12-26 2005-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR101108304B1 (en) 2004-02-26 2012-01-25 노벨러스 시스템즈, 인코포레이티드 Deposition of tungsten nitride
CN100370585C (en) * 2004-04-12 2008-02-20 株式会社爱发科 Method of forming barrier film and method of forming electrode film
KR101166236B1 (en) 2004-04-21 2012-07-17 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Method for the thermal treatment of tungsten electrodes free from thorium oxide for high-pressure discharge lamps
US8495305B2 (en) * 2004-06-30 2013-07-23 Citrix Systems, Inc. Method and device for performing caching of dynamically generated objects in a data communication network
US20060145190A1 (en) 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100642750B1 (en) 2005-01-31 2006-11-10 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US7344983B2 (en) 2005-03-18 2008-03-18 International Business Machines Corporation Clustered surface preparation for silicide and metal contacts
JP4738178B2 (en) 2005-06-17 2011-08-03 富士通セミコンダクター株式会社 A method of manufacturing a semiconductor device
JP4945937B2 (en) 2005-07-01 2012-06-06 東京エレクトロン株式会社 Method of forming a tungsten film, the film forming apparatus and a storage medium
JP4864368B2 (en) 2005-07-21 2012-02-01 シャープ株式会社 Vapor deposition method
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7235485B2 (en) 2005-10-14 2007-06-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
US7276796B1 (en) 2006-03-15 2007-10-02 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
JP2007250907A (en) 2006-03-16 2007-09-27 Renesas Technology Corp Semiconductor device and manufacturing method therefor
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
WO2007121249A3 (en) 2006-04-11 2007-12-27 Applied Materials Inc Process for forming cobalt-containing materials
US7557047B2 (en) 2006-06-09 2009-07-07 Micron Technology, Inc. Method of forming a layer of material using an atomic layer deposition process
KR100884339B1 (en) * 2006-06-29 2009-02-18 주식회사 하이닉스반도체 Method for forming W film and method for forming W connection line in semiconductor device
KR100705936B1 (en) 2006-06-30 2007-04-03 주식회사 하이닉스반도체 Method for forming bitline of semiconductor device
US7355254B2 (en) 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts
GB0614049D0 (en) * 2006-07-14 2006-08-23 Pabari Alpa S Comb
KR100894769B1 (en) 2006-09-29 2009-04-24 주식회사 하이닉스반도체 Method of forming a metal wire in a semiconductor device
KR100881391B1 (en) 2006-09-29 2009-02-05 주식회사 하이닉스반도체 Method for forming gate of semiconductor device
KR20080036679A (en) * 2006-10-24 2008-04-29 삼성전자주식회사 Method of forming a non-volatile memory device
US7675119B2 (en) 2006-12-25 2010-03-09 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
US20080254619A1 (en) 2007-04-14 2008-10-16 Tsang-Jung Lin Method of fabricating a semiconductor device
KR20080101745A (en) * 2007-05-15 2008-11-21 어플라이드 머티어리얼스, 인코포레이티드 Atomic layer deposition of tungsten materials
JP2008288289A (en) 2007-05-16 2008-11-27 Oki Electric Ind Co Ltd Field-effect transistor and its manufacturing method
US7879222B2 (en) 2007-08-27 2011-02-01 Eci Technology, Inc. Detection of additive breakdown products in acid copper plating baths
KR101564473B1 (en) 2007-11-21 2015-10-29 램 리써치 코포레이션 Method of controlling etch microloading for a tungsten-containing layer
US8080324B2 (en) 2007-12-03 2011-12-20 Kobe Steel, Ltd. Hard coating excellent in sliding property and method for forming same
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
KR101163825B1 (en) 2008-03-28 2012-07-09 도쿄엘렉트론가부시키가이샤 Electrostatic chuck and manufacturing method thereof
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US20100072623A1 (en) 2008-09-19 2010-03-25 Advanced Micro Devices, Inc. Semiconductor device with improved contact plugs, and related fabrication methods
JP2010093116A (en) 2008-10-09 2010-04-22 Panasonic Corp Semiconductor device and method for manufacturing the same
US7825024B2 (en) * 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US8110877B2 (en) * 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
WO2010077847A3 (en) 2008-12-31 2010-09-23 Applied Materials, Inc. Method of depositing tungsten film with reduced resistivity and improved surface morphology
DE102009015747B4 (en) 2009-03-31 2013-08-08 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg A process for the fabrication of transistors with metal gate electrodes and gate dielectric structures with large ε and a Zwischenätzstoppschicht
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US8039394B2 (en) 2009-06-26 2011-10-18 Seagate Technology Llc Methods of forming layers of alpha-tantalum
US20160071764A9 (en) 2009-08-04 2016-03-10 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR20140143202A (en) 2012-03-27 2014-12-15 노벨러스 시스템즈, 인코포레이티드 Tungsten feature fill with nucleation inhibition
US20120294874A1 (en) 2009-11-19 2012-11-22 Paul Anthony Macary Method for Producing T Cell Receptor-Like Monoclonal Antibodies and Uses Thereof
DE102009055392B4 (en) * 2009-12-30 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Semiconductor device and method of manufacturing the semiconductor device
US9129945B2 (en) 2010-03-24 2015-09-08 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
US9034768B2 (en) * 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8778797B2 (en) 2010-09-27 2014-07-15 Novellus Systems, Inc. Systems and methods for selective tungsten deposition in vias
US20120199887A1 (en) 2011-02-03 2012-08-09 Lana Chan Methods of controlling tungsten film properties
US20120225191A1 (en) 2011-03-01 2012-09-06 Applied Materials, Inc. Apparatus and Process for Atomic Layer Deposition
US8865594B2 (en) 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8546250B2 (en) 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8916435B2 (en) 2011-09-09 2014-12-23 International Business Machines Corporation Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory
US8617985B2 (en) 2011-10-28 2013-12-31 Applied Materials, Inc. High temperature tungsten metallization process
KR20140113947A (en) 2011-12-12 2014-09-25 노벨러스 시스템즈, 인코포레이티드 Monitoring leveler concentrations in electroplating solutions
WO2013148880A1 (en) 2012-03-27 2013-10-03 Novellus Systems, Inc. Tungsten feature fill
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
KR20140029041A (en) 2012-08-31 2014-03-10 에스케이하이닉스 주식회사 Semiconductor device with fluorine free tungsten barrier layer and method for fabricating the same
KR20140028992A (en) 2012-08-31 2014-03-10 에스케이하이닉스 주식회사 Semiconductor device with tungsten gate electrode and method for fabricating the same
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US8975142B2 (en) 2013-04-25 2015-03-10 Globalfoundries Inc. FinFET channel stress using tungsten contacts in raised epitaxial source and drain
US9362163B2 (en) 2013-07-30 2016-06-07 Lam Research Corporation Methods and apparatuses for atomic layer cleaning of contacts and vias
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4804560A (en) * 1986-03-17 1989-02-14 Fujitsu Limited Method of selectively depositing tungsten upon a semiconductor substrate
US4746375A (en) * 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
US5250329A (en) * 1989-04-06 1993-10-05 Microelectronics And Computer Technology Corporation Method of depositing conductive lines on a dielectric
US5028565A (en) * 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
US5391394A (en) * 1990-01-08 1995-02-21 Lsi Logic Corporation Tungsten deposition process for low contact resistivity to silicon
US5227329A (en) * 1990-08-31 1993-07-13 Hitachi, Ltd. Method of manufacturing semiconductor device
US5326723A (en) * 1992-09-09 1994-07-05 Intel Corporation Method for improving stability of tungsten chemical vapor deposition
US5661080A (en) * 1992-12-10 1997-08-26 Hyundai Electronics Industries Co., Ltd. Method for fabricating tungsten plug
US5726096A (en) * 1993-12-17 1998-03-10 Hyundai Electronics Industries Co., Ltd. Method for forming a tungsten silicide layer in a semiconductor device
US5817576A (en) * 1994-09-27 1998-10-06 Applied Materials, Inc. Utilization of SiH4 soak and purge in deposition processes
US6593233B1 (en) * 1995-03-03 2003-07-15 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US20010008808A1 (en) * 1995-10-25 2001-07-19 Fernando Gonzalez A Method Of Fabricating A DRAM Transistor With A Dual Gate Oxide Technique
US6017818A (en) * 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US6297152B1 (en) * 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
US5804249A (en) * 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US20010015494A1 (en) * 1997-06-13 2001-08-23 Kie Y. Ahn Integrated circuit wiring with low rc time delay
US5956609A (en) * 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5795824A (en) * 1997-08-28 1998-08-18 Novellus Systems, Inc. Method for nucleation of CVD tungsten films
US5926720A (en) * 1997-09-08 1999-07-20 Lsi Logic Corporation Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
US6861356B2 (en) * 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6099904A (en) * 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
US6206967B1 (en) * 1997-12-02 2001-03-27 Applied Materials, Inc. Low resistivity W using B2H6 nucleation step
US6107200A (en) * 1998-03-12 2000-08-22 Fujitsu Limited Semiconductor device manufacturing method
US6066366A (en) * 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6143082A (en) * 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
US6404054B1 (en) * 1998-10-28 2002-06-11 Samsung Electronics Co., Ltd. Tungsten layer formation method for semiconductor device and semiconductor device using the same
US6037263A (en) * 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6465347B2 (en) * 1998-12-18 2002-10-15 Tokyo Electron Limited Tungsten film forming method
US20010014533A1 (en) * 1999-01-08 2001-08-16 Shih-Wei Sun Method of fabricating salicide
US6245654B1 (en) * 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6294468B1 (en) * 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6720261B1 (en) * 1999-06-02 2004-04-13 Agere Systems Inc. Method and system for eliminating extrusions in semiconductor vias
US6174812B1 (en) * 1999-06-08 2001-01-16 United Microelectronics Corp. Copper damascene technology for ultra large scale integration circuits
US6355558B1 (en) * 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6265312B1 (en) * 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US6309966B1 (en) * 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
US20020090796A1 (en) * 1999-09-13 2002-07-11 Applied Materials, Inc. Silicon layer to improve plug filling by CVD
US6902763B1 (en) * 1999-10-15 2005-06-07 Asm International N.V. Method for depositing nanolaminate thin films on sensitive surfaces
US6277744B1 (en) * 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US20010044041A1 (en) * 2000-05-18 2001-11-22 Badding Michael E. High performance solid electrolyte fuel cells
US6551929B1 (en) * 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US20020177316A1 (en) * 2000-11-16 2002-11-28 Miller Anne E. Slurry and method for chemical mechanical polishing of copper
US6908848B2 (en) * 2000-12-20 2005-06-21 Samsung Electronics, Co., Ltd. Method for forming an electrical interconnection providing improved surface morphology of tungsten
US20080124926A1 (en) * 2001-05-22 2008-05-29 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US20110223763A1 (en) * 2001-05-22 2011-09-15 Lana Hiului Chan Methods for growing low-resistivity tungsten for high aspect ratio and small features
US6635965B1 (en) * 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7141494B2 (en) * 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7955972B2 (en) * 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US20100035427A1 (en) * 2001-05-22 2010-02-11 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7589017B2 (en) * 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7262125B2 (en) * 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US20080254623A1 (en) * 2001-05-22 2008-10-16 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US20050031786A1 (en) * 2001-05-22 2005-02-10 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US20040202786A1 (en) * 2001-05-22 2004-10-14 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7211144B2 (en) * 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US20030127043A1 (en) * 2001-07-13 2003-07-10 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US6939804B2 (en) * 2001-07-16 2005-09-06 Applied Materials, Inc. Formation of composite tungsten films
US20040014315A1 (en) * 2001-07-16 2004-01-22 Applied Materials, Inc. Formation of composite tungsten films
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7416979B2 (en) * 2001-07-25 2008-08-26 Applied Materials, Inc. Deposition methods for barrier and tungsten materials
US6740585B2 (en) * 2001-07-25 2004-05-25 Applied Materials, Inc. Barrier formation using novel sputter deposition method with PVD, CVD, or ALD
US20030059980A1 (en) * 2001-09-25 2003-03-27 Ling Chen Copper interconnect barrier layer structure and formation method
US6607976B2 (en) * 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
US20030104126A1 (en) * 2001-10-10 2003-06-05 Hongbin Fang Method for depositing refractory metal layers employing sequential deposition techniques
US6797340B2 (en) * 2001-10-10 2004-09-28 Applied Materials, Inc. Method for depositing refractory metal layers employing sequential deposition techniques
US6566262B1 (en) * 2001-11-01 2003-05-20 Lsi Logic Corporation Method for creating self-aligned alloy capping layers for copper interconnect structures
US6566250B1 (en) * 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
US6905543B1 (en) * 2002-06-19 2005-06-14 Novellus Systems, Inc Methods of forming tungsten nucleation layer
US20040044127A1 (en) * 2002-08-22 2004-03-04 Konica Corporation Organic-inorganic hybrid film, its manufacturing method, optical film, and polarizing film
US6706625B1 (en) * 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6962873B1 (en) * 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
US20040206267A1 (en) * 2002-12-23 2004-10-21 Sankar Sambasivan Aluminum phosphate coatings
US7691749B2 (en) * 2003-01-21 2010-04-06 Novellus Systems, Inc. Deposition of tungsten nitride
US7005372B2 (en) * 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US20060094238A1 (en) * 2003-01-21 2006-05-04 Novellus Systems, Inc. Deposition of tungsten nitride
US20040142557A1 (en) * 2003-01-21 2004-07-22 Novellus Systems, Inc. Deposition of tungsten nitride
US7157798B1 (en) * 2003-05-09 2007-01-02 Novellus Systems, Inc. Selective refractory metal and nitride capping
US6844258B1 (en) * 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US20070190780A1 (en) * 2003-06-18 2007-08-16 Applied Materials, Inc. Atomic layer deposition of barrier materials
US7754604B2 (en) * 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
US20050059236A1 (en) * 2003-09-11 2005-03-17 Akio Nishida Semiconductor device and a method of manufacturing the same
US20050136594A1 (en) * 2003-12-23 2005-06-23 Hynix Semiconductor Inc. Method for forming bit-line of semiconductor device
US20060003581A1 (en) * 2004-06-30 2006-01-05 Johnston Steven W Atomic layer deposited tantalum containing adhesion layer
US7429402B2 (en) * 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US7220671B2 (en) * 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
US20070099420A1 (en) * 2005-11-02 2007-05-03 Dominguez Juan E Direct tailoring of the composition and density of ALD films
US20080081127A1 (en) * 2006-09-28 2008-04-03 Thompson David M Organometallic compounds, processes for the preparation thereof and methods of use thereof
US7655567B1 (en) * 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US8101521B1 (en) * 2007-07-24 2012-01-24 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US20100273327A1 (en) * 2007-12-05 2010-10-28 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US7772114B2 (en) * 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US20090163025A1 (en) * 2007-12-21 2009-06-25 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US20120040530A1 (en) * 2007-12-21 2012-02-16 Raashina Humayun Methods for forming all tungsten contacts and lines
US20120015518A1 (en) * 2008-06-12 2012-01-19 Anand Chandrashekar Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US20100159694A1 (en) * 2008-06-12 2010-06-24 Novellus Systems Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US20100055900A1 (en) * 2008-09-02 2010-03-04 Jae-Hyun Kang Mask and method for fabricating semiconductor device using the same
US20100267235A1 (en) * 2009-04-16 2010-10-21 Feng Chen Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US20110059608A1 (en) * 2009-09-09 2011-03-10 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US20110221044A1 (en) * 2010-03-12 2011-09-15 Michal Danek Tungsten barrier and seed for copper filled tsv

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110223763A1 (en) * 2001-05-22 2011-09-15 Lana Hiului Chan Methods for growing low-resistivity tungsten for high aspect ratio and small features
US9583385B2 (en) 2001-05-22 2017-02-28 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US8409985B2 (en) 2001-05-22 2013-04-02 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US8101521B1 (en) 2007-07-24 2012-01-24 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US20100273327A1 (en) * 2007-12-05 2010-10-28 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8329576B2 (en) 2007-12-05 2012-12-11 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8367546B2 (en) 2007-12-21 2013-02-05 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US20100159694A1 (en) * 2008-06-12 2010-06-24 Novellus Systems Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8409987B2 (en) 2008-06-12 2013-04-02 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US9589835B2 (en) 2008-12-10 2017-03-07 Novellus Systems, Inc. Method for forming tungsten film having low resistivity, low roughness and high reflectivity
US9673146B2 (en) 2009-04-16 2017-06-06 Novellus Systems, Inc. Low temperature tungsten film deposition for small critical dimension contacts and interconnects
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US9236297B2 (en) 2009-04-16 2016-01-12 Novellus Systems, Inc. Low tempature tungsten film deposition for small critical dimension contacts and interconnects
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US9653353B2 (en) 2009-08-04 2017-05-16 Novellus Systems, Inc. Tungsten feature fill
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US20160071764A9 (en) * 2009-08-04 2016-03-10 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US20110059608A1 (en) * 2009-09-09 2011-03-10 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US8207062B2 (en) 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US20110221044A1 (en) * 2010-03-12 2011-09-15 Michal Danek Tungsten barrier and seed for copper filled tsv
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US8883637B2 (en) 2011-06-30 2014-11-11 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials
US8841676B2 (en) 2011-08-18 2014-09-23 Wafertech, Llc Vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8546250B2 (en) 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
WO2014058536A1 (en) * 2012-10-11 2014-04-17 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US9966307B2 (en) 2016-02-02 2018-05-08 Semiconductor Manufacturing International (Shanghai) Corporation Method and system for uniform deposition of metal
EP3206222A1 (en) * 2016-02-02 2017-08-16 Semiconductor Manufacturing International Corporation (Shanghai) Method and system for uniform deposition of metal

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