US20170133231A1 - Method for depositing extremely low resistivity tungsten - Google Patents

Method for depositing extremely low resistivity tungsten Download PDF

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US20170133231A1
US20170133231A1 US15/415,800 US201715415800A US2017133231A1 US 20170133231 A1 US20170133231 A1 US 20170133231A1 US 201715415800 A US201715415800 A US 201715415800A US 2017133231 A1 US2017133231 A1 US 2017133231A1
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tungsten
annealing
tungsten film
deposition
resistivity
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Hanna Bamnolker
Raashina Humayun
Deqi Wang
Yan Guan
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Lam Research Corp
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Lam Research Corp
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14Deposition of only one other metal element
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers

Definitions

  • Tungsten film deposition using chemical vapor deposition techniques is an integral part of semiconductor fabrication processes.
  • Tungsten films may be used as low resistivity electrical connections in the form of horizontal interconnects, vias between adjacent metal layers, and contacts between a first metal layer and the devices on a silicon substrate.
  • a barrier layer is deposited on a dielectric substrate, followed by deposition of a nucleation or seed layer of tungsten film. Thereafter, the remainder of the tungsten film is deposited on the nucleation layer as a bulk layer.
  • the tungsten bulk layer is formed by the reduction of tungsten hexafluoride (WF 6 ) with hydrogen (H 2 ) in a chemical vapor deposition (CVD) process.
  • a method of forming a tungsten film on a substrate includes providing the substrate with a nitride layer, annealing the nitride layer, and depositing tungsten on the nitride layer to form the tungsten film such that the nitride layer is annealed before tungsten is deposited.
  • the nitride layer is a titanium nitride layer or a tungsten nitride layer.
  • the titanium nitride film is annealed at a temperature between about 385° C. and about 445° C.
  • argon gas is flowed during annealing.
  • the tungsten may be deposited by chemical vapor deposition.
  • the nitride layer may be annealed at conditions to change the grain structure of the nitride layer.
  • Another aspect is a method of forming tungsten film by annealing a nitride film on a substrate, depositing bulk tungsten on the nitride film to form the tungsten film, and annealing the tungsten film.
  • the method also includes depositing a tungsten nucleation layer on the nitride film after annealing the nitride film, and annealing the tungsten nucleation layer before depositing the bulk tungsten.
  • the nucleation layer is annealed at a temperature between about 385° C. and about 445°.
  • the tungsten film is annealed for no more than 1 minute.
  • the annealing pressure may be at least 1 Torr.
  • Another aspect is a method of forming a tungsten film on a substrate in a reaction chamber.
  • the method includes depositing tungsten on the substrate to form the tungsten film and annealing the tungsten film to thereby lower the resistivity at a chamber pressure of at least about 1 Torr.
  • the tungsten film is annealed at a temperature between about 385° C. and about 445° C.
  • boron is used during deposition of the tungsten film, and the tungsten film has a boron content of less than about 1%.
  • the tungsten film is annealed for a duration between about 1 second and about 10 minutes.
  • Another aspect is a method of forming a tungsten film on a substrate in a reaction chamber.
  • the method may involve depositing tungsten on the substrate to form the tungsten film at a deposition pressure and annealing the tungsten film to thereby lower the resistivity at the deposition pressure.
  • FIG. 1 is a schematic illustration of a feature filled with tungsten nucleation and bulk layers according to certain embodiments.
  • FIG. 2 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 3 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 4 depicts schematic illustrations of feature cross-sections at various stages of a process according to certain embodiments.
  • FIG. 5 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 6 shows a block diagram of a processing system for practicing methods in accordance with the disclosed embodiments.
  • FIG. 7 shows a graph representing experimental data on annealing time in accordance with various embodiments.
  • FIGS. 8A and 8B show graphs representing experimental data on annealing temperature in accordance with various embodiments.
  • FIG. 9 shows a graph representing experimental data on timing of an annealing step in accordance with various embodiments.
  • FIGS. 10A and 10B show graphs representing experimental data on boron content in accordance with various embodiments.
  • FIG. 11 shows an image of deposited layers.
  • FIG. 12 shows an image of deposited layers in accordance with various embodiments.
  • FIGS. 13A and 13B show graphs representing experimental data on flow chemistry in accordance with various embodiments.
  • tungsten (W) fill As devices scale to smaller technology nodes.
  • One challenge is preventing an increase in resistance due to the thinner films in contacts and vias.
  • the tungsten contact or line resistance increases due to scattering effects in the thinner tungsten film.
  • Conventional chemical vapor deposition (CVD) tungsten deposition processes involve depositing a barrier layer of titanium nitride (TiN), followed by nucleation deposition, and then a CVD bulk tungsten deposition. While efficient tungsten deposition processes use tungsten nucleation layers, these layers typically have higher electrical resistivities than the bulk layers. As features become smaller, low resistivity tungsten films minimize power losses and overheating in integrated circuit designs.
  • the thin barrier and tungsten nucleation films which have higher resistivity, occupy a larger percentage of the smaller features.
  • FIG. 1 shows a volume occupied by a nucleation film 110 and a bulk tungsten material 120 in a via or contact structure 100 .
  • the resistivity of the nucleation layer is higher than that of the bulk layer ( ⁇ nucleation > ⁇ bulk ) the thickness of the nucleation layer should be minimized to keep the total resistance as low as possible.
  • the tungsten nucleation should be sufficiently thick to fully cover the underlying substrate to support high quality bulk deposition. Resistivity of a tungsten film depends on the thickness of the film deposited. For example, conventional methods may yield a 50 ⁇ tungsten film with a resistivity of 60 ⁇ -cm. In another example, conventional methods may yield a 100 ⁇ film with a resistivity of 30 ⁇ -cm.
  • tungsten films are provided herein. Methods involve annealing layers during certain times of the deposition process at various conditions. Resulting tungsten films in accordance with the disclosed embodiments have resistivities up to 20% lower than conventionally deposited tungsten films.
  • annealing may occur after deposition of a layer in a separate annealing chamber, or may occur in a deposition chamber altered to accommodate annealing methods.
  • annealing operations may be conducted with an air break between deposition of a layer and a subsequent annealing, typically without processing operations, without negative effects on the tungsten deposition or resistivity.
  • An air break may last between about 1 second and about 12 hours. An air break can allow annealing operations to be performed in different tools than previous or subsequent deposition or other processing operations, as the substrate does not have to be kept under vacuum.
  • annealing is performed prior to the deposition of tungsten. In some implementations, annealing is performed after deposition of tungsten. In some implementations, annealing is performed both before and after the deposition of tungsten. Also, in some implementations, annealing can be performed after deposition of a nucleation layer of tungsten. As discussed further below, these aspects result in tungsten films having improved resistivity.
  • the methods described herein may be used to deposit tungsten in a feature formed in a substrate.
  • a feature may have an aspect ratio of at least 10:1, at least 15:1, at least 20:1, at least 25:1, or at least 30:1.
  • the feature size can be characterized by the feature opening size in addition to or instead of the aspect ratio.
  • the opening may be from about 10 nm to about 100 nm wide in some embodiments.
  • the methods may be advantageously used with features having narrow openings, regardless of the aspect ratio.
  • the methods may further be advantageously used to deposit tungsten in larger and/or smaller aspect ratio features, as well to deposit blanket or planar tungsten layers.
  • a recessed feature is formed within a dielectric layer on a substrate, with the bottom of the feature providing contact to an underlying metal layer.
  • the feature includes a liner layer such as a diffusion barrier layer on its sidewalls and/or bottom.
  • liner layers include titanium nitride (TiN) layers including titanium/titanium nitride (Ti/TiN), and tungsten nitride (WN).
  • the feature may include layers such as an adhesion layer, a nucleation layer, a combination thereof, or any other applicable material lining the sidewalls and the bottom of the feature.
  • the feature is a re-entrant feature; with a liner layer or other material forming an overhang that partially blocks the feature opening. Because many deposition processes do not have good step coverage properties and result in more material being deposited on the field region and near the opening than inside the feature, a liner layer may be thicker near the opening than inside the feature.
  • “near the opening” is defined as an approximate position or an area within the feature (i.e., along the side wall of the feature) corresponding to between about 0% and about 10% of the feature depth measured from the field region. In certain embodiments, the area near the opening corresponds to the area at the opening.
  • “inside the feature” is defined as an approximate position or an area within the feature corresponding to between about 20% and about 60% of the feature depth measured from the field region on the top of the feature.
  • values for certain parameters e.g., thicknesses
  • these values represent a measurement or an average of multiple measurements taken within these positions/areas.
  • an average thickness of an underlayer near the opening is at least about 10% greater than that inside the feature. In more specific embodiments, this difference may be at least about 25%, at least about 50%, or at least about 100%. Distribution of a material within a feature may also be characterized by its step coverage.
  • step coverage is defined as a ratio of two thicknesses, i.e., thickness of the material inside the feature divided by the thickness of the material near the opening.
  • the step coverage of the liner or other underlayer is less than about 100% or, more specifically, less than about 75% or even less than about 50%.
  • Embodiments described herein may involve deposition of tungsten nucleation layers and/or bulk layers for features.
  • a description of methods of depositing tungsten nucleation layers and bulk layers that may be used in methods of the present disclosure is provided below. It should be noted however, that other methods of nucleation and/or bulk layer deposition may also be used.
  • a tungsten nucleation layer may be deposited in a feature to conformally coat the sidewalls and bottom of the feature.
  • a nucleation layer is a thin conformal layer that serves to facilitate the subsequent formation of a bulk material thereon. Conforming to the underlying feature bottom and sidewalls can be critical to support high quality deposition.
  • Various processes may be used to form the nucleation layer, including but not limited to, CVD processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, and pulsed nucleation layer (PNL) deposition processes.
  • PNL pulses of reactant are sequentially injected and purged from the reaction chamber, typically by a pulse of a purge gas between reactants.
  • a first reactant is typically adsorbed onto the substrate, available to react with the next reactant.
  • the process is repeated in a cyclical fashion until the desired thickness is achieved.
  • PNL is similar to ALD techniques. PNL is generally distinguished from ALD by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer film growth per cycle). Chamber pressure during PNL deposition may range from about 1 Torr to about 400 Torr.
  • PNL broadly embodies any cyclical process of sequentially adding reactants for reaction on a semiconductor substrate.
  • CVD embodies processes in which reactants are together introduced to a reactor for a vapor-phase reaction.
  • PNL and ALD processes are distinct from CVD processes and vice versa.
  • Forming a nucleation layer using one or more PNL cycles is discussed in U.S. Pat. Nos. 6,844,258; 7,005,372; 7,141,494; 7,262,125; 7,589,017; 7,772,114; 7,955,972; and 8,058,170, all of which are incorporated herein by this reference.
  • These PNL deposition processes involve exposing a substrate to various sequences of reducing agents and tungsten precursors to grow a nucleation layer of the desired thickness.
  • a combined PNL-CVD method of depositing a nucleation layer is described in U.S. Pat. No. 7,655,567, also incorporated herein by reference.
  • Nucleation layer thickness can be enough to support high quality deposition. In certain embodiments, the requisite thickness depends in part on the nucleation layer deposition method.
  • a PNL method providing near 100% step coverage with nucleation film thicknesses as low as about 12 ⁇ (as compared to typical nucleation films of 50 ⁇ ) may be used in certain embodiments.
  • a low temperature CVD operation used to fill the feature can afford use of thinner nucleation layers than required by conventional higher temperature CVD. Without being bound by a particular theory, it is believed that this may be because the lower chemistry at the reduced temperatures improves growth even on the nucleation sites that are not fully developed. See, e.g., U.S. Patent Publication No. 2010/0267235, incorporated by reference herein.
  • nucleation layers may be formed as low as between about 10 ⁇ and about 15 ⁇ .
  • nucleation layer deposition is followed by a post-deposition treatment operation to improve resistivity.
  • a post-deposition treatment operation to improve resistivity.
  • CVD deposition can then occur on the nucleation layer.
  • CVD deposition of a bulk layer can involve flowing a tungsten-containing precursor and a co-reactant such as a reducing agent, if appropriate, into a deposition chamber.
  • An inert carrier gas may be used to deliver one or more of the reactant streams, which may or may not be pre-mixed.
  • this operation generally involves flowing the reactants continuously until the desired amount is deposited.
  • the CVD operation may take place in multiple stages, with multiple periods of continuous and simultaneous flow of reactants separated by periods of one or more diverted reactant flows. Flows may also be pulsed for a pulse time between about 1 second and about 2 seconds. Chamber pressure during CVD deposition may range from about 40 Torr to about 500 Torr.
  • Example substrate temperatures are as low as 250° C. and may be as high as 495° C. during the CVD reaction.
  • Various tungsten-containing gases including, but not limited to, WF 6 , tungsten chloride (WCl 6 ), and tungsten hexacarbonyl W(CO) 6 , can be used as the tungsten-containing precursor.
  • the tungsten-containing precursor is a halogen-containing compound, such as WF 6 .
  • the reducing agent is hydrogen gas, though other reducing agents may be used, including silane (SiH 4 ), disilane (Si 2 H 6 ), hydrazine (N 2 H 4 ), diborane (B 2 H 6 ), and germane (GeH 4 ).
  • CVD may be implemented in various stages, such as a low temperature stage and a high temperature stage.
  • nitrogen may be pulsed during CVD deposition of a bulk layer as described in U.S. Pat. No. 8,551,885 and U.S. patent application Ser. No. 13/633,798, both of which are incorporated by reference herein.
  • FIG. 2 provides a process flow diagram for depositing a tungsten film in which a titanium nitride underlayer is annealed.
  • Method 200 involves operation 202 of providing a substrate with a titanium nitride layer thereon.
  • the titanium nitride layer may be conformal to a high aspect ratio feature formed in the substrate.
  • Example thicknesses of the titanium nitride layer may be between about 30 ⁇ and about 300 ⁇ thick.
  • the titanium nitride layer may be an ALD-deposited layer, or a PVD-deposited layer, or CVD-deposited layer, in some implementations. It should be noted that annealing titanium nitride layers has been shown to be improved for both ALD-layers and PVD-deposited layers.
  • the annealing lowers resistivity by an effect other than or in addition to removing various impurities that might be incorporated into a film depending on the deposition (e.g., removing chloride in a titanium nitride film deposited from titanium chloride). Such an effect is discussed further below with respect to FIG. 12 .
  • the titanium nitride layer is annealed.
  • Annealing can involve flowing an inert gas at a high temperature for a time range as desired.
  • gases include argon (Ar), hydrogen (H 2 ), and combinations thereof.
  • argon (Ar) argon (Ar)
  • H 2 hydrogen
  • a mixture of argon (Ar) and hydrogen (H 2 ) is used.
  • only argon (Ar) is flowed.
  • an optional nitrogen-based gas such as nitrogen (N 2 ) or ammonia (NH 3 ), is flowed as an inert gas.
  • Substrate temperature may be higher than the temperature during deposition (such as ALD, CVD, or PVD).
  • substrate temperature may be as high as a temperature where crystal reorganization of the titanium nitride layer occurs.
  • Low resistivity films may also be achieved at relatively low temperatures, such as at a substrate temperature of less than about 500° C., or less than about 450° C.
  • substrate temperature may vary from about 385° C. to about 445° C.
  • the pressure of the station or chamber may be between about 1 mTorr to about 760 Torr. In some examples, the pressure of the station or chamber may be between about 1 Torr and about 100 Torr. In some embodiments, the pressure of the station or chamber may be at least about 1 Torr. In some embodiments, the pressure may be the same as the pressure during ALD, PVD, or CVD of the titanium nitride layer.
  • the annealing step may last about 1 second to about 10 minutes. In some embodiments, the annealing step may last between about 1 second and about 20 seconds.
  • annealing a TiN layer prior to deposition of a tungsten film lowers resistivity of a subsequently deposited tungsten film.
  • annealing the titanium nitride layer rearranges the orientation of molecules in the layer, thereby providing a preferential growth surface for nucleation of tungsten in the subsequent step.
  • Annealing the titanium nitride layer does not change the chemical composition and does not result in formation of a silicide layer.
  • the texture of the titanium nitride barrier layer may also be different and improved to allow better nucleation of tungsten.
  • FIG. 2 refers to TiN underlayers, it is believed than anneals of other underlayers, including nitrides such as WN, may have similar advantages.
  • a tungsten bulk layer is deposited on the substrate by CVD.
  • operation 206 is preceded by deposition of a tungsten nucleation as described above.
  • another annealing operation may occur after nucleation of the tungsten but before bulk deposition of the tungsten layer, using any of the conditions discussed above with respect to operation 204 .
  • transitioning from operation 204 to 206 involves moving the substrate from one deposition station to another, which may occur in a multi-station chamber.
  • Each of operation 204 and operation 206 may be performed in the same or different chamber. If performed in the same chamber, they each may be performed in the same or different stations of the same multi-station chamber or in a single station chamber. Also, operation 204 may be performed outside of a deposition chamber in a separate chamber that may or may not be in the same vacuum environment that operation 206 is performed.
  • FIG. 3 provides a process flow diagram for depositing tungsten in another embodiment.
  • a tungsten bulk layer is deposited in operation 302 .
  • Methods of deposition may be any of those discussed above.
  • the tungsten layer is annealed to lower resistivity.
  • Annealing conditions may be any of the ones previously discussed with respect to FIG. 2 , except that a non-nitrogen atmosphere may be used during anneal.
  • the anneal operation does not change the chemical composition of the tungsten layer. Accordingly, nitrogen-containing or silicon-containing atmospheres may be avoided to prevent formation of a nitride or silicide layer.
  • Example resistivities are about 41 ⁇ -cm for a 60 ⁇ layer of tungsten, or about 26 ⁇ -cm for a 110 ⁇ layer of tungsten. Percentage decrease in resistivity as compared to non-annealed tungsten layers may be between about 5% and about 35%.
  • Each of operation 302 and operation 304 may be performed in a different station of the same multi-station chamber, or in the same station of a single or multi-station chamber. Still further, they may be performed in different chambers, which may or may not be part of the same vacuum environment.
  • transitioning from operation 302 to 304 may involve shutting off a flow of tungsten precursor (operationally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature.
  • FIG. 4 illustrates schematic representations of one example of a feature's cross-sections at different stages of a filling process in which a CVD layer is deposited and annealed.
  • Cross-section 401 represents an example of the feature 410 prior to any tungsten deposition.
  • the feature 410 is formed in a dielectric layer 430 , has an opening 425 at the top surface 405 of the substrate and includes a liner layer 413 , such as a TiN layer.
  • the size of the cavity near the opening 425 is narrower than inside the feature, for example, due to overhang 415 of the liner layer 413 as depicted in FIG. 4 .
  • Cross-section 411 depicts the feature after CVD is performed to fill the feature with bulk layer. Note that the figure does not depict a nucleation layer.
  • CVD is performed until at least the feature corner 417 (the point at which the substrate transitions from a planar region to the recessed feature) is covered with CVD tungsten. As further discussed below, the CVD tungsten followed by an anneal step has low resistivity, resulting in an excellent tungsten plug.
  • Cross-section 421 represents the feature after CVD is performed and after annealing to result in an annealed CVD tungsten layer 455 .
  • annealing at high temperature after deposition of tungsten on the substrate results in purification of impurities from the tungsten film.
  • the annealing step may be releasing boron from the tungsten film, resulting in a tungsten film with less atomic boron content and lower resistivity overall.
  • FIG. 5 provides a process flow diagram showing steps for depositing a layer of tungsten including annealing prior to and after bulk tungsten deposition.
  • a layer of titanium nitride is deposited on the substrate. Methods of deposition and conditions of deposition may be any of those discussed with respect to FIG. 2 .
  • the titanium nitride layer is annealed. Any of the annealing conditions with respect to FIG. 2 may be used here.
  • a bulk tungsten layer is deposited. Conditions and methods of depositing the tungsten layer may be any of those discussed above with respect to FIG. 3 .
  • an optional nucleation layer may be deposited prior to depositing bulk tungsten.
  • the nucleation layer may also be annealed as discussed with respect to FIG. 2 .
  • the bulk tungsten layer is annealed.
  • conditions may be any of those discussed with respect to FIG. 2 , except that a non-nitrogen atmosphere may be used during the anneal.
  • a pre-tungsten deposition annealing step and post-tungsten deposition annealing step are implemented.
  • the anneal operation does not change the chemical composition of the tungsten layer. Accordingly, nitrogen-containing or silicon-containing atmospheres may be avoided to prevent formation of a nitride or silicide layer
  • transitioning from operation 504 to 506 , or 506 to 508 involves moving the substrate from one deposition station to another, which may occur in a multi-station chamber.
  • Each of these operations may be performed in the same or different chamber. If performed in the same chamber, they each may be performed in the same or different stations of the same multi-station chamber or in a single station chamber. Also, the anneal operations may be performed outside of a deposition chamber in a separate chamber that may or may not be in the same vacuum environment that the deposition operation is performed.
  • transitioning from operation 506 to 508 may involve shutting off a flow of tungsten precursor (operationally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature. Once the substrate temperature is stabilized, the tungsten precursor and other gases, if necessary, are flowed into the reaction chamber for a high temperature deposition.
  • Methods of the disclosed embodiments may be carried out in various types of deposition apparatuses available from various vendors.
  • suitable apparatuses include a Lam Concept 1 Altus, a Concept 2 Altus, a Concept 2 Altus-S, a Concept 3 Altus deposition system, or any of a variety of other commercially available CVD tools.
  • processes may be performed on multiple depositions stations sequentially.
  • the annealing step is performed at a station that is one of two, four, five, or even more deposition stations positioned within a single deposition chamber.
  • the annealing step is performed at a station on another chamber separate from the deposition chamber used for CVD.
  • an existing deposition station may be modified to accommodate an annealing step.
  • One or more stations in a chamber may be used to perform CVD, or two or more stations may be used to perform CVD in a parallel processing.
  • FIG. 6 is a block diagram of a processing system suitable for conducting tungsten thin film deposition processes in accordance with disclosed embodiments.
  • System 600 includes a transfer module 603 , which provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between various reactor modules.
  • a multi-station reactor 609 capable of performing pulsed nucleation layer (PNL) deposition, multi-pulse treatment if desired, CVD, and annealing steps according to the disclosed embodiments.
  • Chamber 609 may include multiple stations 611 , 613 , 615 , and 617 that may sequentially perform these operations.
  • chamber 609 could be configured such that station 611 performs PNL deposition, station 613 performs multi-pulse treatment, station 615 performs CVD, and station 617 performs annealing.
  • Also mounted on the transfer module 603 may be one or more single or multi-station modules 607 capable of performing plasma or chemical (non-plasma) pre-cleans.
  • the module may also be used for various other treatments, e.g., titanium nitride barrier layer deposition or post-liner tungsten nitride treatments.
  • a module 607 may be an anneal module.
  • the system 600 also includes one or more wafer source modules 601 here wafers are stored before and after processing.
  • An atmospheric robot (not shown) in the atmospheric transfer chamber 619 first removes wafers from the source modules 601 to loadlocks 621 .
  • a wafer transfer device (generally a robot arm unit) in the transfer module 603 moves the wafers from loadlocks 621 to and among the modules mounted on the transfer module 603 .
  • a system controller 650 is employed to control process conditions during deposition.
  • the controller 650 will typically include one or more memory devices and one or more processors.
  • the processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.
  • the controller 650 may control all of the activities of the deposition apparatus.
  • the system controller 650 executes system control software, including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process.
  • Other computer programs stored on memory devices associated with the control 650 may be employed in some embodiments.
  • the user interface may include a display screen, graphical software displays of the apparatus and or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
  • System control logic may be configured in any suitable way.
  • the logic can be designed or configured in hardware and/or software.
  • the instructions for controlling the drive circuitry may be hard coded or provided as software. It may be said that the instructions are provided by “programming.”
  • Such programming is understood to include logic of any form including hard coded logic in digital signal processors, application specific integrated circuits, and other devices which have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general purpose processor.
  • System control software may be coded in any suitable computer readable programming language.
  • the computer program code for controlling the deposition, annealing, and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may hard coded.
  • the controller parameters relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe, and may be entered utilizing the user interface.
  • Signals for monitoring the process may be provided by analog and/or digital input connections of the system controller 650 .
  • the signals for controlling the process are output on the analog and digital output connections of the deposition apparatus.
  • the system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the deposition processes in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.
  • a substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and/or target.
  • a process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into the chamber prior to deposition in order to stabilize the pressure in the chamber.
  • a pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber.
  • a heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck.
  • the apparatus and process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility.
  • Lithographic patterning of a film typically comprises some or all of the following steps, each step provided with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
  • a tool such as an RF or microwave plasma resist stripper.
  • Set A refers to the following set of conditions for the nucleation station.
  • Substrate temperature is set at 250° C.
  • B 2 H 6 and WF 6 are sequentially flowed for two cycles. Diversion of B 2 H 6 is set at 1 second with a B 2 H 6 purge time of 1 second and WF 6 purge time of 1 second.
  • the flow rate of WF 6 is about 180 sccm.
  • the H 2 flow of the front of the tool is about 27,000 sccm and the H 2 flow of the back of the tool is about 3000 sccm.
  • Set B refers to the following set of conditions for the nucleation station.
  • Substrate temperature is set at 250° C.
  • B 2 H 6 and WF 6 are flowed for two cycles. Diversion of B 2 H 6 is set at 1.5 seconds with a B 2 H 6 purge time of 2 seconds and WF 6 purge time of 2 seconds.
  • the flow rate of WF 6 is about 220 sccm.
  • the H 2 flow of the front of the tool is about 25,000 sccm and the H 2 flow of the back of the tool is about 10,000 sccm.
  • the second step for optional treatment involves substrates subject to five cycles of B 2 H 6 pulses flow at a substrate temperature of 325° C.
  • the step for CVD of tungsten may involve H 2 and WF 6 flow and tungsten deposition at 325° C. Varying conditions of the annealing steps are used in the following experiments.
  • Resistivity of tungsten films deposited using various anneal times was measured. For purposes of this experiment, Set A conditions were used. A 300 ⁇ titanium nitride substrate was used in this experiment. The substrate was annealed after deposition of tungsten at a temperature of 445° C. using Ar flow. The argon flow rate was about 6000 sccm. Trials were conducted to determine resistivity of both about 60 ⁇ tungsten films and about 90 ⁇ tungsten films. The results are summarized in FIG. 7 .
  • the round points indicate resistivity of the films without an annealing step.
  • the square points indicate resistivity of films using a 20-second anneal after deposition of the tungsten. Compared to the points representing no anneal, the resistivity substantially decreased.
  • the triangular points indicate resistivity of films using a 10-minute anneal after deposition of the tungsten. Compared to the points representing no anneal, the resistivity is further decreased. It is noted here that the difference between the 20-second anneal and 10-minute anneal is almost the same as the difference between the 20-second anneal and no anneal, thereby suggesting that a threshold anneal time exists such that at a point in time, further annealing will result in the same resistivity. Nonetheless, as shown in FIG. 7 , a post-deposition anneal for as short as 20 seconds can achieve substantially lower resistivity films. It is further believed that post-deposition anneals for as short as 1-5 seconds may also improve resistivity.
  • the square shaped points represent the resistivity of the annealed substrates at various temperatures.
  • the diamond shaped points represent the resistivity of each of those annealed substrates prior to the annealing step.
  • the substrate had a resistivity of about 40.8 ⁇ -cm before annealing, but after annealing the resistivity lowered to 39.6 ⁇ -cm, resulting in a resistivity improvement of about 3.0%.
  • Resistivity improvement, or the trend in decreased resistivity is shown in FIG. 8B .
  • a subsequent trial was run to compare resistivity drop for a tungsten film annealed at 445° C. for 10 minutes (not shown in figures).
  • the resulting resistivity drop was about 12.0%, substantially higher than the resistivity drop for using a 20-second anneal. According to the results, as anneal temperature increases, the difference in resistivity increases, thereby exhibiting a higher resistivity drop, and a better, lower resistivity tungsten films. The data suggests using a longer anneal time at a higher temperature to achieve the greatest resistivity drop and thus extremely low resistivity tungsten films.
  • substrates deposited without an annealing step had the highest resistivity.
  • resistivity was about 40 ⁇ -cm, as compared to a same thickness tungsten film with a post-W anneal which resulted in a resistivity of about 38 ⁇ -cm.
  • Using only a pre-W anneal had a higher resistivity for a film with a tungsten thickness of about 82 ⁇ than when both a pre-W and post-W anneal were used.
  • the data suggests that the optimal conditions for achieving extremely low resistivity tungsten films is to both anneal before and after depositing tungsten on the substrate.
  • the second wafer was deposited subject to Set B conditions as recited above, except with an added anneal step after the nucleation step, and an added anneal step instead of the last CVD deposition such that the low temperature CVD of tungsten deposited the bulk tungsten.
  • the 91 ⁇ tungsten wafer was annealed at 445° C. for 10 minutes using argon flow with a flow rate of about 6000 sccm, or Ar/H 2 flow with a flow rate of about 6000 sccm and about 7000 sccm, respectively.
  • X-ray photoelectron spectroscopy was used to evaluate the boron content.
  • the boron content in the annealed substrate had an atomic content of only 0.555%, indicating a substantial decrease by a factor of 10 in boron content as compared to the wafer that was not annealed.
  • annealing may be purifying the tungsten layer such that gases such as boron are released to decrease resistivity.
  • a second wafer with a 30 ⁇ layer of titanium nitride barrier layer was subject to conditions in Set A as recited above including an anneal after the tungsten deposition.
  • the boron content over etch time was measured and is shown in FIG. 10A and represented by 1002 .
  • a third wafer with a 30 ⁇ layer of titanium nitride as a barrier layer was subject to conditions in Set B as recited above, including an anneal after nucleation and an anneal after tungsten bulk deposition.
  • the boron content over etch time was measured and is shown in FIG. 10A and represented by 1003 . It is noted that all three wafers exhibited atomic boron content of less than 0.7%, a significantly low amount.
  • a 300 ⁇ titanium nitride barrier layer was deposited on the next wafer. This wafer was subject to conditions in Set B as recited above and did not include an anneal step. Boron content of this no-anneal wafer is represented by the solid, no-anneal line represented in FIG. 10B . Lastly, a 300 ⁇ titanium nitride barrier layer was deposited on a last wafer. This wafer was subjected to conditions in Set B as recited above, including annealing after nucleation and annealing after tungsten bulk deposition. The boron content over etch time was measured and is represented by the dotted line, labeled “with anneal” in FIG. 10B . As shown, the wafer that was annealed had an atomic content of boron less than 1%, which is significantly lower than the boron content in the non-annealed wafer, which was as high as over 5%.
  • FIGS. 10A and 10B both suggest that boron content may contribute to the resistivity of the deposited tungsten film on the substrate.
  • FIG. 11 shows an image of deposited a titanium nitride and a tungsten layer without an annealing step. As shown in FIG. 11 , an interface layer exists between the titanium nitride layer and tungsten layer.
  • FIG. 12 shows an image of a titanium nitride layer and an annealed tungsten layer.
  • the tungsten was deposited before annealing the substrate at 445° C. for 20 seconds.
  • FIG. 12 shows a substantial decrease in the interface layer and uniformity in the resulting film. This is a surprising result because the layers are smooth and have low resistivity, whereas conventional tungsten films with low resistivity may tend to be less smooth due to the granularity of the film. This phenomenon may provide support for the theory that annealing rearranges grains in the tungsten film, thereby reducing the resistivity.
  • the diamond points represent measurements of resistivity for wafers that were not annealed, whereas the square points represent measurements of resistivity for wafers annealed with Ar/H 2 and the triangular points represent measurements of resistivity for wafers annealed with only Ar.
  • the points for both the Ar/H 2 anneal and Ar anneal are very similar for similar thicknesses of tungsten, thus suggesting that using either Ar/H 2 or Ar is suitable for annealing.
  • substrates with a 300 ⁇ titanium nitride barrier layer were used.
  • the conditions from Set A as recited above were used, and wafers were annealed at 445° C. for 10 minutes after tungsten deposition using Ar only and Ar/H 2 .
  • a substrate deposited using conditions from Set A as recited above was not annealed.
  • the resulting resistivity of each of these wafers is plotted in FIG. 13B .
  • the diamond shaped points represent measurements of resistivity of wafers that were not annealed.
  • Square points represent measurements of resistivity of wafers annealed with Ar/H 2 and triangular points represent measurements of resistivity of wafers annealed with only Ar. Similar to FIG. 13A , the resulting resistivity of wafers annealed with Ar and Ar/H 2 were very similar for similar thicknesses of tungsten deposited, thereby suggesting that either Ar/H 2 or Ar can be used during the annealing process.

Abstract

Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of U.S. patent application Ser. No. 14/135,375, filed Dec. 19, 2013, and titled “METHOD FOR DEPOSITING EXTREMELY LOW RESISTIVITY TUNGSTEN”, which is incorporated by reference herein in its entirety and for all purposes.
  • BACKGROUND
  • Tungsten film deposition using chemical vapor deposition techniques is an integral part of semiconductor fabrication processes. Tungsten films may be used as low resistivity electrical connections in the form of horizontal interconnects, vias between adjacent metal layers, and contacts between a first metal layer and the devices on a silicon substrate. In a conventional tungsten deposition process, a barrier layer is deposited on a dielectric substrate, followed by deposition of a nucleation or seed layer of tungsten film. Thereafter, the remainder of the tungsten film is deposited on the nucleation layer as a bulk layer. Conventionally, the tungsten bulk layer is formed by the reduction of tungsten hexafluoride (WF6) with hydrogen (H2) in a chemical vapor deposition (CVD) process.
  • As semiconductor devices scale to smaller and smaller technology nodes, shrinking contact and via dimensions make CVD of tungsten more challenging. Increasing aspect ratios can lead to voids or large seams within device features, resulting in lower yields and decreased performance in microprocessor and memory chips. Void-free fill in high aspect ratio features of 10:1, 20:1 or greater is difficult using conventional CVD tungsten deposition techniques.
  • SUMMARY
  • Provided are methods of depositing low resistivity tungsten on a semiconductor substrate.
  • In one aspect, a method of forming a tungsten film on a substrate is provided. The method includes providing the substrate with a nitride layer, annealing the nitride layer, and depositing tungsten on the nitride layer to form the tungsten film such that the nitride layer is annealed before tungsten is deposited. In various embodiments, the nitride layer is a titanium nitride layer or a tungsten nitride layer. In some embodiments, the titanium nitride film is annealed at a temperature between about 385° C. and about 445° C. In many embodiments, argon gas is flowed during annealing. The tungsten may be deposited by chemical vapor deposition. In various embodiments, the nitride layer may be annealed at conditions to change the grain structure of the nitride layer.
  • Another aspect is a method of forming tungsten film by annealing a nitride film on a substrate, depositing bulk tungsten on the nitride film to form the tungsten film, and annealing the tungsten film. In some embodiments, the method also includes depositing a tungsten nucleation layer on the nitride film after annealing the nitride film, and annealing the tungsten nucleation layer before depositing the bulk tungsten. In various embodiments, the nucleation layer is annealed at a temperature between about 385° C. and about 445°. In various embodiments, the tungsten film is annealed for no more than 1 minute. The annealing pressure may be at least 1 Torr.
  • Another aspect is a method of forming a tungsten film on a substrate in a reaction chamber. The method includes depositing tungsten on the substrate to form the tungsten film and annealing the tungsten film to thereby lower the resistivity at a chamber pressure of at least about 1 Torr. In various embodiments, the tungsten film is annealed at a temperature between about 385° C. and about 445° C. In many embodiments, boron is used during deposition of the tungsten film, and the tungsten film has a boron content of less than about 1%. In many embodiments, the tungsten film is annealed for a duration between about 1 second and about 10 minutes.
  • Another aspect is a method of forming a tungsten film on a substrate in a reaction chamber. The method may involve depositing tungsten on the substrate to form the tungsten film at a deposition pressure and annealing the tungsten film to thereby lower the resistivity at the deposition pressure.
  • These and other aspects are described further below with reference to the drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic illustration of a feature filled with tungsten nucleation and bulk layers according to certain embodiments.
  • FIG. 2 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 3 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 4 depicts schematic illustrations of feature cross-sections at various stages of a process according to certain embodiments.
  • FIG. 5 is a process flow diagram for depositing tungsten in accordance with various embodiments.
  • FIG. 6 shows a block diagram of a processing system for practicing methods in accordance with the disclosed embodiments.
  • FIG. 7 shows a graph representing experimental data on annealing time in accordance with various embodiments.
  • FIGS. 8A and 8B show graphs representing experimental data on annealing temperature in accordance with various embodiments.
  • FIG. 9 shows a graph representing experimental data on timing of an annealing step in accordance with various embodiments.
  • FIGS. 10A and 10B show graphs representing experimental data on boron content in accordance with various embodiments.
  • FIG. 11 shows an image of deposited layers.
  • FIG. 12 shows an image of deposited layers in accordance with various embodiments.
  • FIGS. 13A and 13B show graphs representing experimental data on flow chemistry in accordance with various embodiments.
  • DETAILED DESCRIPTION
  • In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.
  • There are various challenges in tungsten (W) fill as devices scale to smaller technology nodes. One challenge is preventing an increase in resistance due to the thinner films in contacts and vias. As features become smaller, the tungsten contact or line resistance increases due to scattering effects in the thinner tungsten film. Conventional chemical vapor deposition (CVD) tungsten deposition processes involve depositing a barrier layer of titanium nitride (TiN), followed by nucleation deposition, and then a CVD bulk tungsten deposition. While efficient tungsten deposition processes use tungsten nucleation layers, these layers typically have higher electrical resistivities than the bulk layers. As features become smaller, low resistivity tungsten films minimize power losses and overheating in integrated circuit designs. The thin barrier and tungsten nucleation films, which have higher resistivity, occupy a larger percentage of the smaller features.
  • FIG. 1 shows a volume occupied by a nucleation film 110 and a bulk tungsten material 120 in a via or contact structure 100. Because the resistivity of the nucleation layer is higher than that of the bulk layer (ρnucleationbulk) the thickness of the nucleation layer should be minimized to keep the total resistance as low as possible. On the other hand, the tungsten nucleation should be sufficiently thick to fully cover the underlying substrate to support high quality bulk deposition. Resistivity of a tungsten film depends on the thickness of the film deposited. For example, conventional methods may yield a 50 Å tungsten film with a resistivity of 60 μΩ-cm. In another example, conventional methods may yield a 100 Å film with a resistivity of 30 μΩ-cm.
  • Provided herein are methods of depositing extremely low resistivity thin tungsten films on substrates. Methods involve annealing layers during certain times of the deposition process at various conditions. Resulting tungsten films in accordance with the disclosed embodiments have resistivities up to 20% lower than conventionally deposited tungsten films.
  • According to various implementations, annealing may occur after deposition of a layer in a separate annealing chamber, or may occur in a deposition chamber altered to accommodate annealing methods. In some implementations, annealing operations may be conducted with an air break between deposition of a layer and a subsequent annealing, typically without processing operations, without negative effects on the tungsten deposition or resistivity. An air break may last between about 1 second and about 12 hours. An air break can allow annealing operations to be performed in different tools than previous or subsequent deposition or other processing operations, as the substrate does not have to be kept under vacuum.
  • In some implementations, annealing is performed prior to the deposition of tungsten. In some implementations, annealing is performed after deposition of tungsten. In some implementations, annealing is performed both before and after the deposition of tungsten. Also, in some implementations, annealing can be performed after deposition of a nucleation layer of tungsten. As discussed further below, these aspects result in tungsten films having improved resistivity.
  • According to various embodiments, the methods described herein may be used to deposit tungsten in a feature formed in a substrate. Such a feature may have an aspect ratio of at least 10:1, at least 15:1, at least 20:1, at least 25:1, or at least 30:1. The feature size can be characterized by the feature opening size in addition to or instead of the aspect ratio. The opening may be from about 10 nm to about 100 nm wide in some embodiments. For example, in certain embodiments, the methods may be advantageously used with features having narrow openings, regardless of the aspect ratio. The methods may further be advantageously used to deposit tungsten in larger and/or smaller aspect ratio features, as well to deposit blanket or planar tungsten layers.
  • In certain embodiments, a recessed feature is formed within a dielectric layer on a substrate, with the bottom of the feature providing contact to an underlying metal layer. Also in certain embodiments, the feature includes a liner layer such as a diffusion barrier layer on its sidewalls and/or bottom. Examples of liner layers include titanium nitride (TiN) layers including titanium/titanium nitride (Ti/TiN), and tungsten nitride (WN). In additional to or instead of diffusion barrier layers, the feature may include layers such as an adhesion layer, a nucleation layer, a combination thereof, or any other applicable material lining the sidewalls and the bottom of the feature.
  • In certain embodiments, the feature is a re-entrant feature; with a liner layer or other material forming an overhang that partially blocks the feature opening. Because many deposition processes do not have good step coverage properties and result in more material being deposited on the field region and near the opening than inside the feature, a liner layer may be thicker near the opening than inside the feature. For the purposes of this description, “near the opening” is defined as an approximate position or an area within the feature (i.e., along the side wall of the feature) corresponding to between about 0% and about 10% of the feature depth measured from the field region. In certain embodiments, the area near the opening corresponds to the area at the opening. Further, “inside the feature” is defined as an approximate position or an area within the feature corresponding to between about 20% and about 60% of the feature depth measured from the field region on the top of the feature. Typically, when values for certain parameters (e.g., thicknesses) are specified “near the opening” or “inside the feature,” these values represent a measurement or an average of multiple measurements taken within these positions/areas. In certain embodiments, an average thickness of an underlayer near the opening is at least about 10% greater than that inside the feature. In more specific embodiments, this difference may be at least about 25%, at least about 50%, or at least about 100%. Distribution of a material within a feature may also be characterized by its step coverage. For the purposes of this description, “step coverage” is defined as a ratio of two thicknesses, i.e., thickness of the material inside the feature divided by the thickness of the material near the opening. In certain examples, the step coverage of the liner or other underlayer is less than about 100% or, more specifically, less than about 75% or even less than about 50%.
  • Embodiments described herein may involve deposition of tungsten nucleation layers and/or bulk layers for features. For context, a description of methods of depositing tungsten nucleation layers and bulk layers that may be used in methods of the present disclosure is provided below. It should be noted however, that other methods of nucleation and/or bulk layer deposition may also be used.
  • A tungsten nucleation layer may be deposited in a feature to conformally coat the sidewalls and bottom of the feature. In general, a nucleation layer is a thin conformal layer that serves to facilitate the subsequent formation of a bulk material thereon. Conforming to the underlying feature bottom and sidewalls can be critical to support high quality deposition. Various processes may be used to form the nucleation layer, including but not limited to, CVD processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, and pulsed nucleation layer (PNL) deposition processes.
  • In a PNL technique, pulses of reactant are sequentially injected and purged from the reaction chamber, typically by a pulse of a purge gas between reactants. A first reactant is typically adsorbed onto the substrate, available to react with the next reactant. The process is repeated in a cyclical fashion until the desired thickness is achieved. PNL is similar to ALD techniques. PNL is generally distinguished from ALD by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer film growth per cycle). Chamber pressure during PNL deposition may range from about 1 Torr to about 400 Torr. In the context of the description provided herein, PNL broadly embodies any cyclical process of sequentially adding reactants for reaction on a semiconductor substrate. Thus, the concept embodies techniques conventionally referred to as ALD. In the context of the disclosed embodiments, CVD embodies processes in which reactants are together introduced to a reactor for a vapor-phase reaction. PNL and ALD processes are distinct from CVD processes and vice versa.
  • Forming a nucleation layer using one or more PNL cycles is discussed in U.S. Pat. Nos. 6,844,258; 7,005,372; 7,141,494; 7,262,125; 7,589,017; 7,772,114; 7,955,972; and 8,058,170, all of which are incorporated herein by this reference. These PNL deposition processes involve exposing a substrate to various sequences of reducing agents and tungsten precursors to grow a nucleation layer of the desired thickness. A combined PNL-CVD method of depositing a nucleation layer is described in U.S. Pat. No. 7,655,567, also incorporated herein by reference.
  • Nucleation layer thickness can be enough to support high quality deposition. In certain embodiments, the requisite thickness depends in part on the nucleation layer deposition method. A PNL method providing near 100% step coverage with nucleation film thicknesses as low as about 12 Å (as compared to typical nucleation films of 50 Å) may be used in certain embodiments. Regardless of the method used to deposit the nucleation layer, however, in some embodiments a low temperature CVD operation used to fill the feature can afford use of thinner nucleation layers than required by conventional higher temperature CVD. Without being bound by a particular theory, it is believed that this may be because the lower chemistry at the reduced temperatures improves growth even on the nucleation sites that are not fully developed. See, e.g., U.S. Patent Publication No. 2010/0267235, incorporated by reference herein. According to various embodiments, nucleation layers may be formed as low as between about 10 Å and about 15 Å.
  • In certain embodiments, nucleation layer deposition is followed by a post-deposition treatment operation to improve resistivity. Such treatment operations are described further below and in more detail in U.S. Pat. Nos. 7,772,114 and 8,058,170, both of which are incorporated by reference herein.
  • CVD deposition can then occur on the nucleation layer. CVD deposition of a bulk layer can involve flowing a tungsten-containing precursor and a co-reactant such as a reducing agent, if appropriate, into a deposition chamber. An inert carrier gas may be used to deliver one or more of the reactant streams, which may or may not be pre-mixed. Unlike PNL or ALD processes, this operation generally involves flowing the reactants continuously until the desired amount is deposited. In certain embodiments, the CVD operation may take place in multiple stages, with multiple periods of continuous and simultaneous flow of reactants separated by periods of one or more diverted reactant flows. Flows may also be pulsed for a pulse time between about 1 second and about 2 seconds. Chamber pressure during CVD deposition may range from about 40 Torr to about 500 Torr.
  • Example substrate temperatures are as low as 250° C. and may be as high as 495° C. during the CVD reaction. Various tungsten-containing gases including, but not limited to, WF6, tungsten chloride (WCl6), and tungsten hexacarbonyl W(CO)6, can be used as the tungsten-containing precursor. In certain embodiments, the tungsten-containing precursor is a halogen-containing compound, such as WF6. In certain embodiments, the reducing agent is hydrogen gas, though other reducing agents may be used, including silane (SiH4), disilane (Si2H6), hydrazine (N2H4), diborane (B2H6), and germane (GeH4). In some embodiments, CVD may be implemented in various stages, such as a low temperature stage and a high temperature stage. Still further, nitrogen may be pulsed during CVD deposition of a bulk layer as described in U.S. Pat. No. 8,551,885 and U.S. patent application Ser. No. 13/633,798, both of which are incorporated by reference herein.
  • FIG. 2 provides a process flow diagram for depositing a tungsten film in which a titanium nitride underlayer is annealed. Method 200 involves operation 202 of providing a substrate with a titanium nitride layer thereon. The titanium nitride layer may be conformal to a high aspect ratio feature formed in the substrate. Example thicknesses of the titanium nitride layer may be between about 30 Å and about 300 Å thick. The titanium nitride layer may be an ALD-deposited layer, or a PVD-deposited layer, or CVD-deposited layer, in some implementations. It should be noted that annealing titanium nitride layers has been shown to be improved for both ALD-layers and PVD-deposited layers. This indicates that the annealing lowers resistivity by an effect other than or in addition to removing various impurities that might be incorporated into a film depending on the deposition (e.g., removing chloride in a titanium nitride film deposited from titanium chloride). Such an effect is discussed further below with respect to FIG. 12.
  • Next, in operation 204, the titanium nitride layer is annealed. Annealing can involve flowing an inert gas at a high temperature for a time range as desired. Examples of gases include argon (Ar), hydrogen (H2), and combinations thereof. In various embodiments, a mixture of argon (Ar) and hydrogen (H2) is used. In many embodiments, only argon (Ar) is flowed. In some embodiments, an optional nitrogen-based gas, such as nitrogen (N2) or ammonia (NH3), is flowed as an inert gas. Substrate temperature may be higher than the temperature during deposition (such as ALD, CVD, or PVD). In various embodiments, substrate temperature may be as high as a temperature where crystal reorganization of the titanium nitride layer occurs. Low resistivity films may also be achieved at relatively low temperatures, such as at a substrate temperature of less than about 500° C., or less than about 450° C. As an example, substrate temperature may vary from about 385° C. to about 445° C.
  • In various embodiments, the pressure of the station or chamber may be between about 1 mTorr to about 760 Torr. In some examples, the pressure of the station or chamber may be between about 1 Torr and about 100 Torr. In some embodiments, the pressure of the station or chamber may be at least about 1 Torr. In some embodiments, the pressure may be the same as the pressure during ALD, PVD, or CVD of the titanium nitride layer.
  • In various embodiments, the annealing step may last about 1 second to about 10 minutes. In some embodiments, the annealing step may last between about 1 second and about 20 seconds.
  • As discussed further below, with reference to FIGS. 7, 8A, 8B, 9, 13A, and 13B, it has been found that annealing a TiN layer prior to deposition of a tungsten film lowers resistivity of a subsequently deposited tungsten film. Without being bound to a particular theory, it is believed that annealing the titanium nitride layer rearranges the orientation of molecules in the layer, thereby providing a preferential growth surface for nucleation of tungsten in the subsequent step. Annealing the titanium nitride layer does not change the chemical composition and does not result in formation of a silicide layer. The texture of the titanium nitride barrier layer may also be different and improved to allow better nucleation of tungsten. Better nucleation results in better adhesion to the surface, thereby reducing the resistivity and providing a smoother, more uniform tungsten layer. Further, while FIG. 2 refers to TiN underlayers, it is believed than anneals of other underlayers, including nitrides such as WN, may have similar advantages.
  • In operation 206, a tungsten bulk layer is deposited on the substrate by CVD. According to various embodiments, operation 206 is preceded by deposition of a tungsten nucleation as described above. In some embodiments, another annealing operation may occur after nucleation of the tungsten but before bulk deposition of the tungsten layer, using any of the conditions discussed above with respect to operation 204.
  • In certain embodiments, transitioning from operation 204 to 206, involves moving the substrate from one deposition station to another, which may occur in a multi-station chamber. Each of operation 204 and operation 206 may be performed in the same or different chamber. If performed in the same chamber, they each may be performed in the same or different stations of the same multi-station chamber or in a single station chamber. Also, operation 204 may be performed outside of a deposition chamber in a separate chamber that may or may not be in the same vacuum environment that operation 206 is performed.
  • FIG. 3 provides a process flow diagram for depositing tungsten in another embodiment. In method 300, a tungsten bulk layer is deposited in operation 302. Methods of deposition may be any of those discussed above. Next, in operation 304, the tungsten layer is annealed to lower resistivity. Annealing conditions may be any of the ones previously discussed with respect to FIG. 2, except that a non-nitrogen atmosphere may be used during anneal. In general, while it may remove some impurities from the tungsten layer, the anneal operation does not change the chemical composition of the tungsten layer. Accordingly, nitrogen-containing or silicon-containing atmospheres may be avoided to prevent formation of a nitride or silicide layer.
  • Example resistivities are about 41 μΩ-cm for a 60 Å layer of tungsten, or about 26 μΩ-cm for a 110 Å layer of tungsten. Percentage decrease in resistivity as compared to non-annealed tungsten layers may be between about 5% and about 35%.
  • Each of operation 302 and operation 304 may be performed in a different station of the same multi-station chamber, or in the same station of a single or multi-station chamber. Still further, they may be performed in different chambers, which may or may not be part of the same vacuum environment.
  • In embodiments in which a single station is used to perform operations 302 and 304, transitioning from operation 302 to 304 may involve shutting off a flow of tungsten precursor (operationally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature.
  • FIG. 4 illustrates schematic representations of one example of a feature's cross-sections at different stages of a filling process in which a CVD layer is deposited and annealed. Cross-section 401 represents an example of the feature 410 prior to any tungsten deposition. In this example, the feature 410 is formed in a dielectric layer 430, has an opening 425 at the top surface 405 of the substrate and includes a liner layer 413, such as a TiN layer. In certain embodiments, the size of the cavity near the opening 425 is narrower than inside the feature, for example, due to overhang 415 of the liner layer 413 as depicted in FIG. 4.
  • Cross-section 411 depicts the feature after CVD is performed to fill the feature with bulk layer. Note that the figure does not depict a nucleation layer. In certain embodiments, CVD is performed until at least the feature corner 417 (the point at which the substrate transitions from a planar region to the recessed feature) is covered with CVD tungsten. As further discussed below, the CVD tungsten followed by an anneal step has low resistivity, resulting in an excellent tungsten plug.
  • Cross-section 421 represents the feature after CVD is performed and after annealing to result in an annealed CVD tungsten layer 455. Without being bound by a particular theory, it is believed that annealing at high temperature after deposition of tungsten on the substrate results in purification of impurities from the tungsten film. For example, the annealing step may be releasing boron from the tungsten film, resulting in a tungsten film with less atomic boron content and lower resistivity overall.
  • FIG. 5 provides a process flow diagram showing steps for depositing a layer of tungsten including annealing prior to and after bulk tungsten deposition. In method 500, in operation 502, a layer of titanium nitride is deposited on the substrate. Methods of deposition and conditions of deposition may be any of those discussed with respect to FIG. 2. In operation 504, the titanium nitride layer is annealed. Any of the annealing conditions with respect to FIG. 2 may be used here. Next, in operation 506, a bulk tungsten layer is deposited. Conditions and methods of depositing the tungsten layer may be any of those discussed above with respect to FIG. 3. During this operation, an optional nucleation layer may be deposited prior to depositing bulk tungsten. The nucleation layer may also be annealed as discussed with respect to FIG. 2. Lastly, in operation 508, the bulk tungsten layer is annealed. In this operation, conditions may be any of those discussed with respect to FIG. 2, except that a non-nitrogen atmosphere may be used during the anneal. In this method, both a pre-tungsten deposition annealing step and post-tungsten deposition annealing step are implemented. As indicated above, while it may remove some impurities from the tungsten layer, the anneal operation does not change the chemical composition of the tungsten layer. Accordingly, nitrogen-containing or silicon-containing atmospheres may be avoided to prevent formation of a nitride or silicide layer
  • In certain embodiments, transitioning from operation 504 to 506, or 506 to 508, involves moving the substrate from one deposition station to another, which may occur in a multi-station chamber. Each of these operations may be performed in the same or different chamber. If performed in the same chamber, they each may be performed in the same or different stations of the same multi-station chamber or in a single station chamber. Also, the anneal operations may be performed outside of a deposition chamber in a separate chamber that may or may not be in the same vacuum environment that the deposition operation is performed.
  • In alternative embodiments in which a single station is used to perform operations 506 and 508, transitioning from operation 506 to 508 may involve shutting off a flow of tungsten precursor (operationally allowing hydrogen or other reducing gas and/or carrier gas to run), while raising the substrate temperature. Once the substrate temperature is stabilized, the tungsten precursor and other gases, if necessary, are flowed into the reaction chamber for a high temperature deposition.
  • Apparatus
  • Methods of the disclosed embodiments may be carried out in various types of deposition apparatuses available from various vendors. Examples of suitable apparatuses include a Lam Concept 1 Altus, a Concept 2 Altus, a Concept 2 Altus-S, a Concept 3 Altus deposition system, or any of a variety of other commercially available CVD tools. In some cases, processes may be performed on multiple depositions stations sequentially. In some embodiments, the annealing step is performed at a station that is one of two, four, five, or even more deposition stations positioned within a single deposition chamber. In some embodiments, the annealing step is performed at a station on another chamber separate from the deposition chamber used for CVD. In various embodiments, an existing deposition station may be modified to accommodate an annealing step. One or more stations in a chamber may be used to perform CVD, or two or more stations may be used to perform CVD in a parallel processing.
  • FIG. 6 is a block diagram of a processing system suitable for conducting tungsten thin film deposition processes in accordance with disclosed embodiments. System 600 includes a transfer module 603, which provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between various reactor modules. Mounted on the transfer module 603 is a multi-station reactor 609 capable of performing pulsed nucleation layer (PNL) deposition, multi-pulse treatment if desired, CVD, and annealing steps according to the disclosed embodiments. Chamber 609 may include multiple stations 611, 613, 615, and 617 that may sequentially perform these operations. For example, chamber 609 could be configured such that station 611 performs PNL deposition, station 613 performs multi-pulse treatment, station 615 performs CVD, and station 617 performs annealing.
  • Also mounted on the transfer module 603 may be one or more single or multi-station modules 607 capable of performing plasma or chemical (non-plasma) pre-cleans. The module may also be used for various other treatments, e.g., titanium nitride barrier layer deposition or post-liner tungsten nitride treatments. Still further, a module 607 may be an anneal module. The system 600 also includes one or more wafer source modules 601 here wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 619 first removes wafers from the source modules 601 to loadlocks 621. A wafer transfer device (generally a robot arm unit) in the transfer module 603 moves the wafers from loadlocks 621 to and among the modules mounted on the transfer module 603.
  • In certain embodiments, a system controller 650 is employed to control process conditions during deposition. The controller 650 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.
  • The controller 650 may control all of the activities of the deposition apparatus. The system controller 650 executes system control software, including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored on memory devices associated with the control 650 may be employed in some embodiments.
  • Typically there will be a user interface associated with the controller 650. The user interface may include a display screen, graphical software displays of the apparatus and or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
  • System control logic may be configured in any suitable way. In general, the logic can be designed or configured in hardware and/or software. In other words, the instructions for controlling the drive circuitry may be hard coded or provided as software. It may be said that the instructions are provided by “programming.” Such programming is understood to include logic of any form including hard coded logic in digital signal processors, application specific integrated circuits, and other devices which have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general purpose processor. System control software may be coded in any suitable computer readable programming language.
  • The computer program code for controlling the deposition, annealing, and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may hard coded.
  • The controller parameters relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe, and may be entered utilizing the user interface.
  • Signals for monitoring the process may be provided by analog and/or digital input connections of the system controller 650. The signals for controlling the process are output on the analog and digital output connections of the deposition apparatus.
  • The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the deposition processes in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.
  • A substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and/or target. A process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into the chamber prior to deposition in order to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck.
  • Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions.
  • The foregoing describes implementation of disclosed embodiments in a single or multi-chamber semiconductor processing tool.
  • The apparatus and process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically comprises some or all of the following steps, each step provided with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
  • Experimental
  • Experiments were conducted to determine the effect of annealing substrates at various times and temperatures. In these experiments, wafers were processed using nucleation steps, optional treatment steps, CVD steps, and anneal steps. For purposes of these experiments, two sets of conditions were used in various experiments for the nucleation step.
  • Set A refers to the following set of conditions for the nucleation station. Substrate temperature is set at 250° C., and B2H6 and WF6 are sequentially flowed for two cycles. Diversion of B2H6 is set at 1 second with a B2H6 purge time of 1 second and WF6 purge time of 1 second. The flow rate of WF6 is about 180 sccm. The H2 flow of the front of the tool is about 27,000 sccm and the H2 flow of the back of the tool is about 3000 sccm.
  • Set B refers to the following set of conditions for the nucleation station. Substrate temperature is set at 250° C., and B2H6 and WF6 are flowed for two cycles. Diversion of B2H6 is set at 1.5 seconds with a B2H6 purge time of 2 seconds and WF6 purge time of 2 seconds. The flow rate of WF6 is about 220 sccm. The H2 flow of the front of the tool is about 25,000 sccm and the H2 flow of the back of the tool is about 10,000 sccm.
  • The second step for optional treatment involves substrates subject to five cycles of B2H6 pulses flow at a substrate temperature of 325° C. Next, the step for CVD of tungsten may involve H2 and WF6 flow and tungsten deposition at 325° C. Varying conditions of the annealing steps are used in the following experiments.
  • EXPERIMENT 1
  • Resistivity of tungsten films deposited using various anneal times was measured. For purposes of this experiment, Set A conditions were used. A 300 Å titanium nitride substrate was used in this experiment. The substrate was annealed after deposition of tungsten at a temperature of 445° C. using Ar flow. The argon flow rate was about 6000 sccm. Trials were conducted to determine resistivity of both about 60 Å tungsten films and about 90 Å tungsten films. The results are summarized in FIG. 7.
  • The round points indicate resistivity of the films without an annealing step. The square points indicate resistivity of films using a 20-second anneal after deposition of the tungsten. Compared to the points representing no anneal, the resistivity substantially decreased. The triangular points indicate resistivity of films using a 10-minute anneal after deposition of the tungsten. Compared to the points representing no anneal, the resistivity is further decreased. It is noted here that the difference between the 20-second anneal and 10-minute anneal is almost the same as the difference between the 20-second anneal and no anneal, thereby suggesting that a threshold anneal time exists such that at a point in time, further annealing will result in the same resistivity. Nonetheless, as shown in FIG. 7, a post-deposition anneal for as short as 20 seconds can achieve substantially lower resistivity films. It is further believed that post-deposition anneals for as short as 1-5 seconds may also improve resistivity.
  • Experiment 2
  • Experiments were conducted to determine the effect of varying annealing temperatures on substrates. Conditions from Set A as recited above were used for deposition of a tungsten films on a 300 Å titanium nitride barrier layer on a substrate. Tungsten films were between about 86.5 Å and 90 Å in thickness. The substrate was annealed after tungsten deposition using argon flow for 20 seconds at varying temperatures. Data points were determined by measuring resistivity of a substrate before anneal, and measuring resistivity of the same substrate after anneal at a certain temperature. The results of this experiment are shown in FIGS. 8A and 8B.
  • In FIG. 8A, the square shaped points represent the resistivity of the annealed substrates at various temperatures. The diamond shaped points represent the resistivity of each of those annealed substrates prior to the annealing step. For example, at 395° C., the substrate had a resistivity of about 40.8 μΩ-cm before annealing, but after annealing the resistivity lowered to 39.6 μΩ-cm, resulting in a resistivity improvement of about 3.0%. Resistivity improvement, or the trend in decreased resistivity, is shown in FIG. 8B. A subsequent trial was run to compare resistivity drop for a tungsten film annealed at 445° C. for 10 minutes (not shown in figures). The resulting resistivity drop was about 12.0%, substantially higher than the resistivity drop for using a 20-second anneal. According to the results, as anneal temperature increases, the difference in resistivity increases, thereby exhibiting a higher resistivity drop, and a better, lower resistivity tungsten films. The data suggests using a longer anneal time at a higher temperature to achieve the greatest resistivity drop and thus extremely low resistivity tungsten films.
  • Experiment 3
  • A series of experiments were conducted to determine the effect of the timing of annealing on resistivity. In the first experiment, conditions from Set A as recited above were used on 30 Å titanium nitride barrier layer on substrates. Three different variations were tested: (1) “pre-W anneal,” which involved annealing before depositing any tungsten; (2) “pre-W and post-W anneal,” which involved annealing both before and after depositing tungsten; and (3) “post-W anneal,” which involved annealing after depositing tungsten. To compare, trials were conducted for tungsten films without an annealing step. Annealing steps involved annealing at 445° C. for 10 minutes using either Ar (or Ar/H2) flow. The results are shown in FIG. 9.
  • As shown in the figure, substrates deposited without an annealing step had the highest resistivity. For a 75 Å tungsten film, resistivity was about 40 μΩ-cm, as compared to a same thickness tungsten film with a post-W anneal which resulted in a resistivity of about 38 μΩ-cm. Using only a pre-W anneal had a higher resistivity for a film with a tungsten thickness of about 82 Å than when both a pre-W and post-W anneal were used. The data suggests that the optimal conditions for achieving extremely low resistivity tungsten films is to both anneal before and after depositing tungsten on the substrate.
  • In the second experiment, conditions from Set B as recited above were used on 300 Å titanium nitride barrier layers on substrates. Flow rates of H2 in both the front and back of the tool were either 20,000 sccm or 30,000 sccm and 1,000 sccm or 15,000 sccm respectively. After tungsten deposition, substrates were annealed at 445° C. using argon (or Ar/H2) for 10 minutes. Resistivity was measured before and after annealing for each of four substrates, as shown in Table 1 below.
  • TABLE 1
    Resistivity and Post-Tungsten Deposition Annealing
    No Post-W
    Tungsten Anneal Anneal Decrease
    H2 Flow Thickness Resistivity Resistivity Resistivity in
    (sccm) (Å) (μΩ-cm) (μΩ-cm) Difference Resistivity
    30,000/ 96.23 44.95 36.19 8.76 19%
    1000
    30,000/ 96.83 46.23 36.71 9.52 21%
    15,000
    20,000/ 108.48 78.27 52.61 25.66 33%
    1000
    20,000/ 107.84 76.76 52.61 26.16 34%
    15,000
  • The data suggests using a post-tungsten deposition anneal substantially decreases resistivity, regardless of the H2 flow variations, and a higher decrease in resistivity is shown in films with a thicker layer of tungsten. Nonetheless, extremely low resistivity tungsten films were achieved, with a tungsten film having a resistivity as low as 36.19 μΩ-cm.
  • Experiment 4
  • Experiments were conducted to evaluate the atomic nature of the deposited tungsten films. Substrates that were not annealed showed a higher atomic content of boron than substrates that were annealed. Two wafers each with a 300 Å layer of titanium nitride barrier layer were compared. The first wafer was deposited subject to Set B conditions as recited above. A resulting wafer with a 127 Å tungsten layer was evaluated using x-ray photoelectron spectroscopy, which indicated an atomic boron content of 5.107%. The second wafer was deposited subject to Set B conditions as recited above, except with an added anneal step after the nucleation step, and an added anneal step instead of the last CVD deposition such that the low temperature CVD of tungsten deposited the bulk tungsten. The 91 Å tungsten wafer was annealed at 445° C. for 10 minutes using argon flow with a flow rate of about 6000 sccm, or Ar/H2 flow with a flow rate of about 6000 sccm and about 7000 sccm, respectively. X-ray photoelectron spectroscopy was used to evaluate the boron content. Surprisingly, the boron content in the annealed substrate had an atomic content of only 0.555%, indicating a substantial decrease by a factor of 10 in boron content as compared to the wafer that was not annealed. This supports the theory that annealing may be purifying the tungsten layer such that gases such as boron are released to decrease resistivity.
  • Experiments were conducted on substrates with varying thicknesses of titanium nitride. All anneal steps in these experiments involved annealing at 445° C. for 10 minutes with argon flow with a flow rate of about 6000 sccm, or Ar/H2 flow with a flow rate of about 6000 sccm and about 7000 sccm, respectively. A first wafer with a 30 Å layer of titanium nitride barrier layer was subject to the conditions in Set A as recited above including an anneal before and after tungsten deposition. The boron content over etch time was measured and is shown in FIG. 10A and represented by 1001. A second wafer with a 30 Å layer of titanium nitride barrier layer was subject to conditions in Set A as recited above including an anneal after the tungsten deposition. The boron content over etch time was measured and is shown in FIG. 10A and represented by 1002. A third wafer with a 30 Å layer of titanium nitride as a barrier layer was subject to conditions in Set B as recited above, including an anneal after nucleation and an anneal after tungsten bulk deposition. The boron content over etch time was measured and is shown in FIG. 10A and represented by 1003. It is noted that all three wafers exhibited atomic boron content of less than 0.7%, a significantly low amount.
  • A 300 Å titanium nitride barrier layer was deposited on the next wafer. This wafer was subject to conditions in Set B as recited above and did not include an anneal step. Boron content of this no-anneal wafer is represented by the solid, no-anneal line represented in FIG. 10B. Lastly, a 300 Å titanium nitride barrier layer was deposited on a last wafer. This wafer was subjected to conditions in Set B as recited above, including annealing after nucleation and annealing after tungsten bulk deposition. The boron content over etch time was measured and is represented by the dotted line, labeled “with anneal” in FIG. 10B. As shown, the wafer that was annealed had an atomic content of boron less than 1%, which is significantly lower than the boron content in the non-annealed wafer, which was as high as over 5%.
  • Overall, FIGS. 10A and 10B both suggest that boron content may contribute to the resistivity of the deposited tungsten film on the substrate.
  • Experiment 5
  • Experiments were conducted to determine the effect annealing had on uniformity of the deposited layers. FIG. 11 shows an image of deposited a titanium nitride and a tungsten layer without an annealing step. As shown in FIG. 11, an interface layer exists between the titanium nitride layer and tungsten layer.
  • In contrast, FIG. 12 shows an image of a titanium nitride layer and an annealed tungsten layer. In these images, the tungsten was deposited before annealing the substrate at 445° C. for 20 seconds. FIG. 12 shows a substantial decrease in the interface layer and uniformity in the resulting film. This is a surprising result because the layers are smooth and have low resistivity, whereas conventional tungsten films with low resistivity may tend to be less smooth due to the granularity of the film. This phenomenon may provide support for the theory that annealing rearranges grains in the tungsten film, thereby reducing the resistivity.
  • Experiment 6
  • A series of experiments were conducted to determine whether the type of gas used during annealing affected the resulting resistivity of the deposited tungsten on the substrate. In the first experiment, substrates with a 300 Å titanium nitride barrier layer were used. The conditions from Set B as recited above were used, and comparisons were made between wafers that were not annealed, wafers annealed with argon and hydrogen, and wafers annealed with just argon. Annealing steps occurred at 445° C. for 10 minutes after tungsten deposition. Resistivity results are shown in FIG. 13A. The diamond points represent measurements of resistivity for wafers that were not annealed, whereas the square points represent measurements of resistivity for wafers annealed with Ar/H2 and the triangular points represent measurements of resistivity for wafers annealed with only Ar. The points for both the Ar/H2 anneal and Ar anneal are very similar for similar thicknesses of tungsten, thus suggesting that using either Ar/H2 or Ar is suitable for annealing.
  • A similar trend resulted from a second experiment. In the second experiment, substrates with a 300 Å titanium nitride barrier layer were used. The conditions from Set A as recited above were used, and wafers were annealed at 445° C. for 10 minutes after tungsten deposition using Ar only and Ar/H2. For comparison, a substrate deposited using conditions from Set A as recited above was not annealed. The resulting resistivity of each of these wafers is plotted in FIG. 13B. The diamond shaped points represent measurements of resistivity of wafers that were not annealed. Square points represent measurements of resistivity of wafers annealed with Ar/H2 and triangular points represent measurements of resistivity of wafers annealed with only Ar. Similar to FIG. 13A, the resulting resistivity of wafers annealed with Ar and Ar/H2 were very similar for similar thicknesses of tungsten deposited, thereby suggesting that either Ar/H2 or Ar can be used during the annealing process.
  • CONCLUSION
  • Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims (20)

What is claimed is:
1. A method of forming a tungsten film on a substrate in a reaction chamber, the method comprising:
depositing tungsten on the substrate by introducing a vapor phase tungsten-containing precursor and a boron-containing reactant into a chamber housing the substrate to form the tungsten film; and
annealing the tungsten film to thereby lower the resistivity,
wherein the tungsten film is annealed at a chamber pressure of at least about 1 Torr, and
wherein annealing the tungsten film reduces the boron content of the tungsten film by a factor of 10.
2. The method of claim 1, wherein the tungsten film is annealed at a temperature between about 385° C. and about 445° C.
3. The method of claim 1, wherein the tungsten film has a boron content of less than about 1%.
4. The method of claim 1, wherein the tungsten film is annealed for a duration between about 1 second and about 10 minutes.
5. The method of claim 1, wherein the tungsten film is annealed in a non-nitrogen atmosphere.
6. The method of claim 1, wherein annealing the tungsten film does not change the chemical composition of the tungsten layer.
7. The method of claim 1, wherein the tungsten film is annealed in a non-silicon atmosphere.
8. The method of claim 1, wherein annealing the tungsten film lowers the resistivity by between about 5% and about 35%.
9. A method of forming a tungsten film on a substrate in a reaction chamber, the method comprising:
depositing tungsten on the substrate by introducing a vapor phase tungsten-containing precursor and a boron-containing reactant into a chamber housing the substrate to form the tungsten film at a deposition pressure; and
annealing the tungsten film to thereby lower the resistivity,
wherein the tungsten film is annealed at the deposition pressure, and
wherein annealing the tungsten film reduces the boron content of the tungsten film by a factor of 10.
10. The method of claim 9, wherein the tungsten film has a boron content of less than about 1%.
11. The method of claim 9, wherein the tungsten film is annealed in a non-nitrogen atmosphere.
12. The method of claim 9, wherein annealing the tungsten film does not change the chemical composition of the tungsten layer.
13. The method of claim 9, wherein the tungsten film is annealed in a non-silicon atmosphere.
14. The method of claim 9, wherein annealing the tungsten film lowers the resistivity by between about 5% and about 35%.
15. The method of claim 9, wherein the reaction chamber is a multi-station reactor and the depositing the tungsten and the annealing the tungsten film are performed in different stations of the multi-station reactor.
16. The method of claim 9, wherein flow of a tungsten precursor is shut off after depositing the tungsten and prior to annealing the tungsten film.
17. The method of claim 16, wherein the tungsten film is annealed at a temperature between about 385° C. and about 445° C.
18. The method of claim 9, wherein the deposition pressure is between about 1 mTorr and about 760 Torr.
19. The method of claim 18, wherein the deposition pressure is between about 1 Torr and about 100 Torr.
20. The method of claim 9, wherein the tungsten film is annealed for a duration between about 1 second and about 10 minutes.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
CN113862634A (en) 2012-03-27 2021-12-31 诺发系统公司 Tungsten feature fill
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9595466B2 (en) * 2015-03-20 2017-03-14 Applied Materials, Inc. Methods for etching via atomic layer deposition (ALD) cycles
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US9991362B2 (en) * 2016-09-30 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including tungsten gate and manufacturing method thereof
JP7224335B2 (en) 2017-04-10 2023-02-17 ラム リサーチ コーポレーション Low resistance film containing molybdenum
WO2020028587A1 (en) * 2018-07-31 2020-02-06 Lam Research Corporation Multi-layer feature fill
US11821071B2 (en) 2019-03-11 2023-11-21 Lam Research Corporation Precursors for deposition of molybdenum-containing films
US11205589B2 (en) * 2019-10-06 2021-12-21 Applied Materials, Inc. Methods and apparatuses for forming interconnection structures
US11798845B2 (en) 2020-10-28 2023-10-24 Applied Materials, Inc. Methods and apparatus for low resistivity and stress tungsten gap fill
WO2023059381A1 (en) * 2021-10-05 2023-04-13 Applied Materials, Inc. Methods for forming low resistivity tungsten features

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090149022A1 (en) * 2007-12-05 2009-06-11 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film

Family Cites Families (215)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI117944B (en) 1999-10-15 2007-04-30 Asm Int A method for growing transition metal nitride thin films
JPS5629648A (en) 1979-08-16 1981-03-25 Toshiba Tungaloy Co Ltd High hardness sintered body
JPS62216224A (en) 1986-03-17 1987-09-22 Fujitsu Ltd Selectively growing method for tungsten
JPS62260340A (en) 1986-05-06 1987-11-12 Toshiba Corp Manufacture of semiconductor device
US4746375A (en) 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
US4962063A (en) 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
US5250329A (en) 1989-04-06 1993-10-05 Microelectronics And Computer Technology Corporation Method of depositing conductive lines on a dielectric
GB8907898D0 (en) 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
US5028565A (en) 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
EP1069208A3 (en) 1990-01-08 2003-05-21 Lsi Logic Corporation Method of diffusing gas into a CVD chamber and gas diffusing means
KR100209856B1 (en) 1990-08-31 1999-07-15 가나이 쓰도무 Method of manufacturing semiconductor device
US5250467A (en) 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
US5308655A (en) 1991-08-16 1994-05-03 Materials Research Corporation Processing for forming low resistivity titanium nitride films
US5567583A (en) 1991-12-16 1996-10-22 Biotronics Corporation Methods for reducing non-specific priming in DNA detection
US5370739A (en) 1992-06-15 1994-12-06 Materials Research Corporation Rotating susceptor semiconductor wafer processing cluster tool module useful for tungsten CVD
US5326723A (en) 1992-09-09 1994-07-05 Intel Corporation Method for improving stability of tungsten chemical vapor deposition
KR950012738B1 (en) 1992-12-10 1995-10-20 현대전자산업주식회사 Method of making a tungsten contact plug supply to semiconductor device
KR970009867B1 (en) 1993-12-17 1997-06-18 현대전자산업 주식회사 Forming method of tungsten silicide in the semiconductor device
DE69518710T2 (en) 1994-09-27 2001-05-23 Applied Materials Inc Process for treating a substrate in a vacuum treatment chamber
JPH08115984A (en) 1994-10-17 1996-05-07 Hitachi Ltd Semiconductor device and its manufacture
US6001729A (en) 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JP2737764B2 (en) 1995-03-03 1998-04-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
JPH0927596A (en) 1995-07-11 1997-01-28 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5863819A (en) 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique
US6017818A (en) 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US5833817A (en) 1996-04-22 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving conformity and contact bottom coverage of sputtered titanium nitride barrier layers
US5633200A (en) * 1996-05-24 1997-05-27 Micron Technology, Inc. Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer
US5963833A (en) 1996-07-03 1999-10-05 Micron Technology, Inc. Method for cleaning semiconductor wafers and
US5916634A (en) 1996-10-01 1999-06-29 Sandia Corporation Chemical vapor deposition of W-Si-N and W-B-N
KR100214852B1 (en) 1996-11-02 1999-08-02 김영환 Forming method for metal wiring in semiconductor device
US6310300B1 (en) 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
KR100255516B1 (en) 1996-11-28 2000-05-01 김영환 A metal wire of semiconductor device and forming method thereof
US6297152B1 (en) 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
JP3090074B2 (en) 1997-01-20 2000-09-18 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5804249A (en) 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US6156382A (en) 1997-05-16 2000-12-05 Applied Materials, Inc. Chemical vapor deposition process for depositing tungsten
US6037248A (en) 1997-06-13 2000-03-14 Micron Technology, Inc. Method of fabricating integrated circuit wiring with low RC time delay
US6287965B1 (en) 1997-07-28 2001-09-11 Samsung Electronics Co, Ltd. Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
US5956609A (en) 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5795824A (en) 1997-08-28 1998-08-18 Novellus Systems, Inc. Method for nucleation of CVD tungsten films
US5913145A (en) 1997-08-28 1999-06-15 Texas Instruments Incorporated Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures
US5926720A (en) 1997-09-08 1999-07-20 Lsi Logic Corporation Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6099904A (en) 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
JPH11260759A (en) 1998-03-12 1999-09-24 Fujitsu Ltd Manufacture of semiconductor device
US6452276B1 (en) 1998-04-30 2002-09-17 International Business Machines Corporation Ultra thin, single phase, diffusion barrier for metal conductors
US6066366A (en) 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6143082A (en) 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
KR100273767B1 (en) 1998-10-28 2001-01-15 윤종용 Tungsten film manufacturing method of semiconductor device and semiconductor device manufactured accordingly
US6037263A (en) 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6331483B1 (en) 1998-12-18 2001-12-18 Tokyo Electron Limited Method of film-forming of tungsten
KR100296126B1 (en) * 1998-12-22 2001-08-07 박종섭 Gate electrode formation method of highly integrated memory device
US20010014533A1 (en) 1999-01-08 2001-08-16 Shih-Wei Sun Method of fabricating salicide
JP3206578B2 (en) 1999-01-11 2001-09-10 日本電気株式会社 Method of manufacturing semiconductor device having multilayer wiring structure
JP4570704B2 (en) 1999-02-17 2010-10-27 株式会社アルバック Barrier film manufacturing method
US6306211B1 (en) 1999-03-23 2001-10-23 Matsushita Electric Industrial Co., Ltd. Method for growing semiconductor film and method for fabricating semiconductor device
US6245654B1 (en) 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6294468B1 (en) 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6720261B1 (en) 1999-06-02 2004-04-13 Agere Systems Inc. Method and system for eliminating extrusions in semiconductor vias
US6174812B1 (en) 1999-06-08 2001-01-16 United Microelectronics Corp. Copper damascene technology for ultra large scale integration circuits
US6355558B1 (en) 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6265312B1 (en) 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US6391785B1 (en) 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6309966B1 (en) 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
US6303480B1 (en) 1999-09-13 2001-10-16 Applied Materials, Inc. Silicon layer to improve plug filling by CVD
US6924226B2 (en) 1999-10-02 2005-08-02 Uri Cohen Methods for making multiple seed layers for metallic interconnects
US6610151B1 (en) 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
EP1221178A1 (en) 1999-10-15 2002-07-10 ASM America, Inc. Method for depositing nanolaminate thin films on sensitive surfaces
KR100330163B1 (en) * 2000-01-06 2002-03-28 윤종용 A Method of Forming Tungsten Contact Plug in A Semiconductor Devices
US6277744B1 (en) 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US6777331B2 (en) 2000-03-07 2004-08-17 Simplus Systems Corporation Multilayered copper structure for improving adhesion property
US6429126B1 (en) * 2000-03-29 2002-08-06 Applied Materials, Inc. Reduced fluorine contamination for tungsten CVD
JP5184731B2 (en) 2000-05-18 2013-04-17 コーニング インコーポレイテッド FLEXIBLE ELECTRODE / ELECTROLYTE STRUCTURE FOR SOLID OXIDE FUEL CELL, FUEL CELL DEVICE, AND METHOD FOR PRODUCING THE SAME
JP3651360B2 (en) 2000-05-19 2005-05-25 株式会社村田製作所 Method for forming electrode film
US7253076B1 (en) 2000-06-08 2007-08-07 Micron Technologies, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6491978B1 (en) 2000-07-10 2002-12-10 Applied Materials, Inc. Deposition of CVD layers for copper metallization using novel metal organic chemical vapor deposition (MOCVD) precursors
US6218301B1 (en) 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
US6740591B1 (en) 2000-11-16 2004-05-25 Intel Corporation Slurry and method for chemical mechanical polishing of copper
AU2002214283A1 (en) 2000-11-17 2002-05-27 Tokyo Electron Limited Method of forming metal wiring and semiconductor manufacturing apparatus for forming metal wiring
KR100375230B1 (en) 2000-12-20 2003-03-08 삼성전자주식회사 Method for forming an interconnection of semiconductor device having a smooth surface
US6908848B2 (en) 2000-12-20 2005-06-21 Samsung Electronics, Co., Ltd. Method for forming an electrical interconnection providing improved surface morphology of tungsten
KR100399417B1 (en) 2001-01-08 2003-09-26 삼성전자주식회사 A method for preparing of integrated circuit of semiconductor
US20020117399A1 (en) 2001-02-23 2002-08-29 Applied Materials, Inc. Atomically thin highly resistive barrier layer in a copper via
KR20020072996A (en) 2001-03-14 2002-09-19 주성엔지니어링(주) Method for forming a metal plug
US20020168840A1 (en) 2001-05-11 2002-11-14 Applied Materials, Inc. Deposition of tungsten silicide films
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7589017B2 (en) 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7141494B2 (en) 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7005372B2 (en) 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US7262125B2 (en) 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7955972B2 (en) 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US6635965B1 (en) 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US6686278B2 (en) 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
TW581822B (en) 2001-07-16 2004-04-01 Applied Materials Inc Formation of composite tungsten films
WO2003030224A2 (en) 2001-07-25 2003-04-10 Applied Materials, Inc. Barrier formation using novel sputter-deposition method
US20030029715A1 (en) 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
JP4032872B2 (en) 2001-08-14 2008-01-16 東京エレクトロン株式会社 Method for forming tungsten film
JP4595989B2 (en) 2001-08-24 2010-12-08 東京エレクトロン株式会社 Deposition method
US6607976B2 (en) 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
TW589684B (en) 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
JP2003142484A (en) 2001-10-31 2003-05-16 Mitsubishi Electric Corp Method of manufacturing semiconductor device
US6566262B1 (en) 2001-11-01 2003-05-20 Lsi Logic Corporation Method for creating self-aligned alloy capping layers for copper interconnect structures
TWI253478B (en) 2001-11-14 2006-04-21 Mitsubishi Heavy Ind Ltd Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus
US20030091870A1 (en) 2001-11-15 2003-05-15 Siddhartha Bhowmik Method of forming a liner for tungsten plugs
KR20030050652A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method for forming tungsten layer
US20030123216A1 (en) 2001-12-27 2003-07-03 Yoon Hyungsuk A. Deposition of tungsten for the formation of conformal tungsten silicide
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6566250B1 (en) 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
KR100446300B1 (en) 2002-05-30 2004-08-30 삼성전자주식회사 Method for forming metal interconnections of semiconductor device
US20030224217A1 (en) * 2002-05-31 2003-12-04 Applied Materials, Inc. Metal nitride formation
US6905543B1 (en) 2002-06-19 2005-06-14 Novellus Systems, Inc Methods of forming tungsten nucleation layer
TWI287559B (en) 2002-08-22 2007-10-01 Konica Corp Organic-inorganic hybrid film, its manufacturing method, optical film, and polarizing film
US6706625B1 (en) 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6962873B1 (en) 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
AU2003304283B2 (en) 2002-12-23 2009-10-22 Applied Thin Films, Inc. Aluminum phosphate coatings
JP2004235456A (en) 2003-01-30 2004-08-19 Seiko Epson Corp Film depositing system, film depositing process, and process for manufacturing semiconductor device
US7713592B2 (en) 2003-02-04 2010-05-11 Tegal Corporation Nanolayer deposition process
JP3956049B2 (en) 2003-03-07 2007-08-08 東京エレクトロン株式会社 Method for forming tungsten film
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7211508B2 (en) 2003-06-18 2007-05-01 Applied Materials, Inc. Atomic layer deposition of tantalum based barrier materials
JP2005029821A (en) 2003-07-09 2005-02-03 Tokyo Electron Ltd Film-forming method
US7754604B2 (en) 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
JP4606006B2 (en) 2003-09-11 2011-01-05 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7078341B2 (en) 2003-09-30 2006-07-18 Tokyo Electron Limited Method of depositing metal layers from metal-carbonyl precursors
US6924223B2 (en) 2003-09-30 2005-08-02 Tokyo Electron Limited Method of forming a metal layer using an intermittent precursor gas flow process
KR100557626B1 (en) 2003-12-23 2006-03-10 주식회사 하이닉스반도체 Method for Forming Bit-Line of Semiconductor Device
US20050139838A1 (en) 2003-12-26 2005-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR100528030B1 (en) * 2003-12-30 2005-11-15 주식회사 아이피에스 A method of plating a thin film
KR101108304B1 (en) 2004-02-26 2012-01-25 노벨러스 시스템즈, 인코포레이티드 Deposition of tungsten nitride
WO2005101473A1 (en) 2004-04-12 2005-10-27 Ulvac, Inc. Method of forming barrier film and method of forming electrode film
JP5074183B2 (en) 2004-04-21 2012-11-14 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method for manufacturing high-pressure gas discharge lamp, tungsten electrode, high-pressure gas discharge lamp, and lighting unit
US7605469B2 (en) 2004-06-30 2009-10-20 Intel Corporation Atomic layer deposited tantalum containing adhesion layer
US7429402B2 (en) 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US20060145190A1 (en) 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100642750B1 (en) 2005-01-31 2006-11-10 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US7344983B2 (en) 2005-03-18 2008-03-18 International Business Machines Corporation Clustered surface preparation for silicide and metal contacts
US7220671B2 (en) 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
JP4738178B2 (en) 2005-06-17 2011-08-03 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP4945937B2 (en) 2005-07-01 2012-06-06 東京エレクトロン株式会社 Tungsten film forming method, film forming apparatus, and storage medium
JP4864368B2 (en) 2005-07-21 2012-02-01 シャープ株式会社 Vapor deposition method
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7235485B2 (en) 2005-10-14 2007-06-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
US7524765B2 (en) 2005-11-02 2009-04-28 Intel Corporation Direct tailoring of the composition and density of ALD films
US7276796B1 (en) 2006-03-15 2007-10-02 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
JP2007250907A (en) 2006-03-16 2007-09-27 Renesas Technology Corp Semiconductor device and manufacturing method therefor
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
TW200746268A (en) 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
US7557047B2 (en) 2006-06-09 2009-07-07 Micron Technology, Inc. Method of forming a layer of material using an atomic layer deposition process
KR100884339B1 (en) 2006-06-29 2009-02-18 주식회사 하이닉스반도체 Method for forming W film and method for forming W connection line in semiconductor device
KR100705936B1 (en) 2006-06-30 2007-04-13 주식회사 하이닉스반도체 Method for forming bitline of semiconductor device
US7355254B2 (en) 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts
US8153831B2 (en) 2006-09-28 2012-04-10 Praxair Technology, Inc. Organometallic compounds, processes for the preparation thereof and methods of use thereof
KR100894769B1 (en) 2006-09-29 2009-04-24 주식회사 하이닉스반도체 Method of forming a metal wire in a semiconductor device
KR20080036679A (en) 2006-10-24 2008-04-29 삼성전자주식회사 Method of forming a non-volatile memory device
US7675119B2 (en) 2006-12-25 2010-03-09 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
US20080254619A1 (en) 2007-04-14 2008-10-16 Tsang-Jung Lin Method of fabricating a semiconductor device
KR20080101745A (en) 2007-05-15 2008-11-21 어플라이드 머티어리얼스, 인코포레이티드 Atomic layer deposition of tungsten materials
JP2008288289A (en) 2007-05-16 2008-11-27 Oki Electric Ind Co Ltd Field-effect transistor and its manufacturing method
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US7879222B2 (en) 2007-08-27 2011-02-01 Eci Technology, Inc. Detection of additive breakdown products in acid copper plating baths
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
KR101163825B1 (en) 2008-03-28 2012-07-09 도쿄엘렉트론가부시키가이샤 Electrostatic chuck and manufacturing method thereof
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US20100072623A1 (en) 2008-09-19 2010-03-25 Advanced Micro Devices, Inc. Semiconductor device with improved contact plugs, and related fabrication methods
JP2010093116A (en) 2008-10-09 2010-04-22 Panasonic Corp Semiconductor device and method for manufacturing the same
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
WO2010077847A2 (en) 2008-12-31 2010-07-08 Applied Materials, Inc. Method of depositing tungsten film with reduced resistivity and improved surface morphology
DE102009015747B4 (en) 2009-03-31 2013-08-08 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg A method of fabricating transistors having metal gate electrode structures and high-k gate dielectric and an intermediate etch stop layer
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US8039394B2 (en) 2009-06-26 2011-10-18 Seagate Technology Llc Methods of forming layers of alpha-tantalum
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8207062B2 (en) * 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US20120294874A1 (en) 2009-11-19 2012-11-22 Paul Anthony Macary Method for Producing T Cell Receptor-Like Monoclonal Antibodies and Uses Thereof
DE102009055392B4 (en) 2009-12-30 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Semiconductor component and method for producing the semiconductor device
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US9129945B2 (en) 2010-03-24 2015-09-08 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
US8778797B2 (en) 2010-09-27 2014-07-15 Novellus Systems, Inc. Systems and methods for selective tungsten deposition in vias
US20120199887A1 (en) 2011-02-03 2012-08-09 Lana Chan Methods of controlling tungsten film properties
US20120225191A1 (en) 2011-03-01 2012-09-06 Applied Materials, Inc. Apparatus and Process for Atomic Layer Deposition
US8865594B2 (en) 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8546250B2 (en) 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8916435B2 (en) 2011-09-09 2014-12-23 International Business Machines Corporation Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory
WO2013063260A1 (en) 2011-10-28 2013-05-02 Applied Materials, Inc. High temperature tungsten metallization process
SG10201605902RA (en) 2011-12-12 2016-09-29 Novellus Systems Inc Monitoring leveler concentrations in electroplating solutions
KR102100520B1 (en) 2012-03-27 2020-04-14 노벨러스 시스템즈, 인코포레이티드 Tungsten feature fill with nucleation inhibition
CN113862634A (en) 2012-03-27 2021-12-31 诺发系统公司 Tungsten feature fill
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
KR101990051B1 (en) 2012-08-31 2019-10-01 에스케이하이닉스 주식회사 Semiconductor device with fluorine free tungsten barrier layer and method for fabricating the same
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9362163B2 (en) 2013-07-30 2016-06-07 Lam Research Corporation Methods and apparatuses for atomic layer cleaning of contacts and vias

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090149022A1 (en) * 2007-12-05 2009-06-11 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US10529722B2 (en) 2015-02-11 2020-01-07 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US10546751B2 (en) 2015-05-27 2020-01-28 Lam Research Corporation Forming low resistivity fluorine free tungsten film without nucleation
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures

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