JP3206578B2 - Method of manufacturing semiconductor device having multilayer wiring structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure and a method of manufacturing the same, and more particularly, to a semiconductor device having a recess formed in an insulating layer on a semiconductor substrate. After the film processing is performed, a conductor layer is deposited on the processed insulating layer and the concave portion,
A multilayer wiring in which an unnecessary portion of the conductive layer is polished and removed using a chemical mechanical polishing method to form a conductive layer having a flat portion substantially flush with the insulating layer in the recess. The present invention relates to a method for manufacturing a semiconductor device having a structure and a semiconductor device using the method.

[0002]

2. Description of the Related Art In recent years, it has become necessary to three-dimensionally multiply semiconductor devices (for example, LSIs) in order to achieve higher integration and higher performance. It is a desirable method to perform a flattening process for removing irregularities on the laminated surface at an appropriate stage.

As one of the flattening processes, a chemical mechanical polishing (CMP) method has been used. In particular, when a plug or a buried wiring (damascene wiring) is formed by embedding a metal in a through-hole, a contact hole, or a groove-shaped recess (damascene method) for the purpose of realizing a multilayer wiring structure, This chemical mechanical polishing method is a powerful method.

[0004]

However, when the above-described chemical mechanical polishing method is used, a polishing rate is higher in a pattern region having a large number of wirings and plugs in a substrate than in a non-pattern region having a small number of wirings and plugs. In this case, excessive polishing is performed, and as shown in FIG. 5, an erosion that produces a height difference in the substrate occurs. When the erosion occurs, a variation in wiring resistance (plug resistance in the case of a plug) occurs, and a certain quality cannot be maintained.

In a buried interconnect having a large line width, dishing occurs in which the thickness of the interconnect decreases at the center of the interconnect as shown in FIG. 6, causing a problem similar to that of erosion. . Various proposals have been made to solve this problem, for example, Japanese Patent Application Laid-Open No. 8-83780 discloses an example.

In the invention disclosed in Japanese Patent Application Laid-Open No. 8-83780, a silicon oxide film 32 as an insulator is formed on a silicon substrate 31 as shown in FIG. The film 32 is patterned to form a wiring groove 33. Next, on the silicon oxide film 32 including the wiring groove, a titanium film 34 as a lower conductive film for improving adhesion to the silicon oxide film 32 and a titanium nitride film as an intermediate conductive film serving as a barrier layer 35
Are sequentially deposited. Further, a stacked film 30 is formed thereon by depositing a tungsten film 36.

Next, the polishing apparatus 40 shown in FIG.
The laminated substrate 30 shown in FIG. in this case,
The laminated substrate is mounted on a rotatable vacuum chuck holder 41 such that the surface to be polished (upper surface in FIG. 7A) of the laminated substrate faces the polishing pad 43. The polishing pad 43
It is mounted on a rotatable polishing platen 44. From the discharge end of the abrasive supply pipe 45 extended to the vicinity of the polishing pad 43, an abrasive 46 unique to the present invention supplied from an abrasive tank (not shown) is supplied under control.

In this state, when the laminated substrate 30 mounted on the rotating vacuum chuck holder 41 is pressed onto the rotating polishing pad 43, the unevenness of the laminated substrate 30 is reduced in cooperation with the abrasive 46. 7B. Ideally, the polishing is performed flat as shown in FIG. 7B, and an ideal tungsten wiring remains in the groove 33 of the silicon oxide film 32. In this case, abrasive 4
6 polishes, the tungsten film is polished faster than the silicon oxide film 32 acting as a peripheral stopper, and when a dent (dishing) occurs in the central portion of the tungsten wiring to be formed, the components in the polishing agent are removed. A protective film for suppressing chemical polishing is formed on the dent to prevent the dent from progressing, and as a result, a flat and smooth polished surface including the tungsten wiring is formed.

In order to ideally apply a chemical mechanical polishing method to a laminated substrate having an uneven surface as described above without causing erosion or dishing, the components of the abrasive 46 must be complicated. Must be adjusted to
Also, it is not easy to set parameters such as temperature and the number of rotations of the vacuum chuck holder and the polishing pad. This is because the essential factor is that the polishing rate of the tungsten film is too higher than the polishing rate of the silicon oxide film.

In view of the above problems, the present invention uses a chemical mechanical polishing method for realizing a multilayer wiring structure by providing a means for adjusting a polishing rate to a tungsten wiring or a plug itself to be formed. It is an object of the present invention to provide a semiconductor device manufacturing method and a semiconductor device manufactured by the method, which can easily realize ideally flattening the unevenness of the plane of the laminated substrate.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a laminated substrate using a chemical mechanical polishing method by forming a conductor layer such as an embedded wiring or a plug in two steps. The flattening of the flat surface can be easily realized ideally.

That is, according to the method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention, a method is described in which a concave portion is formed in an insulating layer on a semiconductor substrate, and a desired film forming process is performed on the surface of the insulating layer and the concave portion. After that, a conductive layer is deposited on the processed insulating layer and the concave portion, and unnecessary portions of the conductive layer are polished and removed by using a chemical mechanical polishing method, so that the insulating layer and the insulating layer are substantially removed. Forming a conductive layer having a flat portion in the recess in the recess, wherein the depositing step is performed so as to leave a hollow in the recess. A first conductive layer deposited on the insulating layer and the recess
A first conductive layer on the first conductive layer so as to fill the hollow in the concave portion left in the first deposition step and cover the first conductive layer. have a second deposition step of depositing a second conductive layer slower polishing rate than the conductive layer is a tungsten layer
In the first deposition step, the CVD method is used.
Therefore, a film is formed at 450 ° C. or less, and the second deposition step is performed.
In the above, a film is formed at 480 ° C. or higher by a CVD method.
It "(claim 1), is characterized in.

[0013]

[0014]

In the embodiment of the present invention, concave portions (grooves having a concave cross section) 17, 18, and 19 are formed in the insulating layer (silicon oxide film) 12 on the semiconductor substrate 11, and the insulating layer 12 and the After a desired film formation (titanium nitride film) 13 treatment is performed on the surface of the concave portion, the concave portions 17, 18, 19 are formed on the insulating layer 12 and the concave portions 17, 18, 19 covered with the film 13. A first conductive layer (tungsten layer) 14 is deposited so as to leave a hollow inside, and the first conductive layer 14 is filled while filling the hollow in the remaining concave portion.
Is deposited, a second conductive layer (tungsten layer) 15 having a lower polishing rate than the first conductive layer 14 is deposited.

According to such a configuration, when the substrate laminated as described above is polished by the chemical mechanical polishing method, the second conductive layer embedded in the first conductive layer is: A pattern region having a conductor layer composed of the first and second conductor layers is prevented from being polished faster than a non-pattern region having no conductor layer, and the pattern region is polished flush with the non-pattern region. Acts as follows.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings. 1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor device having a multilayer wiring structure according to the present invention.

In this embodiment, as shown in FIG. 1A, first, a silicon oxide film 12 is formed on a semiconductor substrate 11 by a plasma CVD method. Grooves 17, 18, 1 having a concave cross section for forming necessary embedded wiring (damascene wiring) on silicon oxide film 12.
9 (eg, using photolithography and reactive ion etching).

In this embodiment, the groove for the buried wiring is formed by drilling halfway through the thickness of the silicon oxide film 12, but the semiconductor substrate 11 for forming the plug is formed.
May be a contact hole that reaches.

Next, a titanium nitride film 13 is formed by a CVD method so as to cover the upper surface of the silicon oxide film 12 and the grooves 17, 18, and 19 having a concave cross section. This titanium nitride film 13 has a function as an adhesion layer of a tungsten film to be formed later. In the contact hole, a titanium film capable of achieving low resistance by silicidation is formed.

Next, on the titanium nitride film 13, a first tungsten layer 14, which is a sparse ordinary tungsten layer having a high polishing rate, is formed by a CVD method. In this example, the formation of the tungsten layer 14 by the CVD
Performed at 0 ° C. or lower. At the time of this film formation, a groove 1 having a concave cross section is used.
The hollow remains in 7, 18, 19, that is,
It is controlled not to be filled with the tungsten layer 14.

Further, on the first tungsten layer 14, a second tungsten layer 15, which is a dense tungsten layer having a low polishing rate, is provided with at least grooves 17 and 1 having a concave cross section.
Films are formed by a CVD method so as to fill the hollows left in 8, 19. In this example, the formation of the second tungsten layer 15 by the CVD method is performed at 480 ° C. or higher.

Therefore, the titanium nitride film 1 shown in FIG.
3, in particular, grooves 17 having a concave cross section for embedded wiring,
18 and 19, the first and second tungsten layers 1
A laminated substrate 10 having a dense / dense layer having a double structure composed of layers 4 and 15 is formed as shown in FIG.

Therefore, the laminated substrate 1 shown in FIG.
0 is mounted on a vacuum chuck holder of a chemical mechanical polishing apparatus in which a polishing pad makes a rotational movement as shown in FIG. 8 (or a polishing pad may make a linear movement). Polishing is performed. In this example, the rotation speed of the vacuum chuck holder is 35 rpm, the rotation speed of the platen is 50 rpm, and the load 5.
0 psi, backside load 2.5 psi, slurry flow rate 150
cc / min. The polishing was performed under the following conditions.

As a polishing pad, a laminated structure polishing pad of IC series, which is a chemically reactive foam manufactured by Rodale, and a SUBA series, which is a nonwoven fabric type, is used. As an abrasive, abrasive particles are silica particles. using manufactured by Cabot Corporation of SS-W type of slurry to be added hydrogen peroxide water (H ₂ O _2). These are very easy to obtain because they are ready-made. In order to detect the end of polishing, an end point detecting device that detects the end of the polishing based on a change in the torque current of the vacuum chuck holder was used.

FIG. 1B shows the result of the chemical mechanical polishing performed on the laminated substrate 10 shown in FIG. 1A. That is, the erosion as shown in FIG. 5 does not occur, and the upper surface of the buried wiring made of the polished first and second tungsten layers 14 and 15 is flush with the upper surface of the silicon oxide film 12. It is formed so as to be flat and smooth. This is because the first tungsten layer 14
This is because the polishing rate of the chemical mechanical polishing for the dense second tungsten layer 15 embedded in the inside is low. This delay can be easily adjusted to an ideal value by the ratio of the sectional area of the second tungsten layer 15 to the sectional area of the first tungsten layer 14.

FIG. 2 shows a case of a buried wiring having a large line width.
(A) and FIG. 2 (b). Again,
As in the case of FIG. 1, the upper surface of the silicon oxide film 22 on the semiconductor substrate 21 and the wider concave groove 2 formed thereon are formed.
7, a titanium nitride film 23 is formed, and a titanium nitride film 2 is formed.
A sparse first tungsten film 24 and a dense second tungsten film 25 are sequentially formed on 3 to form a laminated substrate 20 as shown in FIG. On the other hand, if the above-described chemical mechanical polishing is performed, a laminated substrate without dishing (FIG. 6) as shown in FIG. 2B is formed.

FIG. 3 is a graph showing the result that the erosion is reduced when the above-described chemical mechanical polishing method is applied. That is, when the wiring width (L) and the distance between wirings (S) are a repetitive pattern having a relationship of L / S = 1.0 μm / 0.24 μm, the erosion is reduced by the conventional method (one-step tungsten CVD). About 1
What was 100 ° has been reduced to about 450 ° by the method of the present invention (two-step tungsten CVD).

FIG. 4 shows that the sheet resistance at each wiring width is reduced by about 15% by the method of the present invention (two-step tungsten CVD) rather than by the conventional method (one-step tungsten CVD). It also shows that the electrical characteristics have been improved.

In the above embodiment, it is described that the recess formed on the silicon oxide film is a buried wiring layer made of tungsten, but the present invention is not limited to this. For example, a plug made of tungsten may be used, or a buried wiring or plug made of another metal other than tungsten, such as Al or Cu, may be used.

The first and second tungsten layers 14,
The first tungsten layer 14 is formed by a CVD method, and the second tungsten layer 15 is formed by a known and uncomplicated CVD method or a sputtering method such as a sputtering method. Obviously, they may be appropriately combined.

[0032]

As described in detail above, according to the method of manufacturing a semiconductor device having a multilayer wiring structure of the present invention, a concave portion is formed in an insulating layer on a semiconductor substrate, and desired surfaces are formed on the insulating layer and the concave portion. After the film forming process is performed, a conductive layer is deposited on the processed insulating layer and the concave portion, and unnecessary portions of the conductive layer are polished and removed by using a chemical mechanical polishing method. In a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conductor layer having a plane portion substantially flush with the insulating layer is formed in the recess, the depositing step may leave a hollow in the recess. Depositing a first conductor layer on the treated insulating layer and the recesses;
A first conductive layer on the first conductive layer so as to fill the hollow in the concave portion left in the first deposition step and cover the first conductive layer. And a second deposition step of depositing a second conductor layer having a lower polishing rate than the first conductor layer when the laminated substrate is polished by the chemical mechanical polishing method. The patterned second conductive layer prevents the pattern region having the conductive layer composed of the first and second conductive layers from being polished faster than the non-pattern region without the conductive layer, and Acts so as to be polished flush with the non-patterned region, which has the effect that erosion and dishing do not occur.

Further, if a semiconductor device is produced by using such a method, there is an effect that a multilayer wiring structure with stable quality can be easily implemented.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views for explaining a method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention, and FIG. (B) shows a state after the chemical mechanical polishing method is performed.

FIGS. 2A and 2B are cross-sectional views illustrating a case where the present invention is applied to an embedded wiring having a large line width.

FIG. 3 is a graph showing the degree of erosion improvement as a result of implementing the present invention.

FIG. 4 is a graph showing the degree of improvement in sheet resistance as a result of implementing the present invention.

FIG. 5 is a cross-sectional view for explaining erosion that occurs when a conventional semiconductor device manufacturing method is used.

FIG. 6 is a cross-sectional view for explaining dishing that occurs in a conventional semiconductor device manufacturing method.

FIGS. 7A and 7B are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

FIG. 8 is a structural view showing an example of a chemical mechanical polishing apparatus.

[Explanation of symbols]

 10, 20 Laminated substrate 11, 21 Semiconductor substrate 12, 22 Silicon oxide film 13, 23 Titanium nitride film 14, 24 First tungsten film 15, 25 Second tungsten film 17, 18, 19, 27 Groove with concave cross section

Claims (1)

(57) [Claims] 1. A concave portion is formed in an insulating layer on a semiconductor substrate, and after a desired film forming process is performed on the surface of the insulating layer and the concave portion, a conductor layer is formed on the processed insulating layer and the concave portion. Is deposited, and unnecessary portions of the conductor layer are polished and removed by using a chemical mechanical polishing method, so that a conductor layer having a plane portion substantially flush with the insulating layer is placed in the recess. In the method for manufacturing a semiconductor device having a multilayer wiring structure to be formed, in the depositing step, a first conductor layer is deposited on the processed insulating layer and the recess so as to leave a hollow in the recess. A first deposition step, and a first conductive layer formed on the first conductive layer so as to fill a hollow in the concave portion left in the first deposition step and cover the first conductive layer. Second polishing rate lower than body layer
Have a second deposition step of the conductive layer deposition, the conductive layer is a tungsten layer, the first sedimentary
In the stacking step, the temperature is 450 ° C or less by the CVD method.
In the second deposition step, CVD is performed.
A method for manufacturing a semiconductor device having a multilayer wiring structure, characterized in that a film is formed at 480 ° C. or higher by a method.