KR100255516B1 - A metal wire of semiconductor device and forming method thereof - Google Patents
A metal wire of semiconductor device and forming method thereof Download PDFInfo
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- KR100255516B1 KR100255516B1 KR1019960059024A KR19960059024A KR100255516B1 KR 100255516 B1 KR100255516 B1 KR 100255516B1 KR 1019960059024 A KR1019960059024 A KR 1019960059024A KR 19960059024 A KR19960059024 A KR 19960059024A KR 100255516 B1 KR100255516 B1 KR 100255516B1
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- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 26
- 239000002184 metal Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 44
- 239000010937 tungsten Substances 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 3
- 239000010410 layer Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 230000003667 anti-reflective effect Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 11
- 229910000838 Al alloy Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 공정중 캐패시터 형성 이후의 공정으로 금속배선을 사용하여 인터-커넥션(Inter-Connection)을 형성하는 DLM(Double Layer Metalization) 공정에 관한 것으로, 특히 단차 피복선(Step Coverage)의 특성이 우수한 텅스텐을 사용한 반도체 장치의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DLM (Double Layer Metalization) process in which an interconnection is formed using metal wiring as a process after capacitor formation in a semiconductor device manufacturing process. Particularly, the characteristics of step coverage A metal wiring forming method of a semiconductor device using this excellent tungsten.
일반적으로, DLM(Double Layer Metalization) 공정은 디램(DRAM) 소자의 기초가 되는 트랜지스터와 캐패시터가 형성된 이후의 공정으로 정보 전달의 원활화(HIGH SPEED)와 소자 크기의 감소를 위한 금속 배선을 정의하는 공정으로 종래에는 알루미늄 합금을 사용하였다.In general, the DLM (Double Layer Metalization) process is a process after transistors and capacitors, which are the basis of DRAM devices, are formed to define metal wires for high speed and device size reduction. Conventionally, aluminum alloys were used.
그러나, 상기와 같은 알루미늄 합금을 사용하여 DLM 공정을 진행하게 될 경우 소자의 고집적화 추세에 따라 콘택홀 사이즈(Contact Hoal Size)가 감소하고 에스펙트 비(Aspect Ratio)가 증가함에 따라 상기와 같은 고집적 소자에서는 단차 피복선(Step Coverage)의 특성이 나쁘게 되어 이후의 금속배선 형성 공정시 콘택홀(Contact Hoal)에서의 단락 현상이 발생되어 소자의 신뢰성이 저하되는 등의 문제점이 있었다.However, when the DLM process is performed using the aluminum alloy as described above, the contact hole size decreases and the aspect ratio increases according to the trend of higher integration of the device. In the case of step coverage, the characteristics of step coverage become poor, and a short circuit phenomenon occurs in a contact hole during a subsequent metal wiring formation process, resulting in deterioration of reliability of the device.
따라서, 상기와 같은 단차 피복선에 의한 단락 현상을 방지하기 위해 종래의 알루미늄 합금 대신 SiH4, WF6, H2, 및 Ar 가스를 소스로하는 단차 피복선의 특성이 우수한 텅스텐을 사용하여 금속배선 형성 공정을 진행하였다.Therefore, in order to prevent the short circuit caused by the stepped line as described above, a metal wiring forming process using tungsten having excellent characteristics of the stepped line using SiH 4 , WF 6 , H 2 , and Ar gas instead of the conventional aluminum alloy is used. Proceeded.
그러나, 텅스텐의 경우 단차 피복선의 특성은 우수하나, 상기 알루미늄 합금에 비해 약 6μΩ·㎝ 내지 12μΩ·㎝ 정도로 자체 비저항이 높아 반응 주기 지연 시간(Response Cycle Delay Time)이 증가되어 소자의 동작속도가 저하되었다.However, in case of tungsten, the step coverage line has excellent characteristics, but its specific resistance is about 6μΩ · cm to 12μΩ · ㎝ compared to the aluminum alloy, so the response cycle delay time is increased, thereby reducing the operation speed of the device. It became.
또한, 상기와 같이 텅스텐의 비저항이 알루미늄 합금에 비해 약 6배 내지 7배 정도 높기 때문에 상기 텅스텐은 금속 배선이 아닌 플러그(Plug)용으로 사용하여 종래에는 텅스텐 플러그 형성 후 텅스텐 상부에 알루미늄 합금을 재증착하는 이중 구조의 금속배선을 형성시킬 수 밖에 없어 공정이 복잡해지는 등의 문제점이 있었다.In addition, as described above, since the specific resistance of tungsten is about 6 to 7 times higher than that of aluminum alloy, the tungsten is used for plugs instead of metal wires. There was a problem in that the process is complicated because there is no choice but to form a metal structure of a double structure to be deposited.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 단차 피복선의 특성이 우수한 텅스텐막 자체의 높은 비저항에 의한 반응 주기 지연 시간(Response Cycle Delay Time)의 증가 방지 및 공정 단순화를 위한 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is the metal wiring of the semiconductor device for preventing the increase of the response cycle delay time due to the high specific resistance of the tungsten film itself excellent in the step coverage line and simplify the process The purpose is to provide a formation method.
도1A 내지 도1C는 본 발명의 일실시예에 따른 반도체 장치의 금속배선 형성 공정 단면도,1A to 1C are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention;
도1B-1은 화학 기상 증착 장비의 모식도(Chemical Vapor Deposition Chamber Schematic),Figure 1B-1 is a schematic diagram of the chemical vapor deposition equipment (Chemical Vapor Deposition Chamber Schematic),
도1B-2는 본 발명의 일실시예에 따른 텅스텐 형성 공정 진행도.1B-2 is a flowchart of a tungsten formation process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film
13 : 소오스/드레인 영역 14 : Ti/TiN막13 source / drain region 14 Ti / TiN film
15a,15b : 텅스텐막 16 : TiN막15a, 15b: tungsten film 16: TiN film
21 : 피데스틀 22 : 웨이퍼21: pedestal 22: wafer
23 : 가스 분사기23: gas injector
31 : 로드 락 챔버 32 : 버퍼 챔버31: load lock chamber 32: buffer chamber
33 : 제1 증착 챔버 34 : 제2 증착 챔버33: first deposition chamber 34: second deposition chamber
상기 목적을 달성하기 위하여 본 발명은 반도체 기판상의 층간 절연막을 관통하여 소정부위의 반도체 기판에 콘택되는 반도체 장치의 금속배선 형성방법에 있어서, 반도체 기판상의 층간 절연막을 선택식각하여 소정 부위의 반도체 기판이 노출되는 콘택홀을 형성하는 단계; 전체구조 상부에 접합층을 형성하는 단계; 적어도 보론과 포스포러스를 포함하는 가스가 공급되는 제1 증착 챔버내에서 소정두께의 텅스텐막을 저온 증착하는 단계; 및 적어도 보론과 포스포러스를 포함하는 가스가 공급되는 제2 증착 챔버내에서 잔류두께의 텅스텐막을 고온 증착하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a metal wiring of a semiconductor device that penetrates an interlayer insulating film on a semiconductor substrate and contacts a semiconductor substrate at a predetermined portion, wherein the semiconductor substrate at a predetermined portion is selectively etched by etching the interlayer insulating film on the semiconductor substrate. Forming an exposed contact hole; Forming a bonding layer on the entire structure; Low temperature deposition of a tungsten film of a predetermined thickness in a first deposition chamber to which a gas including at least boron and phosphorus is supplied; And depositing a tungsten film having a residual thickness at a high temperature in a second deposition chamber to which a gas including at least boron and phosphorus is supplied.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도1A 내지 도1C는 본 발명의 일실시예에 따른 반도체 장치의 금속 배선 형성 공정 단면도이다.1A to 1C are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
먼저, 도1A는 소정의 하부층이 형성된 반도체 기판(11) 상부의 층간절연막(12)을 선택식각하여 반도체 기판(11)상의 소오스/드레인 영역(13)이 노출되는 콘택홀을 형성한 후, 전체구조 상부에 장벽금속막으로 Ti/TiN막(14)을 형성한 다음, 상기 Ti/TiN막(14)에 대해 반응로(Furnace)의 온도를 고온으로하여 열처리하거나 열처리를 위한 챔버(Chamber)내에서 급속 열처리(Rapid Thermal Processing; 이하 RTP라 칭함)한 것을 도시한 것이다.First, FIG. 1A selectively etches the interlayer insulating film 12 over the semiconductor substrate 11 having a predetermined lower layer to form contact holes for exposing the source / drain regions 13 on the semiconductor substrate 11. A Ti / TiN film 14 is formed on the structure as a barrier metal film, and then heat-treated at a high temperature of the furnace with respect to the Ti / TiN film 14, or in a chamber for heat treatment. Rapid thermal processing (hereinafter referred to as RTP) is shown.
이어서, 도1B는 도1B-1의 화학 기상 증착 장비를 사용하여 도1B-2에 도시된 바와 같은 일련의 공정 진행도에 따라 전체구조 상부에 SiH4, WF6, H2, 및 Ar 가스에 B2H6가스와 PH3가스를 첨가하여 텅스텐을 증착한 것을 도시한 것으로, 먼저 콘택 필링(Contact Filling) 특성 개선을 목적으로 약 450℃ 이하의 저온에서 소정 두께의 텅스텐(15a)을 증착한 다음, 텅스텐의 비저항 및 스트레스 감소를 목적으로 약 450℃ 이상의 고온에서 나머지 텅스텐(15b)을 증착한 것을 도시한 것이다.1B is then used to deposit SiH 4 , WF 6 , H 2 , and Ar gas on top of the entire structure according to a series of process progressions as shown in FIG. 1B-2 using the chemical vapor deposition equipment of FIGS. 1B-1. Figure 2 shows the deposition of tungsten by the addition of B 2 H 6 gas and PH 3 gas, first to deposit a tungsten (15a) of a predetermined thickness at a low temperature of about 450 ℃ or less for the purpose of improving contact filling characteristics Next, it shows the deposition of the remaining tungsten (15b) at a high temperature of about 450 ℃ or more for the purpose of reducing the specific resistance and stress of tungsten.
이때, 상기 B2H6가스와 PH3가스에 의해 보론(Boron)이나 포스포러스(Phosphorus)가 텅스텐막내에 고르게 분포할 수 있게 되어 텅스텐의 비저항을 약 1/2 정도 즉 , 약 6μΩ·㎝ 정도로 낮출 수 있어 반응 주기 지연 시간(Response Cycle Delay Time)을 감소로 인한 소자의 고속 동작을 기대할 수 있다.At this time, the boron or phosphorus can be evenly distributed in the tungsten film by the B 2 H 6 gas and the PH 3 gas, so that the specific resistance of tungsten is about 1/2, that is, about 6 μΩ · cm It can be lowered, so the device can be expected to operate at higher speeds by reducing the response cycle delay time.
이하, 도1B-1 및 도1B-2를 통하여 상기 도1B를 상술한다.Hereinafter, FIG. 1B will be described in detail with reference to FIGS. 1B-1 and 1B-2.
도1B-1는 화학 기상 증착 장비의 모식도를 도1B-2는 본 발명의 일실시예에 따른 텅스텐 형성 공정 진행도를 각각 도시한 것으로, 먼저, 도1B-1에 도시된 바와 같이 일정한 온도가 가해진 피데스틀(Heated Pedestal)(21)위에 도1A 까지의 공정이 진행된 웨이퍼(22)를 올려놓고 반응시키고자하는 가스들이 혼합하여 웨이퍼(22) 상에 분사하는 가스 분사기(WATER-COOLED SHOWERHEAD)(23)를 통해 각각의 반응 가스 즉, SiH4, WF6, H2및 Ar 가스에 B2H6가스와 PH3가스를 첨가하여 공급하여 웨이퍼(23)상에 텅스텐을 증착하되, 도1B-2의 본 발명의 일실시예에 따른 텅스텐 형성 공정 진행도에 도시된 바와 같이 상기 텅스텐 증착을 위한 웨이퍼를 로드 락(Load Lock) 챔버(Chamber)(31)에 장입시킨 후, 버퍼 챔버(Buffer Chamber)(32)를 통해 제1 증착 챔버(33)에서 약 450℃ 이하의 낮은 온도 분위기에서 소정 두께의 텅스텐을 증착한 다음, 웨이퍼는 다시 버퍼 챔버(32)를 통해 제2 증착 챔버(34)로 이동되어 약 450℃ 이상의 높은 온도 분위기에서 나머지 두께의 텅스텐이 증착된다. 이어서 텅스텐 증착 공정이 완료된 웨이퍼는 다시 버퍼 챔버(32)를 통해 처음 위치인 로드 락(Load Lock) 챔버(Chamber)(31)에 위치하게 된다.Figure 1B-1 is a schematic diagram of the chemical vapor deposition equipment Figure 1B-2 shows a progress of the tungsten formation process according to an embodiment of the present invention, respectively, first, as shown in Figure 1B-1 A gas injector (WATER-COOLED SHOWERHEAD) is placed on the applied pedestal 21, and the gases 22 to be reacted are placed on the wafer 22, and sprayed onto the wafer 22. 23) through the addition of B 2 H 6 gas and PH 3 gas to each reaction gas, that is, SiH 4 , WF 6 , H 2 and Ar gas through the deposition of tungsten on the wafer 23, Figure 1B- After loading the wafer for tungsten deposition into a load lock chamber 31 as shown in the tungsten formation process progress diagram according to an embodiment of the present invention, a buffer chamber 32 to a low temperature atmosphere of about 450 ° C. or less in the first deposition chamber 33. Depositing a tungsten having a predetermined thickness, and then, the wafer is moved to a second deposition chamber 34 via buffer chamber 32 again, the thickness of the remaining tungsten at least about 450 ℃ high temperature atmosphere is deposited. Subsequently, the wafer in which the tungsten deposition process is completed is placed in the load lock chamber 31, which is the initial position through the buffer chamber 32.
마지막으로, 도1C는 전체구조 상부에 이후의 금속배선 형성을 위한 포토리쏘그라피 공정시 발생하는 난반사를 방지하기 위한 비반사층으로 TiN막(16)을 형성한 다음, 금속배선 형성용 마스크를 사용한 식각 공정에 의해 금속배선을 형성한 것을 도시한 것이다.Finally, FIG. 1C shows the TiN film 16 as a non-reflective layer for preventing diffuse reflection generated during the subsequent photolithography process for forming metal wiring on the entire structure, followed by etching using a metal wiring forming mask. It shows the metal wiring formed by the process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은 단차 피복선의 특성은 우수하나 자체 비저항이 높은 관계로 금속배선의 재료로 사용되지 못하고, 플러그용으로 사용되던 텅스텐막을 텅스텐 형성용 소스에 보론과 포스포러스를 함유하는 가스를 더 첨가하여 저온과 고온의 두 차례에 걸쳐 증착함으로써, 상기 보론과 포스포러스를 포함하는 가스에 의해 텅스텐막내에 보론과 포스포러스가 고르게 분포할 수 있게 되어 텅스텐의 비저항을 약 1/2 정도 즉 , 약 6μΩ·㎝ 정도로 낮출 수 있고, 저온과 고온의 두 차례에 걸친 증착 공정에 의해 콘택의 필링(Contact Filling) 특성을 개선하고, 막의 비저항 및 스트레스를 감소시킬 수 있어 반응 주기 지연 시간(Response Cycle Delay Time)을 감소로 인한 소자의 고속 동작을 기대할 수 있다.The present invention made as described above is excellent in the characteristics of the step coverage line, but because of its high specific resistance, it cannot be used as a material for metal wiring, and a gas containing boron and phosphorus in the tungsten forming source is used for the tungsten film used for the plug. By further adding and depositing two times of low temperature and high temperature, the boron and phosphorus can be evenly distributed in the tungsten film by the gas containing boron and phosphorus, so that the specific resistance of tungsten is about 1/2, that is, It can be reduced to about 6μΩ · ㎝, and the reaction cycle delay time can be improved by improving the contact filling characteristics of the contact through the two deposition processes of low temperature and high temperature, and reducing the resistivity and stress of the film. Fast operation of the device can be expected due to the reduction of time.
또한, 단차 피복선 특성이 우수한 텅스텐을 사용하여 금속배선을 형성함으로써, 종래의 단차 피복선 개선을 위한 텅스텐 플러그(Plug) 공정 및 알루미늄 합금 형성 공정 등의 이중 구조가 아닌 단일 구조의 금속배선을 형성할 수 있어 공정 단순화로 인한 제조 단가를 낮출 수 있다.In addition, by forming a metal wiring using tungsten having excellent step coverage characteristics, it is possible to form a metal structure of a single structure rather than a dual structure such as a tungsten plug process and an aluminum alloy forming process for improving a conventional step coverage line. The manufacturing cost can be lowered due to the process simplification.
Claims (9)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960059024A KR100255516B1 (en) | 1996-11-28 | 1996-11-28 | A metal wire of semiconductor device and forming method thereof |
| JP9303074A JPH10163132A (en) | 1996-11-28 | 1997-11-05 | Metal wiring of semiconductor device and its formation |
| CN97122986A CN1096117C (en) | 1996-11-28 | 1997-11-28 | Semiconductor device and method for forming metal interconnection in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960059024A KR100255516B1 (en) | 1996-11-28 | 1996-11-28 | A metal wire of semiconductor device and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980039906A KR19980039906A (en) | 1998-08-17 |
| KR100255516B1 true KR100255516B1 (en) | 2000-05-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960059024A KR100255516B1 (en) | 1996-11-28 | 1996-11-28 | A metal wire of semiconductor device and forming method thereof |
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| Country | Link |
|---|---|
| JP (1) | JPH10163132A (en) |
| KR (1) | KR100255516B1 (en) |
| CN (1) | CN1096117C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7504333B2 (en) | 2006-06-30 | 2009-03-17 | Hynix Semiconductor Inc. | Method of forming bit line of semiconductor device |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298648B1 (en) * | 1998-12-05 | 2002-06-20 | 황 철 주 | Method for forming wiring thin film for semiconductor device |
| US9076843B2 (en) | 2001-05-22 | 2015-07-07 | Novellus Systems, Inc. | Method for producing ultra-thin tungsten layers with improved step coverage |
| JP2003332058A (en) | 2002-03-05 | 2003-11-21 | Sanyo Electric Co Ltd | Electroluminescence panel and its manufacturing method |
| JP2003258094A (en) * | 2002-03-05 | 2003-09-12 | Sanyo Electric Co Ltd | Wiring method, method forming the same, and display device |
| CN100517422C (en) | 2002-03-07 | 2009-07-22 | 三洋电机株式会社 | Distributing structure, its manufacturing method and optical equipment |
| JP4387654B2 (en) * | 2002-10-10 | 2009-12-16 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| EP1728257A1 (en) * | 2004-01-30 | 2006-12-06 | Greenvalley R & D Innovations Limited | A method of altering the resistivity of a metal wire |
| US9159571B2 (en) | 2009-04-16 | 2015-10-13 | Lam Research Corporation | Tungsten deposition process using germanium-containing reducing agent |
| US20100267230A1 (en) | 2009-04-16 | 2010-10-21 | Anand Chandrashekar | Method for forming tungsten contacts and interconnects with small critical dimensions |
| US10256142B2 (en) | 2009-08-04 | 2019-04-09 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| WO2013148880A1 (en) | 2012-03-27 | 2013-10-03 | Novellus Systems, Inc. | Tungsten feature fill |
| CN103811411B (en) * | 2012-11-13 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The manufacture method of through hole |
| US9589808B2 (en) | 2013-12-19 | 2017-03-07 | Lam Research Corporation | Method for depositing extremely low resistivity tungsten |
| US9953984B2 (en) | 2015-02-11 | 2018-04-24 | Lam Research Corporation | Tungsten for wordline applications |
| US9978605B2 (en) | 2015-05-27 | 2018-05-22 | Lam Research Corporation | Method of forming low resistivity fluorine free tungsten film without nucleation |
| US9754824B2 (en) | 2015-05-27 | 2017-09-05 | Lam Research Corporation | Tungsten films having low fluorine content |
| US9613818B2 (en) | 2015-05-27 | 2017-04-04 | Lam Research Corporation | Deposition of low fluorine tungsten by sequential CVD process |
| CN111095488A (en) | 2017-08-14 | 2020-05-01 | 朗姆研究公司 | Metal filling process for three-dimensional vertical NAND word lines |
| CN107611018A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of method and crystal circle structure for improving wafer stress |
| JP2021523292A (en) | 2018-05-03 | 2021-09-02 | ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ | How to deposit tungsten and other metals in a 3D NAND structure |
| JP2022513479A (en) | 2018-12-14 | 2022-02-08 | ラム リサーチ コーポレーション | Atomic layer deposition on 3D NAND structure |
| CN113710830A (en) | 2019-04-11 | 2021-11-26 | 朗姆研究公司 | High step coverage tungsten deposition |
| CN113496992A (en) * | 2020-04-01 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4884123A (en) * | 1987-02-19 | 1989-11-28 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
-
1996
- 1996-11-28 KR KR1019960059024A patent/KR100255516B1/en not_active IP Right Cessation
-
1997
- 1997-11-05 JP JP9303074A patent/JPH10163132A/en not_active Withdrawn
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7504333B2 (en) | 2006-06-30 | 2009-03-17 | Hynix Semiconductor Inc. | Method of forming bit line of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980039906A (en) | 1998-08-17 |
| CN1096117C (en) | 2002-12-11 |
| CN1184335A (en) | 1998-06-10 |
| JPH10163132A (en) | 1998-06-19 |
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