KR20000000924A - Method for forming metal wires of semiconductor devices - Google Patents

Method for forming metal wires of semiconductor devices Download PDF

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Publication number
KR20000000924A
KR20000000924A KR1019980020866A KR19980020866A KR20000000924A KR 20000000924 A KR20000000924 A KR 20000000924A KR 1019980020866 A KR1019980020866 A KR 1019980020866A KR 19980020866 A KR19980020866 A KR 19980020866A KR 20000000924 A KR20000000924 A KR 20000000924A
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South Korea
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film
tungsten
forming
titanium
layer
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KR1019980020866A
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Korean (ko)
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KR100525903B1 (en
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손현철
홍상기
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A forming method of metal wires is provided to improve a reliability and an yield by depositing a tungsten nitride layer used as a barrier metal of WF6. CONSTITUTION: The method comprises the steps of forming an interlayer dielectric(2) on a semiconductor substrate(1) having a transistor and forming a contact hole by etching the interlayer dielectric; forming a titanium layer(3) used as a barrier metal on the resultant structure; annealing the titanium layer to form a TiSi2 layer(4) by RTA(rapid thermal annealing); depositing a tungsten nitride layer(5) on the TiSi2 layer by in-situ; and filling a tungsten layer(6) into the contact hole.

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 텅스텐막의 비정상적인 성장을 억제하여 생산성 및 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device capable of suppressing abnormal growth of a tungsten film to improve productivity and yield.

종래의 텅스텐 플러그를 형성하기 위해 다음과 같은 공정을 실시한다.In order to form a conventional tungsten plug, the following process is carried out.

반도체 기판 상부에 형성된 층간 절연막의 선택된 영역을 식각하여 메탈 콘택을 형성한 후 메탈 콘택을 포함한 전체 구조 상부에 장벽층(barrier layer)으로 Ti/TiN막을 증착한다. 열공정을 실시하여 층간 절연막을 구성하는 실리콘 원자와 티타늄 원자를 반응시켜 티타늄 실리사이드(TiSix)를 형성한 후 메탈 콘택이 매립되도록 텅스텐막을 증착한다.After etching the selected region of the interlayer insulating layer formed on the semiconductor substrate to form a metal contact, a Ti / TiN film is deposited as a barrier layer on the entire structure including the metal contact. The thermal process is performed to form a titanium silicide (TiSi x ) by reacting the silicon atoms constituting the interlayer insulating film with the titanium atoms, and then deposit a tungsten film to fill the metal contacts.

WF6를 이용한 CVD 방법으로 텅스텐막을 증착할 경우 TiN막은 WF6의 침투 방지층 및 텅스텐 핵형성(nucleation)층으로 사용된다.When the tungsten film is deposited by the CVD method using WF 6 , the TiN film is used as a penetration prevention layer and a tungsten nucleation layer of the WF 6 .

장벽층으로 Ti/TiN막을 사용할 경우 실리사이드화(silicidation)하기 위한 급속 열처리 공정중 열에 의한 스트레스(thermal stress)로 인하여 TiN막의 결합이 깨져 후속 텅스텐 증착 공정시 텅스텐의 비정상적인 성장(abnormal growth)이 발생하여 메탈 라인(metal line)간의 브리지(bridge)를 유발하게 된다. 이로써 소자의 수율을 감소시키는 결과를 초래한다.In the case of using the Ti / TiN film as a barrier layer, the thermal stress of the TiN film is broken during the rapid heat treatment process for silicidation, causing abnormal growth of tungsten in the subsequent tungsten deposition process. It causes a bridge between metal lines. This results in reducing the yield of the device.

따라서, 본 발명은 TiN막의 결함에 의해 발생되는 후속 텅스텐의 비정상적인 성장으로 인한 소자의 수율 감소를 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can prevent a decrease in the yield of the device due to the abnormal growth of subsequent tungsten caused by a defect in the TiN film.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자를 제조하기 위한 다수의 요소가 구성된 반도체 기판 상부에 층간 절연막을 형성한 후 상기 층간 절연막의 선택된 영역을 식각하여 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함한 전체 구조 상부에 장벽 금속층으로 작용하는 티타늄막을 형성하는 단계와, 급속 열처리 공정에 의해 상기 티타늄막이 티타늄 실리사이드막으로 변형되는 단계와, 상기 티타늄 실리사이드막 상부에 텅스텐 나이트라이드막을 형성하는 단계와, 상기 콘택이 매립되도록 텅스텐막을 증착한 후 패터닝하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole by forming an interlayer insulating film over a semiconductor substrate including a plurality of elements for manufacturing a semiconductor device, and then etching selected regions of the interlayer insulating film. Forming a titanium film acting as a barrier metal layer on the entire structure including holes, transforming the titanium film into a titanium silicide film by a rapid heat treatment process, and forming a tungsten nitride film on the titanium silicide film; And depositing a pattern of tungsten so as to fill the contact.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a metal wiring formation method of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

1 : 반도체 기판 2 : 층간 절연막1 semiconductor substrate 2 interlayer insulating film

3 : 티타늄막 4 : 티타늄 실리사이드막3: titanium film 4: titanium silicide film

5 : 텅스텐 나이트라이드막 6 : 텅스텐막5: tungsten nitride film 6: tungsten film

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

도 1(a)를 참조하면, 반도체 소자를 제조하기 위한 다수의 요소가 구성된 반도체 기판(1) 상부에 층간 절연막(2)을 형성한다. 층간 절연막(2)의 선택된 영역을 식각하여 콘택 홀을 형성한 후 콘택 홀을 포함한 전체 구조 상부에 장벽 금속층으로 작용하는 티타늄막(3)을 형성한다.Referring to FIG. 1A, an interlayer insulating film 2 is formed on a semiconductor substrate 1 including a plurality of elements for manufacturing a semiconductor device. After the selected region of the interlayer insulating film 2 is etched to form a contact hole, a titanium film 3 serving as a barrier metal layer is formed on the entire structure including the contact hole.

도 1(b)를 참조하면, NH3또는 N2분위기에서 급속 열처리 공정을 실시하여 티타늄막(3)의 티타늄 원자와 층간 절연막(2)의 산소 원자를 반응시켜 티타늄 실리사이드막(TiSi2)(4)을 형성한다. 이때, 콘택 기저부의 반도체 기판(1)의 일정 영역까지 티타늄 실리사이드막(4)이 형성된다.Referring to FIG. 1 (b), a rapid heat treatment process is performed in an NH 3 or N 2 atmosphere to react a titanium atom of the titanium film 3 with an oxygen atom of the interlayer insulating film 2 to form a titanium silicide film TiSi 2 ( 4) form. At this time, the titanium silicide film 4 is formed to a predetermined region of the semiconductor substrate 1 of the contact base portion.

도 1(c)를 참조하면, 티타늄 실리사이드막(4) 상부에 텅스텐 나이트라이드막(WNx)(5)을 형성한다. 텅스텐 나이트라이드막(5)은 CVD 텅스텐 증착 장비내에서 증착되며, 후속 텅스텐 증착 공정시 WF6의 침투를 막는 장벽층으로 작용하고, 텅스텐의 핵형성을 원활하게 하는 역할도 한다.Referring to FIG. 1C, a tungsten nitride film WN x 5 is formed on the titanium silicide film 4. The tungsten nitride film 5 is deposited in the CVD tungsten deposition equipment, serves as a barrier layer to prevent the penetration of WF 6 in the subsequent tungsten deposition process, and also serves to facilitate tungsten nucleation.

콘택 홀이 매립되도록 전체 구조 상부에 텅스텐막(6)을 형성한다. 텅스텐막(6)은 텅스텐 나이트라이드막(5) 증착 장비와 동일한 장비에서 CVD 방법으로 증착한다. 이 과정중 텅스텐 나이트라이드막(5)의 질소 소스 가스의 양을 조절하여 계면에서의 조성 변화를 급격하게 하거나 완만하게 형성할 수 있다. 계면에서의 조성 변화를 완만하게 형성할 경우 텅스텐의 핵생성 단계를 실시하지 않아도 되므로 공정을 더욱 단순화시킬 수 있다. 즉, 텅스텐 나이트라이드막을 어느 정도의 두께로 증착한 후 질소 소스 가스를 서서히 줄여 텅스텐 나이트라이드막내의 질소 조성에 변화를 주면 핵형성 단계를 생략할 수 있어 공정을 더욱 단순화시켜 생산성을 향상시킬 수 있다.A tungsten film 6 is formed on the entire structure so that the contact hole is filled. The tungsten film 6 is deposited by the CVD method in the same equipment as the tungsten nitride film 5 deposition equipment. During this process, the amount of nitrogen source gas of the tungsten nitride film 5 can be adjusted to form a sudden or gentle change in composition at the interface. If the composition change at the interface is formed slowly, the nucleation step of tungsten does not have to be performed, thereby simplifying the process. In other words, if the thickness of the tungsten nitride film is deposited to a certain thickness and the nitrogen source gas is gradually reduced to change the nitrogen composition in the tungsten nitride film, the nucleation step can be omitted, thereby simplifying the process and improving productivity. .

이러한 방법으로 진행된 텅스텐막 상부에 후속 배선 공정을 실시한다.Subsequent wiring processes are performed on the tungsten film proceeded in this manner.

상술한 바와 같이 본 발명에 의하면 장벽층으로 텅스텐 나이트라이드막을 형성하므로써 텅스텐막의 비정상적인 성장을 방지하여 텅스텐 플러그 및 텅스텐 배선 공정을 안정화시킬 수 있고, 텅스텐 나이트라이드막을 WF6의 장벽층으로 사용하므로써 256M급 이상의 DRAM 소자에서 안정된 콘택 저항을 얻을 수 있다. 또한 텅스텐막을 증착하기 위한 챔버에서 장벽 금속층을 인-시투로 증착하여 공정을 단순화시킬 수 있고, 계면에 기울기를 가진 텅스텐 나이트라이드막을 사용하므로써 텅스텐 증착시의 공정을 줄일 수 있다. 이로써 생산성을 향상시키고, 소자를 안정화시켜 수율을 향상시킬 수 있다.As described above, according to the present invention, by forming a tungsten nitride film as a barrier layer, it is possible to prevent abnormal growth of the tungsten film, thereby to stabilize the tungsten plug and tungsten wiring process, and by using the tungsten nitride film as a barrier layer of WF 6 to 256M class. In the DRAM device described above, stable contact resistance can be obtained. In addition, the barrier metal layer may be deposited in-situ in the chamber for depositing a tungsten film to simplify the process, and the process of tungsten deposition may be reduced by using a tungsten nitride film having an inclination at the interface. Thereby, productivity can be improved, and a device can be stabilized and a yield can be improved.

Claims (3)

반도체 소자를 제조하기 위한 다수의 요소가 구성된 반도체 기판 상부에 층간 절연막을 형성한 후 상기 층간 절연막의 선택된 영역을 식각하여 콘택 홀을 형성하는 단계와,Forming a contact hole by forming an interlayer insulating film on the semiconductor substrate including a plurality of elements for manufacturing a semiconductor device, and then etching selected regions of the interlayer insulating film; 상기 콘택 홀을 포함한 전체 구조 상부에 장벽 금속층으로 작용하는 티타늄막을 형성하는 단계와,Forming a titanium film serving as a barrier metal layer on the entire structure including the contact hole; 급속 열처리 공정에 의해 상기 티타늄막이 티타늄 실리사이드막으로 변형되는 단계와,Transforming the titanium film into a titanium silicide film by a rapid heat treatment process; 상기 티타늄 실리사이드막 상부에 텅스텐 나이트라이드막을 형성하는 단계와,Forming a tungsten nitride film on the titanium silicide film; 상기 콘택이 매립되도록 텅스텐막을 증착한 후 패터닝하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And depositing a pattern of tungsten so that the contact is buried and patterning the metal wire. 제 1 항에 있어서, 상기 텅스텐막은 상기 텅스텐 나이트라이드막을 증착한 챔버내에서 인-시투로 증착하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the tungsten film is deposited in-situ in a chamber in which the tungsten nitride film is deposited. 제 1 항에 있어서, 상기 텅스텐 나이트라이드막은 질소 소스 가스의 양을 조절하여 계면에서의 조성을 변화시키는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the tungsten nitride film controls the amount of nitrogen source gas to change the composition at the interface.
KR1019980020866A 1998-06-05 1998-06-05 Metal wiring formation method of semiconductor device KR100525903B1 (en)

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KR100525903B1 KR100525903B1 (en) 2006-01-12

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KR100626741B1 (en) * 2000-06-30 2006-09-22 주식회사 하이닉스반도체 Method for forming titanium silicide ohmic contact layer of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626741B1 (en) * 2000-06-30 2006-09-22 주식회사 하이닉스반도체 Method for forming titanium silicide ohmic contact layer of semiconductor device

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