KR100265968B1 - Method for forming via contact of semiconductor device - Google Patents

Method for forming via contact of semiconductor device Download PDF

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KR100265968B1
KR100265968B1 KR1019970044923A KR19970044923A KR100265968B1 KR 100265968 B1 KR100265968 B1 KR 100265968B1 KR 1019970044923 A KR1019970044923 A KR 1019970044923A KR 19970044923 A KR19970044923 A KR 19970044923A KR 100265968 B1 KR100265968 B1 KR 100265968B1
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layer
via contact
barrier material
semiconductor device
material layer
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KR1019970044923A
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Korean (ko)
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KR19990021382A (en
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이종협
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of forming a via contact is to form a penetration prevention layer having a low resistance and preventing penetration of impurities between barrier substance layers upon forming the via contact, thereby lowering a via contact resistance and eliminating a defect in a semiconductor device. CONSTITUTION: A via contact hole is formed in an insulating layer(20) covering a metal layer(10) on a semiconductor device. Titanium is then deposited on the insulating layer to form the first barrier substance layer(30). Amorphous silicon is deposited on the first barrier substance layer and is annealed to convert a part of the amorphous silicon into a penetration prevention layer(60). The second barrier substance layer(40) is deposited on the penetration prevention layer and annealed to convert the remaining amorphous silicon into another penetration prevention layer. Thereafter, a tungsten layer(50) is deposited on the second barrier substance layer to bury the via contact hole.

Description

반도체장치의 비아콘택 형성방법{Method for forming via contact of semiconductor device}Method for forming via contact of semiconductor device

본 발명은 반도체장치의 비아콘택 형성방법에 관한 것으로서, 보다 상세하게는 비아콘택형성시 장벽금속층의 저항이 낮고 불순물의 침투가 적은 새로운 층을 형성하여 비아콘택저항을 낮추어 소자의 결함을 없애도록 한 반도체장치의 비아콘택 형성방법에 관한 것이다.The present invention relates to a method of forming a via contact of a semiconductor device, and more particularly, to form a new layer having low resistance of barrier metal layer and less penetration of impurities during via contact formation, thereby reducing via contact resistance to eliminate device defects. A method of forming a via contact in a semiconductor device.

일반적으로, 반도체장치가 점차적으로 고집적화 됨에 따라 반도체기판상의 배선의 넓이 뿐만 아니라 배선과 배선 사이의 간격도 현저하게 감소하는 추세에 있으며, 더욱이 배선과 배선 사이의 간격이 좁아지는 고집적화가 진행됨에 따라 콘택홀형성에 관한 문제는 크게 대두되고 있으며, 또한 고집적도가 증가함에 따라 다층구조로 형성하면서 금속층의 수가 증가됨에 따라 각 금속층간을 연결하기 위한 공간확보를 위한 비아콘택 형성의 중요도가 점점 증가하고 있다.In general, as semiconductor devices become increasingly integrated, not only the width of wirings on the semiconductor substrate but also the distance between wirings and wirings are remarkably reduced. Moreover, as the integration between wirings and wirings becomes narrower, the contact is increased. The problem of hole formation is increasing, and as the degree of high integration increases, the number of metal layers is increased while forming a multilayer structure, and the importance of via contact formation for securing a space for connecting the metal layers is increasing. .

일반적인 비아콘택을 연결하는 물질로는 CVD 텅스텐이 이용되고 있다.As a material for connecting general via contacts, CVD tungsten is used.

도1 내지 도2는 일반적인 반도체장치의 비아콘택 형성방법에 따라 비아콘택의 형성하는 공정을 나타낸 단면도이다.1 to 2 are cross-sectional views illustrating a process of forming a via contact according to a method of forming a via contact in a general semiconductor device.

도1은 금속층(10) 위에 절연층을 증착한 후 마스크를 통해 비아콘택이 형성될 부위를 식각하여 비아홀을 형성하고 그 위에 제1장벽물질층(30)인 Ti층과 제2장벽물질층(40)인 TiN층을 차례로 증착한 상태를 나타낸 단면도이다.FIG. 1 illustrates a via hole by depositing an insulating layer on the metal layer 10 and then etching a portion of the via contact to be formed through a mask, and forming a first barrier material layer 30, a Ti layer and a second barrier material layer ( It is sectional drawing which showed the state which deposited TiN layer which is 40) in order.

도2는 도1의 결과물에 텅스텐(50)으로 금속층(10)간을 연결하기 위해 CVD법에 의해 텅스텐(50)을 증착한 상태를 나타낸 단면도이다.FIG. 2 is a cross-sectional view illustrating a state in which tungsten 50 is deposited by CVD to connect the metal layers 10 to tungsten 50 through the resultant of FIG. 1.

그러나 도2에서 보는바와 같이 텅스텐(50)을 증착할 때 사용되는 소스가스인 WF6가스로부터 발생된 플루오르(F)가 제1,2장벽물질층(30)(40)인 Ti/TiN층에 침투하여 TiF3(32)라는 부도체를 형성함으로서 비아콘택의 저항을 증가시켜 소자의 결함을 일으키게 된다는 문제점이 있다.However, as shown in FIG. 2, fluorine (F) generated from the WF 6 gas, which is a source gas used for depositing tungsten 50, is deposited on the Ti / TiN layer, which is the first and second barrier material layers 30 and 40. By penetrating and forming an insulator called TiF 3 (32), there is a problem in that the resistance of the via contact is increased to cause a defect of the device.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 금속층과의 연결을 위한 비아콘택의 장벽물질층을 저항이 낮고 불순물의 침투를 방지하는 침투 방지막을 형성하고 열처리로 침투 방지막과 장벽 물질층간의 접촉성을 향상시킴으로써 비아콘택저항을 낮출 수 있는 반도체장치의 비아콘택 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to form a barrier material layer of a via contact for connection with a metal layer having a low resistance and preventing penetration of impurities and infiltrating by heat treatment. The present invention provides a method for forming a via contact in a semiconductor device capable of lowering a via contact resistance by improving the contact between the barrier layer and the barrier material layer.

도1 내지 도2는 일반적인 반도체장치의 비아콘택 형성방법에 의한 공정을 나타낸 단면도이다.1 to 2 are cross-sectional views illustrating a process using a via contact forming method of a general semiconductor device.

도3 내지 도7은 본 발명에 의한 반도체장치의 비아콘택 형성방법에 의한 공정을 단계적으로 나타낸 단면도이다.3 to 7 are cross-sectional views showing a step in a via contact forming method of a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings

10 : 금속층 20 : 절연층10: metal layer 20: insulating layer

30 : 제1장벽물질층 40 : 제2장벽물질층30: first barrier material layer 40: second barrier material layer

50 : 텅스텐 60 : 침투방지막50: tungsten 60: penetration barrier

상기와 같은 목적을 실현하기 위한 본 발명은 반도체기판의 금속층을 감싸는 절연층내에 비아콘택홀을 형성하는 단계와, 비아콘택홀이 형성된 절연층에 Ti를 증착하여 제1장벽물질층을 형성하는 단계와, 제1장벽물질층 위에 비정질실리콘을 증착하고 열처리하여 침투방지막을 형성하는 단계와, 침투방지막위에 TiN을 증착하여 제2장벽물질층을 형성하고 열처리하는 단계와, 제2장벽물질층위에 텅스텐을 증착하여 비아콘택홀을 매립하는 단계로 이루어진다.The present invention for realizing the above object is a step of forming a via contact hole in the insulating layer surrounding the metal layer of the semiconductor substrate, and forming a first barrier material layer by depositing Ti in the insulating layer on which the via contact hole is formed. And depositing and heat treating amorphous silicon on the first barrier material layer to form a penetration barrier layer; depositing TiN on the penetration barrier layer to form and heat treatment a second barrier material layer; and tungsten on the second barrier material layer. Depositing the via contact hole.

상기와 같이 이루어진 본 발명에 의한 방법은 비아 콘택의 장벽물질층 사이에 비정질실리콘을 증착하고 열처리로 실리사이드화하여 침투방지막을 형성함으로써 제1,2장벽물질층과의 접촉성을 향상시키면서 동시에 저항을 낮출 수 있어 텅스텐 증착시 발생되는 불순물이 제1장벽물질층까지 침투되는 것을 방지하여 저항이 낮은 비아콘택을 형성할 수 있다.The method according to the present invention made as described above improves contact with the first and second barrier material layers by simultaneously depositing amorphous silicon between the barrier material layers of the via contacts and silicifying by heat treatment to form a penetration barrier. It can be lowered to prevent the impurities generated during the tungsten deposition to penetrate the first barrier material layer to form a via resistance with low resistance.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도3 내지 도4는 본 발명에 의한 방법에 따라 반도체장치의 비아콘택을 형성하는 실시예로서 공정단계별로 나타낸 단면도이다.3 to 4 are cross-sectional views illustrating the process of forming a via contact of a semiconductor device according to the method of the present invention.

도3에 보는바와 같이, 본 발명은 우선 반도체기판의 금속층(10)을 감싸는 절연층(20)을 증착하고, 마스크를 통해 비아콘택이 형성될 부위를 식각하여 비아콘택홀을 형성하고 그 위에 제1장벽물질층(30)인 Ti층을 200∼300Å 정도의 두께로 증착한다. 그 다음, 확산로에서 SiH4가스를 사용하여 제1장벽물질층(30)인 Ti층 위에 비정질실리콘(62)을 100∼200Å 정도의 두께로 증착한다. 이때, 비정질실리콘(62)은 판상비(aspect ratio)가 큰 비아콘택의 측벽에 증착되는 접합성이 매우 양호한 물질이다.As shown in FIG. 3, the present invention first deposits an insulating layer 20 surrounding a metal layer 10 of a semiconductor substrate, and forms a via contact hole by etching a portion where a via contact is to be formed through a mask. A Ti layer, which is one barrier material layer 30, is deposited to a thickness of about 200 to 300 mW. Subsequently, in the diffusion furnace, amorphous silicon 62 is deposited to a thickness of about 100 to about 200 mW on the Ti layer, which is the first barrier material layer 30, using SiH 4 gas. At this time, the amorphous silicon 62 is a material having very good adhesion deposited on the sidewall of the via contact having a large aspect ratio.

도4는 도3에서 증착한 Ti층과 비정질실리콘과의 접촉성을 향상시키기 위해서 600∼620℃의 질소분위기에서 열처리를 한 상태를 나타낸 단면도이다.4 is a cross-sectional view showing a state in which heat treatment is performed in a nitrogen atmosphere at 600 to 620 ° C. in order to improve contact between the Ti layer deposited in FIG. 3 and amorphous silicon.

도4에서 보는바와 같이 열처리를 함으로서 비정질실리콘(62)이 결정화되면서 하부의 제1장벽물질층(30)인 Ti층과의 상호확산에 의해 Ti와 Si의 계면사이에 저항이 낮은 TiSi2(64)이 형성되어 침투방지막(60)이 형성된다.As shown in FIG. 4, as the amorphous silicon 62 is crystallized by heat treatment, the TiSi 2 (64) having low resistance between the Ti and Si interfaces due to interdiffusion with the Ti layer, which is the first barrier material layer 30, is formed. ) Is formed to form a penetration barrier 60.

도5는 도4의 결과물위에 TiN을 증착시킨 상태를 나타낸 단면도이다.FIG. 5 is a cross-sectional view illustrating a state in which TiN is deposited on the resultant product of FIG. 4.

도5에 보는바와 같이 침투방지막(60)이 형성된 결과물 위에 제2장벽물질층(40)인 TiN을 600Å정도의 두께로 증착한다.As shown in FIG. 5, TiN, the second barrier material layer 40, is deposited on the resultant on which the penetration barrier layer 60 is formed to a thickness of about 600 μs.

도6은 도5의 결과물을 다시 600∼620℃의 질소분위기에서 열처리를 한 상태를 나타낸 단면도이다. 이 결과 비정질실리콘(62)의 Si와 제2장벽물질층(40)의 TiN 계면에 다시 저항이 낮은 TiSi2(64)가 형성되어 접촉력이 좋아지게 된다.FIG. 6 is a cross-sectional view illustrating a state in which the resultant of FIG. 5 is heat-treated again in a nitrogen atmosphere at 600 to 620 ° C. FIG. As a result, TiSi 2 (64) having low resistance is formed again at the Si of the amorphous silicon 62 and the TiN interface of the second barrier material layer 40 to improve the contact force.

따라서 도6에서 보는 바와 같이 비정질실리콘(62)이 계면의 Ti와 반응하여 저항이 낮은 TiSi2가(64)로 되어 침투방지막(60)이 형성된 것을 볼 수 있다.Therefore, as shown in FIG. 6, it can be seen that the amorphous silicon 62 reacts with Ti at the interface to form TiSi 2 (64) having low resistance, thereby forming the penetration barrier layer 60.

도7은 도6의 결과물위에 WF6가스를 이용한 CVD법에 의해 텅스텐을 증착한 상태를 나타낸 단면도이다.7 is a cross-sectional view showing a state in which tungsten is deposited by the CVD method using the WF 6 gas on the resultant of FIG.

도7에 보는바와 같이 상기 제2장벽물질층(40)위에 WF6가스를 이용한 CVD법으로 텅스텐(50)을 증착함으로써 비아콘택홀을 매립하여 비아콘택을 형성한다.As shown in FIG. 7, via contact holes are filled by filling tungsten 50 by CVD using WF 6 gas on the second barrier material layer 40 to form via contacts.

그러므로, 본 발명의 비아 콘택 내에 형성된 TiSi2을 포함한 침투방지막(60)에 의해 제1,2장벽물질층(30,40)과의 접촉성이 양호해지면서 동시에 저항이 낮아져 텅스텐 증착시 발생되는 불순물(예컨대 플루오르)이 제1장벽물질층(30)까지 침투되는 것을 방지하여 저항이 낮은 비아콘택을 형성할 수 있다.Therefore, the impurity generated during the tungsten deposition due to the good contact with the first and second barrier material layers 30 and 40 and the low resistance due to the penetration barrier 60 including TiSi 2 formed in the via contact of the present invention. (Eg, fluorine) may be prevented from penetrating to the first barrier material layer 30 to form a via contact having low resistance.

상기한 바와 같이 본 발명은 장벽물질층을 증착할 때 이후의 텅스텐 증착공정에서 침투되는 플루오르의 침투를 방지하기 위해 장벽물질층 중간에 저항성이 낮은 침투방지막을 형성하여 플루오르의 침투를 방지할 수 있도록 하여 불순물이 장벽물질층으로 침투하여 형성되는 고저항성분을 제거할 수 있을 뿐만아니라 저항이 낮은 침투방지막으로 인해 저항이 매우 낮은 비아콘택을 형성할 수 있으며 소자의 결함 원인이 제거되어 수율을 높일 수 있다는 이점이 있다.As described above, the present invention forms a low-resistance penetration barrier layer in the middle of the barrier material layer to prevent the penetration of fluorine in order to prevent the penetration of fluorine in the subsequent tungsten deposition process when the barrier material layer is deposited. As a result, impurities can penetrate the barrier material layer to remove high-resistance components, and the low-resistance barrier prevents the formation of very low-resistance via contacts. There is an advantage that it is.

Claims (5)

반도체기판의 금속층을 감싸는 절연층내에 비아콘택홀을 형성하는 단계와,Forming a via contact hole in the insulating layer surrounding the metal layer of the semiconductor substrate; 상기 비아콘택홀이 형성된 절연층에 Ti를 증착하여 제1장벽물질층을 형성하는 단계와,Depositing Ti on the insulating layer on which the via contact hole is formed to form a first barrier material layer; 상기 제1장벽물질층 위에 비정질실리콘을 증착하고 열처리하여 침투방지막을 형성하는 단계와,Depositing and heat treating amorphous silicon on the first barrier material layer to form a penetration barrier layer; 상기 침투방지막위에 TiN을 증착하여 제2장벽물질층을 형성하고 열처리하는 단계와,Depositing TiN on the penetration barrier layer to form a second barrier material layer and heat treatment; 상기 제2장벽물질층위에 텅스텐을 증착하여 비아콘택홀을 매립하는 단계로 이루어진 반도체장치의 비아콘택 형성방법.Depositing tungsten on the second barrier material layer to fill via contact holes. 제1항에 있어서, 상기 제1장벽물질층은The method of claim 1, wherein the first barrier material layer 200∼300Å 정도 두께인 것을 특징으로 하는 반도체장치의 비아콘택 형성방법.A via contact forming method for a semiconductor device, characterized in that the thickness of about 200 ~ 300Å. 제1항에 있어서, 상기 제2장벽물질층은The method of claim 1, wherein the second barrier material layer 약 600Å 정도 두께인 것을 특징으로 하는 반도체장치의 비아콘택 형성방법.A via contact forming method for a semiconductor device, characterized in that it is about 600 microns thick. 제1항에 있어서, 상기 침투방지막은According to claim 1, wherein the penetration barrier is 100∼200Å 정도 두께인 것을 특징으로 하는 반도체장치의 비아콘택 형성방법.A via contact forming method for a semiconductor device, characterized in that the thickness of about 100 ~ 200Å. 제1항에 있어서, 상기 열처리공정은The method of claim 1, wherein the heat treatment process 600∼620℃의 질소분위기에서 수행하여 상기 침투방지막 계면에서 비정질실리콘이 결정화되면서 TiSi2층이 형성되도록 하는 것을 특징으로 하는 반도체장치의 비아콘택 형성방법.A method of forming a via contact in a semiconductor device, characterized in that the TiSi 2 layer is formed while the silicon is crystallized at the interface of the penetration barrier by performing the nitrogen atmosphere at 600 to 620 ° C.
KR1019970044923A 1997-08-30 1997-08-30 Method for forming via contact of semiconductor device KR100265968B1 (en)

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