KR20000045351A - Method for forming metal wiring contact - Google Patents
Method for forming metal wiring contact Download PDFInfo
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- KR20000045351A KR20000045351A KR1019980061909A KR19980061909A KR20000045351A KR 20000045351 A KR20000045351 A KR 20000045351A KR 1019980061909 A KR1019980061909 A KR 1019980061909A KR 19980061909 A KR19980061909 A KR 19980061909A KR 20000045351 A KR20000045351 A KR 20000045351A
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- layer
- forming
- metal wiring
- gas
- wiring contact
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 83
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000197 pyrolysis Methods 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 4
- 239000010936 titanium Substances 0.000 abstract 4
- 229910052719 titanium Inorganic materials 0.000 abstract 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract 2
- 238000007740 vapor deposition Methods 0.000 abstract 2
- 238000009933 burial Methods 0.000 abstract 1
- 238000005240 physical vapour deposition Methods 0.000 description 18
- 238000001465 metallisation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 콘택 형성방법에 관한 것으로서, 특히 금속배선 콘택홀 매립시 PVD 및 CVD방법으로 Ti층을 연속적으로 형성하여 2중구조의 희생확산방지막을 형성한 다음, 상기 금속배선 콘택홀을 TiN층을 CVD방법으로 매립하여 상기 금속배선 콘택홀의 입구에 오버행이 형성되는 것을 방지하여 매립 특성을 향상시키고, 콘택 저항 및 누설전류를 감소시켜 소자의 동작속도를 향상시키는 방법에 관한 것이다.The present invention relates to a method for forming a metal interconnection contact of a semiconductor device, and in particular, when a metal wiring contact hole is buried, a Ti layer is continuously formed by PVD and CVD to form a double-diffusion anti-diffusion film, and then the metal wiring contact hole. The present invention relates to a method of improving the buried property by preventing the overhang from being formed in the inlet of the metal wiring contact hole by filling the TiN layer by CVD, and improving the operation speed of the device by reducing the contact resistance and leakage current.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고, 후속 공정을 거쳐 이루어지며 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via hole for wiring with a wiring material, forming a wiring layer, and performing a subsequent process. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착(physical vapor deposition, 이하 PVD 라함)방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법으로 형성된다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and has excellent workability and uses an aluminum alloy as a wiring material for physical vapor deposition (hereinafter referred to as PVD). It is formed by the method of filling the contact hole and the via hole by sputtering of the method.
근래에는 반도체소자의 초고집적화에 따라 금속배선 콘택의 크기는 작아지고, 단차비는 높아져서 스퍼터링에 의한 금속배선의 층덮힘이 불량하게 되어 신뢰성을 얻기가 어려워졌다.In recent years, as the ultra-high integration of semiconductor devices increases, the size of the metal interconnection contact is reduced, and the step ratio is increased, resulting in poor layer coverage of the metal interconnection due to sputtering, making it difficult to obtain reliability.
이하, 첨부된 도면을 참고로하여 종래기술에 대하여 살펴보기로 한다.Hereinafter, the prior art will be described with reference to the accompanying drawings.
도 1 은 종래기술에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a metallization contact forming method of a semiconductor device according to the prior art.
먼저, 워드라인 및 비트라인 등의 하부구조물이 구비되어 있는 반도체기판(11) 상부에 층간절연막(12)을 형성한다.First, an interlayer insulating film 12 is formed on the semiconductor substrate 11 having lower structures such as word lines and bit lines.
그 다음, 상기 층간절연막(12) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 감광막 패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the interlayer insulating film 12 to expose a portion intended to be a metal wiring contact.
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 층간절연막(12)을 식각하여 금속배선 콘택홀을 형성한 후, 상기 감광막 패턴을 제거한다.Next, the interlayer insulating layer 12 is etched using the photoresist pattern as an etching mask to form a metal wiring contact hole, and then the photoresist pattern is removed.
그 다음, 상기 구조 표면에 물리기상증착(physical vapor deposition, 이하 PVD 라 함)방법으로 Ti층(13)을 형성한다.Next, the Ti layer 13 is formed on the surface of the structure by physical vapor deposition (hereinafter referred to as PVD).
다음, 상기 Ti층(13) 상부에 PVD방법으로 TiN층(14)을 형성한다.Next, a TiN layer 14 is formed on the Ti layer 13 by PVD.
그 후, 상기 TiN층(14) 상부에 상기 금속배선 콘택홀을 매립하는 W층(15)을 형성한다.Thereafter, a W layer 15 is formed on the TiN layer 14 to fill the metal wiring contact hole.
상기와 같이 종래기술에 따른 반도체소자의 금속배선 콘택 형성방법은,As described above, the method for forming a metal wiring contact of a semiconductor device according to the prior art,
차세대 반도체소자의 금속배선 콘택은 콘택의 크기가 0.25㎛이하이고, 애스펙트비(aspect ratio)가 10이상으로 매우 좁고 깊어지게 되므로, 기존의 방색대로 PVD Ti 및 TiN층을 형성한 다음 W층을 형성하고, 후속 식각 및 계속해서 Al층과 같은 금속층을 형성하는 데에 제약을 받는다. 상기 PVD Ti 및 TiN층은 층분한 전기적 특성을 확보하기 위하여 수백 Å 두께로 형성하여야 하는데, PVD방법은 층덮힘이 나빠서 금속배선 콘택홀의 상부에 오버행(overhang)이 형성되어 상기 금속배선 콘택홀의 입구가 좁아지게 되고, 도 1 에 도시된 바와 같이 키홀(key hole)이 형성되어 소자의 전기적 특성을 저하시키게 되고, 상기 W층의 식각공정시 식각가스에 의해 큰 손상을 받아 금속배선 콘택홀 내부에는 상기 W층이 거의 남아있지 않게 된다. 한편, 금속배선 콘택에 TiCl4증착용 소오스를 이용한 CVD Ti층을 적용하는 경우, CVD Ti 또는 CVD TiN층은 층덮힘이 우수하여 상기 PVD Ti층 보다도 약 1/4 이하의 얇은 두께를 사용할 수 있으나, 상기 CVD Ti층의 경우 상기 TiCl4소오스 내에 존재하는 Cl기가 고온에서 Ti층 형성시 반도체기판에 영향을 미쳐 상기 반도체기판이 손상되어 콘택저항 및 누설전류가 증가하고, 그에 따른 소자의 특성 및 신뢰성이 저하되는 문제점이 있다.Since the contact size of the next-generation semiconductor device has a contact size of 0.25 μm or less and an aspect ratio of 10 or more, it becomes very narrow and deep, forming a W layer after forming a PVD Ti and TiN layer according to the existing color scheme. And subsequent etching and subsequent formation of a metal layer, such as an Al layer. The PVD Ti and TiN layers should be formed to a thickness of several hundreds of millimeters in order to secure sufficient electrical characteristics. In the PVD method, since the layer covering is bad, an overhang is formed on the upper portion of the metal wiring contact hole so that the entrance of the metal wiring contact hole is formed. As shown in FIG. 1, a key hole is formed to decrease electrical characteristics of the device, and is largely damaged by an etching gas during the etching process of the W layer. There is very little W remaining. On the other hand, when applying a CVD Ti layer using a TiCl 4 deposition source to the metallization contact, the CVD Ti or CVD TiN layer has a superior layer covering can use a thinner thickness of about 1/4 or less than the PVD Ti layer In the case of the CVD Ti layer, the Cl group present in the TiCl 4 source affects the semiconductor substrate when the Ti layer is formed at a high temperature, thereby damaging the semiconductor substrate, thereby increasing contact resistance and leakage current. There is a problem of this deterioration.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속배선 콘택홀 내부에 PVD방법으로 소정 두께의 제1Ti층을 형성하고 계속해서 상기 제1Ti층 상부에 CVD방법으로 제2Ti층을 형성하여 2중구조의 희생확산방지막을 형성하고, 상기 제2Ti층 상부에 상기 금속배선 콘택홀을 매립하는 TiN층을 CVD방법으로 형성하여 상기 금속배선 콘택홀의 상부에서 오버행이 형성되는 것을 방지함으로써 매립 특성을 향상시켜 키홀이 발생하는 것을 방지하고, 콘택 저항 및 누설전류를 감소시키며 그에 따른 소자의 동작 속도 및 수율을 향상시키는 반도체소자의 금속배선 콘택 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the first Ti layer having a predetermined thickness is formed in the metal wiring contact hole by PVD method, and the second Ti layer is formed on the first Ti layer by CVD method. By forming a sacrificial diffusion preventing film of the heavy structure, and by forming a TiN layer for embedding the metal wiring contact hole on the second Ti layer by CVD method to prevent the overhang is formed on the metal wiring contact hole to improve the buried characteristics SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring contact of a semiconductor device, which prevents the occurrence of key holes, reduces contact resistance and leakage current, and improves the operation speed and yield of the device.
도 1 은 종래기술에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.1 is a cross-sectional view showing a metallization contact forming method of a semiconductor device according to the prior art.
도 2 는 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.2 is a cross-sectional view showing a metallization contact forming method of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11, 21 : 반도체기판 12, 22 : 층간절연막11, 21: semiconductor substrate 12, 22: interlayer insulating film
13 : Ti층 14, 25 : TiN층13: Ti layer 14, 25: TiN layer
15 : W층 16 : 키홀(key hole)15: W floor 16: key hole
23 : 제1Ti층 24 : 제2Ti층23: 1st Ti layer 24: 2nd Ti layer
26 : Al층26: Al layer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은,In order to achieve the above object, the metallization contact forming method of a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a metal wiring contact hole exposing a portion intended as a metal wiring contact on a semiconductor substrate on which a predetermined substructure is formed;
상기 금속배선 콘택홀 내부에 PVD방법으로 제1Ti층을 형성하는 공정과,Forming a first Ti layer in the metal wiring contact hole by PVD;
상기 제1Ti층 상부에 PECVD 방법으로 제2Ti층을 형성하는 공정과,Forming a second Ti layer on the first Ti layer by PECVD;
상기 제2Ti층 상부에 CVD방법으로 TiN층을 형성하되, 상기 금속배선 콘택홀이 매립되도록 형성하는 공정과,Forming a TiN layer on the second Ti layer by a CVD method, wherein the metal wiring contact hole is buried;
상기 TiN층 상부에 PVD방법으로 Al층을 형성하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of forming an Al layer on the TiN layer by the PVD method.
이하, 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a metal wiring contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2 는 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도이다.2 is a cross-sectional view illustrating a metal wiring contact forming method of a semiconductor device according to the present invention.
먼저, 워드라인(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물이 형성되어 있는 반도체기판(21) 상부에 층간절연막(22)을 형성한다.First, an interlayer insulating layer 22 is formed on the semiconductor substrate 21 on which lower structures such as word lines (not shown) and bit lines (not shown) are formed.
다음, 상기 층간절연막(22) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 감광막 패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the interlayer insulating layer 22 to expose a portion intended as a metal wiring contact.
그 다음, 상기 감광막 패턴을 식각마스크로 상기 층간절연막(22)을 식각하여 금속배선 콘택홀(도시안됨)을 형성하고, 상기 감광막 패턴을 제거한다.Next, the interlayer insulating layer 22 is etched using the photoresist pattern as an etching mask to form a metal wiring contact hole (not shown), and the photoresist pattern is removed.
다음, 전체표면 상부에 PVD방법을 사용하여 제1Ti층(23)을 10 ∼ 100Å 두께로 형성한다. 이때, 상기 제1Ti층(23)은 콘택홀의 애스펙트비가 크서 층덮힘이 나쁘기 때문에 가능한한 얇게 형성하여 상기 금속배선 콘택홀 상부에서 오버행이 형성되는 것을 방지한다. 또한, 상기 제1Ti층(23)은 후속 PECVD방법을 사용한 Ti층의 형성공정시 TiCl4가스내의 Cl기에 의한 반도체기판(21)의 침식을 방지한다.Next, the first Ti layer 23 is formed to have a thickness of 10 to 100 Å on the entire surface by using the PVD method. In this case, the first Ti layer 23 is formed as thin as possible because the aspect ratio of the contact hole is so large that the layer covering is bad to prevent the overhang is formed on the upper portion of the metal wiring contact hole. In addition, the first Ti layer 23 prevents erosion of the semiconductor substrate 21 by Cl groups in the TiCl 4 gas during the formation of the Ti layer using a subsequent PECVD method.
그 다음, 600 ∼ 800℃의 온도에서 N2, Ar 또는 NH3가스 또는 그 혼합가스 분위기에서 급속열처리(rapid thermal annealing, RTA)공정을 10 ∼ 120초간 실시한다.Then, a rapid thermal annealing (RTA) step is performed for 10 to 120 seconds in a N 2 , Ar or NH 3 gas or a mixed gas atmosphere at a temperature of 600 to 800 ° C.
그리고, 상기 제1Ti층(23) 상부에 플라즈마여기증착방법(plasma enhanced chemical vapor deposition, 이하 PECVD 라 함)방법을 사용하여 제2Ti층(24)을 형성한다. 이때, 상기 제2Ti층(24)은 TiCl4가스를 소오스로 사용하여 400 ∼ 700℃의 온도 및 0.1 ∼ 20torr의 압력하에서 100 ∼ 1000W의 RF 파워를 인가하여 형성하되, 10 ∼ 1000sccm의 Ar가스와 100 ∼ 10000sccm의 H2가스를 증착가스로 사용한다.The second Ti layer 24 is formed on the first Ti layer 23 using a plasma enhanced chemical vapor deposition (PECVD) method. At this time, the second Ti layer 24 is formed using TiCl 4 gas as a source by applying RF power of 100 to 1000 W at a temperature of 400 to 700 ° C. and a pressure of 0.1 to 20 torr, with Ar gas of 10 to 1000 sccm. H 2 gas of 100 to 10000 sccm is used as the deposition gas.
다음, 상기 제2Ti층(24) 상부에 TiN층(25)을 형성하되, 상기 금속배선 콘택홀이 매립되도록 형성한다. 이때, 상기 TiN층(25)은 TiCl4가스를 소오스로 사용하여 400 ∼ 700℃의 온도 및 0.1 ∼ 100torr의 압력하에서 형성하되, 10 ∼ 1000sccm의 Ar가스와 100 ∼ 5000sccm의 N2가스를 증착가스로 사용하고, 100 ∼ 1000sccm의 NH3가스를 반응성가스로 사용하여 열분해방식으로 형성한다. 또한, 100 ∼ 1000W의 RF 파워를 인가하여 PECVD방법으로 형성할 수 있다.Next, a TiN layer 25 is formed on the second Ti layer 24, and the metal wiring contact holes are buried. At this time, the TiN layer 25 is formed using a TiCl 4 gas as a source at a temperature of 400 to 700 ℃ and a pressure of 0.1 to 100 torr, a deposition gas of 10 to 1000 sccm Ar gas and 100 to 5000 sccm N 2 gas 100 to 1000 sccm of NH 3 gas is used as a reactive gas to form a pyrolysis method. In addition, it can be formed by a PECVD method by applying an RF power of 100 ~ 1000W.
그 다음, 상기 TiN층(25)의 비저항이 130 ∼ 170μohm㎝로 다소 높기 때문에 배선저항을 낮추기 위하여 상기 TiN층(25) 상부에 Al층(26)을 PVD방법으로 형성한다.Then, since the specific resistance of the TiN layer 25 is somewhat high, 130 to 170 μohm cm, an Al layer 26 is formed on the TiN layer 25 by the PVD method to lower wiring resistance.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은, 금속배선 콘택홀을 형성하고, PVD방법으로 Ti층을 얇게 형성한 후, 계속해서 CVD방법으로 Ti층을 증착하여 2중구조의 희생확산방지막을 형성한 다음, CVD방법으로 TiN층을 증착하여 상기 금속배선 콘택홀을 매립한 후, 상기 TiN층 상부에 PVD방법으로 Al층을 형성함으로써 상기 금속배선 콘택홀의 입구에 오버행이 형성되어 상기 금속배선 콘택홀 내부에 키홀이 형성되는 것을 방지하여 매립 특성을 향상시키고, 상기 PVD방법으로 Ti층을 형성하여 상기 CVD방법에 의한 Ti층 형성시 반도체기판이 TiCl4가스의 Cl기에 의해 침식되는 것을 방지하여 콘택 저항을 감소시키고 그에 따른 반도체소자의 수율 및 특성을 향상시키는 이점이 있다.As described above, in the method for forming a metal wiring contact of the semiconductor device according to the present invention, the metal wiring contact hole is formed, the Ti layer is thinly formed by the PVD method, and the Ti layer is subsequently deposited by the CVD method. After forming a sacrificial diffusion barrier film, a TiN layer is deposited by CVD to fill the metal wiring contact hole, and then an overhang is formed at the inlet of the metal wiring contact hole by forming an Al layer on the TiN layer by PVD method. To prevent the formation of key holes in the metallization contact hole, thereby improving embedding characteristics, and forming the Ti layer by the PVD method, and the semiconductor substrate is eroded by the Cl group of TiCl 4 gas when the Ti layer is formed by the CVD method. There is an advantage in reducing the contact resistance and thereby improving the yield and characteristics of the semiconductor device.
Claims (6)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400031B1 (en) * | 2001-01-17 | 2003-09-29 | 삼성전자주식회사 | Contact plug of semiconductor device and method of forming the same |
| KR20040038147A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming barrier in semiconductor device |
| KR100502673B1 (en) * | 2002-07-05 | 2005-07-22 | 주식회사 하이닉스반도체 | METHOD FOR FORMING Ti LAYER AND BARRIER METAL LAYER OF SEMICONDUCTOR DEVICE |
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1998
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400031B1 (en) * | 2001-01-17 | 2003-09-29 | 삼성전자주식회사 | Contact plug of semiconductor device and method of forming the same |
| KR100502673B1 (en) * | 2002-07-05 | 2005-07-22 | 주식회사 하이닉스반도체 | METHOD FOR FORMING Ti LAYER AND BARRIER METAL LAYER OF SEMICONDUCTOR DEVICE |
| US7060577B2 (en) | 2002-07-05 | 2006-06-13 | Hynix Semiconductor Inc. | Method for forming metal silicide layer in active area of semiconductor device |
| KR20040038147A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming barrier in semiconductor device |
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