KR100190186B1 - Metalization forming method of semiconductor device - Google Patents

Metalization forming method of semiconductor device Download PDF

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KR100190186B1
KR100190186B1 KR1019950017485A KR19950017485A KR100190186B1 KR 100190186 B1 KR100190186 B1 KR 100190186B1 KR 1019950017485 A KR1019950017485 A KR 1019950017485A KR 19950017485 A KR19950017485 A KR 19950017485A KR 100190186 B1 KR100190186 B1 KR 100190186B1
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thin film
forming
semiconductor device
contact
metal wiring
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KR1019950017485A
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KR970003487A (en
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박홍락
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 티타늄을 함유하는 금속유기화합물의 열분해반응을 이용하여 CVD 방법으로 TiCN 박막을 증착하고 대기와의 접촉 없이 상기 TiCN 박막에 고온열처리공정을 실시한 다음, 대기와의 접촉 없이 질소플라즈마 처리를 실시함으로써 전기 비저항 값을 감소시켜 콘택공정시 콘택저항을 감소시키고 막질을 치밀하게 형성함으로써 단차피복성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, by depositing a TiCN thin film by a CVD method using a thermal decomposition reaction of a metal-organic compound containing titanium, and performing a high temperature heat treatment process on the TiCN thin film without contact with air By reducing the electrical resistivity value by performing nitrogen plasma treatment without contact with the air, the contact resistance is reduced during the contact process and the film quality is densely formed to improve the step coverage by improving the characteristics and reliability of the semiconductor device. It is a technology that enables high integration.

Description

반도체소자의 금속배선 형성방법.Metal wiring formation method of a semiconductor device.

제1도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 개략도.1 is a schematic diagram showing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 명칭* Names of symbols for main parts of the drawings

11 : 반도체기판 13 : 하부절연층11: semiconductor substrate 13: lower insulating layer

15 : 콘택홀 17 : TiCN 박막15 contact hole 17 TiCN thin film

19 : 텅스텐막19: tungsten film

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선 공정시 식각장벽층을 화학기상증착(CVD : Chemical Vapor Deposition, 이하 CVD 라함)방법으로 형성함으로써 막질을 향상시키고 전기저항 값을 감소시켜 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and in particular, by forming an etching barrier layer by a chemical vapor deposition (CVD) method in a metal wiring process, the film quality is improved and the electrical resistance value is reduced. The present invention relates to a technology that enables high integration of semiconductor devices.

종래에는 하부구조물이 형성된 반도체기판 상부에 평탄화된 하부절연층을 형성하고 그 상부에 금속배선 콘택마스크를 이용한 식각공정으로 콘택홀을 형성한 다음, 상기 콘택홀을 통하여 상기 반도체기판의 예정된 부분에 접속되는 알루미늄합금을 물리기상증착(PVD : Physical Vapor Deposition, 이하 PVD라함) 방법으로 형성하고 금속배선마스크를 이용한 식각공정으로 상기 알루미늄합금을 식각 함으로써 금속배선을 형성하였다. 그러나, 반도체소자가 고집적화됨에 따라 상기 금속배선 콘택마스크의 디자인 룰(design rule)이 작아져 상기 콘택홀의 임계크기(CD : Critical Dimension, 이하에서 CD 라 함)가 작아지게 되었고 상기 알루미늄합금은 나쁜 단차 피복비로 인하여 상기 콘택홀의 내부에 보이드(void)가 발생되었다. 그리고, 상기 보이드는 반도체소자의 특성 및 신뢰성을 저하시키는 단점을 발생시킨다.Conventionally, a flattened lower insulating layer is formed on a semiconductor substrate on which a lower structure is formed, and a contact hole is formed by an etching process using a metal wiring contact mask thereon, and then connected to a predetermined portion of the semiconductor substrate through the contact hole. The aluminum alloy was formed by physical vapor deposition (PVD), and the metal alloy was formed by etching the aluminum alloy by an etching process using a metal wiring mask. However, as the semiconductor devices are highly integrated, the design rule of the metallization contact mask is reduced, so that the critical dimension (CD) of the contact hole is reduced, and the aluminum alloy has a bad level. Due to the coverage ratio, voids were generated inside the contact hole. In addition, the voids may cause disadvantages of deteriorating characteristics and reliability of the semiconductor device.

그리고, 상기 종래 기술의 단점을 해결하기 위하여, 상기 알루미늄합금 대신에 CVD 방법으로 증착하여 우수한 단차피복비를 갖는 텅스텐막을 형성하였다. 이 때, 상기 텅스텐막을 형성하기 전에 텅스텐 접합층인 TiN 금속이 PVD 방법으로 형성된 것이다.And, in order to solve the disadvantages of the prior art, instead of the aluminum alloy was deposited by a CVD method to form a tungsten film having an excellent step coverage ratio. At this time, before forming the tungsten film, TiN metal, which is a tungsten bonding layer, is formed by PVD method.

그리고, 반도체소자가 초고집적화됨에따라 상기 텅스텐접합층의 단차피복비를 향상시키기 위하여, 금속유기화합물인 테트라디메틸아미도티타늄(TDMAT : Tetra-Di-Methyl-Amido-Titanium, 이하 TDMAT라 칭함)이나 테트라디에틸아미도티타늄(TDEAT : Tetra-Di-ethyl-Amido-Titanium, 이하 TDEAT 라 칭함)의 열분해 반응을 이용하여 CVD 방법으로 TiCN 박막을 증착하였다.In order to improve the step coverage ratio of the tungsten bonding layer as the semiconductor device is highly integrated, tetradimethylamidotitanium (TDMAT), which is a metal organic compound, is referred to as TDMAT or tetra. TiCN thin films were deposited by CVD using a pyrolysis reaction of diethylamidotitanium (TDEAT: Tetra-Di-ethyl-Amido-Titanium, hereinafter referred to as TDEAT).

그러나, 상기 TiCN 박막의 내부는 상기 CVD 공정시 완전히 분해되지 못하여 게재된 CH3결합이 상당량 존재하기 때문에 막의 구조가 치밀하지 못하며, 전기 비저항이 수천 μΩ-㎝이상의 큰 값을 가지고, 후속열공정중에 상기 CH3결합이 분해되어 반도체소자의 신뢰성을 저하시켜 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.However, the inside of the TiCN thin film is not completely decomposed during the CVD process, and thus the structure of the film is not dense because a large amount of the deposited CH 3 bond exists. The CH 3 bond is decomposed to lower the reliability of the semiconductor device, thereby making it difficult to integrate the semiconductor device.

따라서, 본 발명은 종래 기술의 문제점을 해결하기 위하여, 고온열처리공정과 질소플라즈마 처리공정을 이용하여 막질을 향상시켜 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the metal wiring of the semiconductor device is formed by improving the film quality by using a high temperature heat treatment process and a nitrogen plasma treatment process to improve the reliability of the semiconductor device and enable high integration of the semiconductor device. The purpose is to provide a method.

이상의 목적을 달성하기 위한 본 발명인 반도체소자의 금속배선 형성방법의 특징은, 티타늄금속을 함유하는 금속유기화합물의 열분해반응을 이용한 화학증착방법을 이용하여 금속배선의 식각장벽층이나 텅스텐접합층으로 사용할 수 있는 박막을 형성하는 반도체소자의 금속배선 형성방법에 있어서, CVD 방법으로 TiCN 박막을 증착하는 공정과, 대기와의 접촉 없이 반응로에서 고온열처리공정을 실시하는 공정과, 대기와의 접촉 없이 질소플라즈마 처리를 실시하는 공정을 포함하는데 있다.In order to achieve the above object, the present invention provides a method for forming a metal interconnection of a semiconductor device by using a chemical vapor deposition method using a thermal decomposition reaction of a metal organic compound containing titanium metal as an etch barrier layer or a tungsten junction layer of a metal interconnection. A method of forming a metal wiring of a semiconductor device for forming a thin film capable of forming a thin film, wherein the TiCN thin film is deposited by a CVD method, a high temperature heat treatment step is performed in a reactor without contact with the atmosphere, and nitrogen without contact with the atmosphere. It includes the step of performing a plasma treatment.

또한, 상기 고온열처리공정은 400 ∼ 900℃의 온도에서 실시되는 것과, 상기 고온열처리공정은 불활성기체분위기에서 실시되는 것과, 상기 고온열처리공정은 환원성기체분위기에서 실시되는 것과, 상기 고온열처리공정은 대기압 ∼ 1 mTorr 압력에서 실시되는 것과, 상기 질소플라즈마 처리공정은 상온 ∼ 600℃ 온도에서 실시되는 것과, 상기 질소플라즈마 처리공정은 질소분위기에서 실시되는 것과, 상기 질소플라즈마 처리공정은 질소와 수소의 혼합된 분위기에서 실시되는 것과, 상기 질소플라즈마 처리공정은 1mTorr ∼ 10 Torr 의 압력에서 실시되는 것이다.In addition, the high temperature heat treatment process is carried out at a temperature of 400 ~ 900 ℃, the high temperature heat treatment process is carried out in an inert gas atmosphere, the high temperature heat treatment process is carried out in a reducing gas atmosphere, the high temperature heat treatment process is atmospheric pressure The nitrogen plasma treatment step is carried out at a pressure of ~ 1 mTorr, the nitrogen plasma treatment step is carried out at room temperature ~ 600 ℃, the nitrogen plasma treatment step is carried out in a nitrogen atmosphere, the nitrogen plasma treatment step is a mixture of nitrogen and hydrogen The nitrogen plasma treatment step is carried out in an atmosphere and is carried out at a pressure of 1 mTorr to 10 Torr.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체소자 금속배선 형성방법의 제2특징은, 반도체기판 상부에 하부절연층을 형성하는 공정과, 금속배선 콘택마스크를 이용한 식각공정으로 콘택홀을 형성하는 공정과, 전체표면상부에 CVD 방법으로 TiCN 박막을 증착하는 공정과, 공기 중에 노출 없이 별도의 고온열공정으로 실시하는 공정과, 계속적으로 질소플라즈마 처리하는 공정과, 전체표면상부에 텅스텐막을 형성하는 공정과, 금속배선마스크를 이용한 식각공정으로 상기 텅스텐막과 TiCN 박막을 식각 함으로써 금속배선을 형성하는 공정을 포함하는데 있다.A second aspect of the method for forming a semiconductor device metal wiring of the present invention for achieving the above object is to form a contact hole in the process of forming a lower insulating layer on the semiconductor substrate and an etching process using a metal wiring contact mask. A process of depositing a TiCN thin film on the entire surface by a CVD method, a separate high temperature heat process without exposure to air, a process of continuously performing nitrogen plasma treatment, and forming a tungsten film on the entire surface And a step of forming a metal wiring by etching the tungsten film and the TiCN thin film by an etching process using a metal wiring mask.

또한, 상기 고온열공정 조건은 400∼900℃ 온도, 질소가스분위기 및 대기압∼1mTorr 압력인 것과, 상기 고온열공정 조건은 400∼900℃ 온도, 환원성기체분위기 및 대기압 ∼ 1mTorr 압력인 것과, 상기 고온열공정 조건은 400∼900℃ 온도, 불확성기체분위기 및 대기압 ∼ 1mTorr 압력인 것과, 상기 질소플라즈마 처리조건은 상온∼600℃온도, 질소와 수소의 혼합된 분위기 및 1mTorr ∼ 10 Torr의 압력인 것과, 상기 질소플라즈마 처리조건은 상온∼600℃ 온도, 질소가스분위기 및 1mTorr ∼ 107Torr의 압력인 것이다.In addition, the high temperature heat processing conditions are 400 ~ 900 ℃ temperature, nitrogen gas atmosphere and atmospheric pressure ~ 1mTorr pressure, the high temperature heat processing conditions are 400 ~ 900 ℃ temperature, reducing gas atmosphere and atmospheric pressure ~ 1mTorr pressure, Thermal process conditions are 400 ~ 900 ℃ temperature, uncertainty gas atmosphere and atmospheric pressure ~ 1mTorr pressure, the nitrogen plasma treatment conditions are normal temperature ~ 600 ℃ temperature, mixed atmosphere of nitrogen and hydrogen and 1mTorr ~ 10 Torr pressure , The nitrogen plasma treatment conditions are the room temperature to 600 ℃ temperature, nitrogen gas atmosphere and the pressure of 1mTorr ~ 107 Torr.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a metal wiring forming method of a semiconductor device according to an embodiment of the present invention.

제1도를 참조하면, 반도체기판(11) 상부에 하부절연층(13)을 형성한다. 이때, 상기 하부절연층(13)은 금속배선 형성공정의 전공정에서 형성된 하부구조물(도시안됨)을 절연막으로 평탄화시킨 것이다.Referring to FIG. 1, a lower insulating layer 13 is formed on the semiconductor substrate 11. At this time, the lower insulating layer 13 is to planarize the lower structure (not shown) formed in the previous step of the metal wiring forming process with an insulating film.

그 다음에, 금속배선 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부 절연층(13)을 식각하여 상기 반도체기판(11)의 예정된 부분을 노출시키는 콘택홀(15)을 형성한 후, 전체표면상부에 TiCN 박막(17)을 형성한다. 이때, 상기 TiCN 박막(17)은 금속유기화합물인 TDMAT 이나 TDEAT 의 열분해반응을 이용하여 CVD 방법으로 증착된 것이다.Subsequently, the lower insulating layer 13 is etched by an etching process using a metal wiring contact mask (not shown) to form contact holes 15 exposing predetermined portions of the semiconductor substrate 11. The TiCN thin film 17 is formed on the surface. In this case, the TiCN thin film 17 is deposited by a CVD method using a thermal decomposition reaction of a metal organic compound, TDMAT or TDEAT.

그 다음에, 상기 박막(17)을 노출시키지 않고 증착반응으로나 다른 열처리 반응로에서 고온열처리공정을 실시하여, 상기 TiCN 박막(17) 내부의 CH3결합들을 분해 시켜 제거한다. 이때, 상기 고온열처리공정은 400∼900℃온도의 질소분위기에서 대기압∼1mTorr의 압력으로 실시된 것이다. 여기서, 상기 질소분위기는 불활성기체 또는 환원성기체 분위기로 실시할 수도 있다.Then, a high temperature heat treatment process is performed in a deposition reaction or another heat treatment reactor without exposing the thin film 17 to decompose and remove the CH 3 bonds in the TiCN thin film 17. At this time, the high temperature heat treatment process is carried out at a pressure of atmospheric pressure ~ 1mTorr in a nitrogen atmosphere of 400 ~ 900 ℃ temperature. The nitrogen atmosphere may be performed in an inert gas or a reducing gas atmosphere.

그 다음에, 계속적으로 상기 박막(17)을 플라즈마 발생장치에 장입하여 질소 플라즈마처리를 실시함으로써 상기 질소원자가 상기 TiCN 박막(17)의 Ti 원자의 빈 결합손과 결합하여 상기 TiCN 박막(17)의 막질을 치밀하게 하고 전기 비저항 값을 낮춘다. 이때, 상기 플라즈마처리는 캐패시터형(capacitor type)이나 전도형 (induction type)의 플라즈마 발생장치를 이용하여 실시된 것이다. 그리고, 상기 플라즈마처리는 상기 박막(17)이 증착된 반도체기판(11)의 온도는 상온∼600℃ 로하고 기체분위기는 질소분위기 또는 질소와 수소의 혼합된 분위기로 하며 압력은 1mTorr∼10Torr로 하여 실시된 것이다.Subsequently, the thin film 17 is continuously charged into a plasma generating apparatus and subjected to nitrogen plasma treatment, whereby the nitrogen atom is combined with the empty bond of Ti atoms of the TiCN thin film 17 to form the TiCN thin film 17. The film quality is dense and the electrical resistivity value is lowered. In this case, the plasma treatment is performed using a capacitor type or an induction type plasma generator. In the plasma treatment, the temperature of the semiconductor substrate 11 on which the thin film 17 is deposited is at room temperature to 600 ° C., the gas atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and hydrogen, and the pressure is 1 mTorr to 10 Torr. It was done.

그 다음에, 전체표면상부에 텅스텐막(19)을 형성한다. 그리고, 금속배선마스크(도시 안됨)를 이용한 식각공정으로 상기 텅스텐막(19)과 TiCN 박막(17)을 식각 함으로써 금속배선을 형성한다. 상기 텅스텐막(19)은 이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 단차피복성이 우수하고 전기 비저항 값을 감소시켜 막질이 우수한 TiCN을 형성함으로써 콘택저항을 감소시키고 상기 TiCN 박막을 반도체소자 금속배선의 식각 장벽층이나 텅스텐접합층으로 사용함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 이점이 있다.Then, a tungsten film 19 is formed over the entire surface. In addition, the metal wiring is formed by etching the tungsten film 19 and the TiCN thin film 17 by an etching process using a metal wiring mask (not shown). As described above, the tungsten film 19 is a method for forming a metal wiring of a semiconductor device according to the present invention, which reduces contact resistance by forming TiCN having excellent step coverage and excellent electrical resistivity, thereby forming a film having excellent film quality. By using the TiCN thin film as an etch barrier layer or a tungsten junction layer of the semiconductor device metal wiring, there is an advantage of improving the characteristics and reliability of the semiconductor device and enabling high integration of the semiconductor device.

Claims (8)

반도체기판 상부에 하부절연층을 형성하는 공정과, 상기 구조의 전표면에 CVD 방법으로 TiCN 박막을 증착하는 공정과, 상기 TiCN 박막을 대기와의 접촉 없이 반응로에서 열처리하는 공정과, 상기 TiCN 박막을 대기와의 접촉 없이 질소플라즈마 처리하는 공정과, 상기 구조의 전표면에 금속층을 형성하는 공정과, 상기 텅스텐막과 TiCN 박막을 금속배선마스크를 이용한 식각공정으로 패턴닝하여 금속배선을 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.Forming a lower insulating layer on the semiconductor substrate, depositing a TiCN thin film on the entire surface of the structure by a CVD method, heat treating the TiCN thin film in a reactor without contact with the atmosphere, and forming the TiCN thin film. To form a metal wiring by patterning a nitrogen plasma without contact with air, forming a metal layer on the entire surface of the structure, and etching the tungsten film and the TiCN thin film using an etching process using a metal wiring mask. Metal wiring forming method of a semiconductor device comprising a. 제1항에 있어서, 상기 고온열처리공정은 400∼900℃의 온도에서 실시되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the high temperature heat treatment step is performed at a temperature of 400 ~ 900 ℃. 제1항에 있어서, 상기 고온열처리공정을 불활성기체나 환원성기체 분위기에서 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the high temperature heat treatment is performed in an inert gas or a reducing gas atmosphere. 제1항에 있어서, 상기 고온열처리공정은 대기압∼1mTorr 압력에서 실시되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the high temperature heat treatment is performed at atmospheric pressure to 1 mTorr. 제1항에 있어서, 상기 질소플라즈마 처리공정은 상온∼600℃ 온도에서 실시되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the nitrogen plasma treatment step is performed at room temperature to 600 ℃ temperature. 제1항에 있어서, 상기 질소플라즈마 처리공정을 질소 또는 질소와 수소의 혼합된 분위기에서 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the nitrogen plasma treatment process is performed in a mixed atmosphere of nitrogen or nitrogen and hydrogen. 제1항에 있어서, 상기 질소플라즈마 처리공정은 1mTorr∼10Torr 의 압력에서 실시되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the nitrogen plasma treatment process is performed at a pressure of 1 mTorr to 10 Torr. 제1항에 있어서, 상기 TiCN 박막 형성 공정 전에 금속배선 콘택마스크를 이용한 절연막 식각 공정으로 콘택홀을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, further comprising forming a contact hole by an insulating layer etching process using a metal wiring contact mask before the TiCN thin film forming process.
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